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[openwrt.git] / package / ath9k / src / drivers / net / wireless / ath9k / ath9k.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/io.h>
21
22 #define ATHEROS_VENDOR_ID 0x168c
23
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
29
30 #define AR5416_AR9100_DEVID 0x000b
31
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
34
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
40
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
48
49 #define NBBY 8
50 #ifndef howmany
51 #define howmany(x, y) (((x)+((y)-1))/(y))
52 #endif
53
54 struct ath_tx_status {
55 u_int32_t ts_tstamp;
56 u_int16_t ts_seqnum;
57 u_int8_t ts_status;
58 u_int8_t ts_ratecode;
59 u_int8_t ts_rateindex;
60 int8_t ts_rssi;
61 u_int8_t ts_shortretry;
62 u_int8_t ts_longretry;
63 u_int8_t ts_virtcol;
64 u_int8_t ts_antenna;
65 u_int8_t ts_flags;
66 int8_t ts_rssi_ctl0;
67 int8_t ts_rssi_ctl1;
68 int8_t ts_rssi_ctl2;
69 int8_t ts_rssi_ext0;
70 int8_t ts_rssi_ext1;
71 int8_t ts_rssi_ext2;
72 u_int8_t pad[3];
73 u_int32_t ba_low;
74 u_int32_t ba_high;
75 u_int32_t evm0;
76 u_int32_t evm1;
77 u_int32_t evm2;
78 };
79
80 struct ath_rx_status {
81 u_int32_t rs_tstamp;
82 u_int16_t rs_datalen;
83 u_int8_t rs_status;
84 u_int8_t rs_phyerr;
85 int8_t rs_rssi;
86 u_int8_t rs_keyix;
87 u_int8_t rs_rate;
88 u_int8_t rs_antenna;
89 u_int8_t rs_more;
90 int8_t rs_rssi_ctl0;
91 int8_t rs_rssi_ctl1;
92 int8_t rs_rssi_ctl2;
93 int8_t rs_rssi_ext0;
94 int8_t rs_rssi_ext1;
95 int8_t rs_rssi_ext2;
96 u_int8_t rs_isaggr;
97 u_int8_t rs_moreaggr;
98 u_int8_t rs_num_delims;
99 u_int8_t rs_flags;
100 u_int32_t evm0;
101 u_int32_t evm1;
102 u_int32_t evm2;
103 };
104
105 #define ATH9K_RXERR_CRC 0x01
106 #define ATH9K_RXERR_PHY 0x02
107 #define ATH9K_RXERR_FIFO 0x04
108 #define ATH9K_RXERR_DECRYPT 0x08
109 #define ATH9K_RXERR_MIC 0x10
110
111 #define ATH9K_RX_MORE 0x01
112 #define ATH9K_RX_MORE_AGGR 0x02
113 #define ATH9K_RX_GI 0x04
114 #define ATH9K_RX_2040 0x08
115 #define ATH9K_RX_DELIM_CRC_PRE 0x10
116 #define ATH9K_RX_DELIM_CRC_POST 0x20
117 #define ATH9K_RX_DECRYPT_BUSY 0x40
118
119 #define HAL_RXKEYIX_INVALID ((u_int8_t)-1)
120 #define HAL_TXKEYIX_INVALID ((u_int)-1)
121
122 struct ath_desc {
123 u_int32_t ds_link;
124 u_int32_t ds_data;
125 u_int32_t ds_ctl0;
126 u_int32_t ds_ctl1;
127 u_int32_t ds_hw[20];
128 union {
129 struct ath_tx_status tx;
130 struct ath_rx_status rx;
131 void *stats;
132 } ds_us;
133 void *ds_vdata;
134 } __packed;
135
136 #define ds_txstat ds_us.tx
137 #define ds_rxstat ds_us.rx
138 #define ds_stat ds_us.stats
139
140 #define HAL_TXDESC_CLRDMASK 0x0001
141 #define HAL_TXDESC_NOACK 0x0002
142 #define HAL_TXDESC_RTSENA 0x0004
143 #define HAL_TXDESC_CTSENA 0x0008
144 #define HAL_TXDESC_INTREQ 0x0010
145 #define HAL_TXDESC_VEOL 0x0020
146 #define HAL_TXDESC_EXT_ONLY 0x0040
147 #define HAL_TXDESC_EXT_AND_CTL 0x0080
148 #define HAL_TXDESC_VMF 0x0100
149 #define HAL_TXDESC_FRAG_IS_ON 0x0200
150
151 #define HAL_RXDESC_INTREQ 0x0020
152
153 enum hal_capability_type {
154 HAL_CAP_CIPHER = 0,
155 HAL_CAP_TKIP_MIC,
156 HAL_CAP_TKIP_SPLIT,
157 HAL_CAP_PHYCOUNTERS,
158 HAL_CAP_DIVERSITY,
159 HAL_CAP_PSPOLL,
160 HAL_CAP_TXPOW,
161 HAL_CAP_PHYDIAG,
162 HAL_CAP_MCAST_KEYSRCH,
163 HAL_CAP_TSF_ADJUST,
164 HAL_CAP_WME_TKIPMIC,
165 HAL_CAP_RFSILENT,
166 HAL_CAP_ANT_CFG_2GHZ,
167 HAL_CAP_ANT_CFG_5GHZ
168 };
169
170 struct hal_capabilities {
171 u_int halChanSpreadSupport:1,
172 halChapTuningSupport:1,
173 halMicAesCcmSupport:1,
174 halMicCkipSupport:1,
175 halMicTkipSupport:1,
176 halCipherAesCcmSupport:1,
177 halCipherCkipSupport:1,
178 halCipherTkipSupport:1,
179 halVEOLSupport:1,
180 halBssIdMaskSupport:1,
181 halMcastKeySrchSupport:1,
182 halTsfAddSupport:1,
183 halChanHalfRate:1,
184 halChanQuarterRate:1,
185 halHTSupport:1,
186 halGTTSupport:1,
187 halFastCCSupport:1,
188 halRfSilentSupport:1,
189 halWowSupport:1,
190 halCSTSupport:1,
191 halEnhancedPmSupport:1,
192 halAutoSleepSupport:1,
193 hal4kbSplitTransSupport:1,
194 halWowMatchPatternExact:1;
195 u_int32_t halWirelessModes;
196 u_int16_t halTotalQueues;
197 u_int16_t halKeyCacheSize;
198 u_int16_t halLow5GhzChan, halHigh5GhzChan;
199 u_int16_t halLow2GhzChan, halHigh2GhzChan;
200 u_int16_t halNumMRRetries;
201 u_int16_t halRtsAggrLimit;
202 u_int8_t halTxChainMask;
203 u_int8_t halRxChainMask;
204 u_int16_t halTxTrigLevelMax;
205 u_int16_t halRegCap;
206 u_int8_t halNumGpioPins;
207 u_int8_t halNumAntCfg2GHz;
208 u_int8_t halNumAntCfg5GHz;
209 };
210
211 struct hal_ops_config {
212 int ath_hal_dma_beacon_response_time;
213 int ath_hal_sw_beacon_response_time;
214 int ath_hal_additional_swba_backoff;
215 int ath_hal_6mb_ack;
216 int ath_hal_cwmIgnoreExtCCA;
217 u_int8_t ath_hal_pciePowerSaveEnable;
218 u_int8_t ath_hal_pcieL1SKPEnable;
219 u_int8_t ath_hal_pcieClockReq;
220 u_int32_t ath_hal_pcieWaen;
221 int ath_hal_pciePowerReset;
222 u_int8_t ath_hal_pcieRestore;
223 u_int8_t ath_hal_analogShiftReg;
224 u_int8_t ath_hal_htEnable;
225 u_int32_t ath_hal_ofdmTrigLow;
226 u_int32_t ath_hal_ofdmTrigHigh;
227 u_int32_t ath_hal_cckTrigHigh;
228 u_int32_t ath_hal_cckTrigLow;
229 u_int32_t ath_hal_enableANI;
230 u_int8_t ath_hal_noiseImmunityLvl;
231 u_int32_t ath_hal_ofdmWeakSigDet;
232 u_int32_t ath_hal_cckWeakSigThr;
233 u_int8_t ath_hal_spurImmunityLvl;
234 u_int8_t ath_hal_firStepLvl;
235 int8_t ath_hal_rssiThrHigh;
236 int8_t ath_hal_rssiThrLow;
237 u_int16_t ath_hal_diversityControl;
238 u_int16_t ath_hal_antennaSwitchSwap;
239 int ath_hal_serializeRegMode;
240 int ath_hal_intrMitigation;
241 #define SPUR_DISABLE 0
242 #define SPUR_ENABLE_IOCTL 1
243 #define SPUR_ENABLE_EEPROM 2
244 #define AR_EEPROM_MODAL_SPURS 5
245 #define AR_SPUR_5413_1 1640
246 #define AR_SPUR_5413_2 1200
247 #define AR_NO_SPUR 0x8000
248 #define AR_BASE_FREQ_2GHZ 2300
249 #define AR_BASE_FREQ_5GHZ 4900
250 #define AR_SPUR_FEEQ_BOUND_HT40 19
251 #define AR_SPUR_FEEQ_BOUND_HT20 10
252 int ath_hal_spurMode;
253 u_int16_t ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
254 };
255
256 enum hal_tx_queue {
257 HAL_TX_QUEUE_INACTIVE = 0,
258 HAL_TX_QUEUE_DATA,
259 HAL_TX_QUEUE_BEACON,
260 HAL_TX_QUEUE_CAB,
261 HAL_TX_QUEUE_UAPSD,
262 HAL_TX_QUEUE_PSPOLL
263 };
264
265 #define HAL_NUM_TX_QUEUES 10
266
267 enum hal_tx_queue_subtype {
268 HAL_WME_AC_BK = 0,
269 HAL_WME_AC_BE,
270 HAL_WME_AC_VI,
271 HAL_WME_AC_VO,
272 HAL_WME_UPSD
273 };
274
275 enum hal_tx_queue_flags {
276 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
277 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
278 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
279 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
280 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
281 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
282 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
283 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
284 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
285 };
286
287 struct hal_txq_info {
288 u_int32_t tqi_ver;
289 enum hal_tx_queue_subtype tqi_subtype;
290 enum hal_tx_queue_flags tqi_qflags;
291 u_int32_t tqi_priority;
292 u_int32_t tqi_aifs;
293 u_int32_t tqi_cwmin;
294 u_int32_t tqi_cwmax;
295 u_int16_t tqi_shretry;
296 u_int16_t tqi_lgretry;
297 u_int32_t tqi_cbrPeriod;
298 u_int32_t tqi_cbrOverflowLimit;
299 u_int32_t tqi_burstTime;
300 u_int32_t tqi_readyTime;
301 u_int32_t tqi_compBuf;
302 };
303
304 #define HAL_TQI_NONVAL 0xffff
305
306 #define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
307
308 #define HAL_COMP_BUF_MAX_SIZE 9216
309 #define HAL_COMP_BUF_ALIGN_SIZE 512
310 #define HAL_DECOMP_MASK_SIZE 128
311
312 #define HAL_READY_TIME_LO_BOUND 50
313 #define HAL_READY_TIME_HI_BOUND 96
314
315 enum hal_pkt_type {
316 HAL_PKT_TYPE_NORMAL = 0,
317 HAL_PKT_TYPE_ATIM,
318 HAL_PKT_TYPE_PSPOLL,
319 HAL_PKT_TYPE_BEACON,
320 HAL_PKT_TYPE_PROBE_RESP,
321 HAL_PKT_TYPE_CHIRP,
322 HAL_PKT_TYPE_GRP_POLL,
323 };
324
325 struct hal_tx_queue_info {
326 u_int32_t tqi_ver;
327 enum hal_tx_queue tqi_type;
328 enum hal_tx_queue_subtype tqi_subtype;
329 enum hal_tx_queue_flags tqi_qflags;
330 u_int32_t tqi_priority;
331 u_int32_t tqi_aifs;
332 u_int32_t tqi_cwmin;
333 u_int32_t tqi_cwmax;
334 u_int16_t tqi_shretry;
335 u_int16_t tqi_lgretry;
336 u_int32_t tqi_cbrPeriod;
337 u_int32_t tqi_cbrOverflowLimit;
338 u_int32_t tqi_burstTime;
339 u_int32_t tqi_readyTime;
340 u_int32_t tqi_physCompBuf;
341 u_int32_t tqi_intFlags;
342 };
343
344 enum hal_rx_filter {
345 HAL_RX_FILTER_UCAST = 0x00000001,
346 HAL_RX_FILTER_MCAST = 0x00000002,
347 HAL_RX_FILTER_BCAST = 0x00000004,
348 HAL_RX_FILTER_CONTROL = 0x00000008,
349 HAL_RX_FILTER_BEACON = 0x00000010,
350 HAL_RX_FILTER_PROM = 0x00000020,
351 HAL_RX_FILTER_PROBEREQ = 0x00000080,
352 HAL_RX_FILTER_PSPOLL = 0x00004000,
353 HAL_RX_FILTER_PHYERR = 0x00000100,
354 HAL_RX_FILTER_PHYRADAR = 0x00002000,
355 };
356
357 enum hal_int {
358 HAL_INT_RX = 0x00000001,
359 HAL_INT_RXDESC = 0x00000002,
360 HAL_INT_RXNOFRM = 0x00000008,
361 HAL_INT_RXEOL = 0x00000010,
362 HAL_INT_RXORN = 0x00000020,
363 HAL_INT_TX = 0x00000040,
364 HAL_INT_TXDESC = 0x00000080,
365 HAL_INT_TIM_TIMER = 0x00000100,
366 HAL_INT_TXURN = 0x00000800,
367 HAL_INT_MIB = 0x00001000,
368 HAL_INT_RXPHY = 0x00004000,
369 HAL_INT_RXKCM = 0x00008000,
370 HAL_INT_SWBA = 0x00010000,
371 HAL_INT_BMISS = 0x00040000,
372 HAL_INT_BNR = 0x00100000,
373 HAL_INT_TIM = 0x00200000,
374 HAL_INT_DTIM = 0x00400000,
375 HAL_INT_DTIMSYNC = 0x00800000,
376 HAL_INT_GPIO = 0x01000000,
377 HAL_INT_CABEND = 0x02000000,
378 HAL_INT_CST = 0x10000000,
379 HAL_INT_GTT = 0x20000000,
380 HAL_INT_FATAL = 0x40000000,
381 HAL_INT_GLOBAL = 0x80000000,
382 HAL_INT_BMISC = HAL_INT_TIM
383 | HAL_INT_DTIM | HAL_INT_DTIMSYNC | HAL_INT_CABEND,
384 HAL_INT_COMMON = HAL_INT_RXNOFRM
385 | HAL_INT_RXDESC
386 | HAL_INT_RXEOL
387 | HAL_INT_RXORN
388 | HAL_INT_TXURN
389 | HAL_INT_TXDESC
390 | HAL_INT_MIB
391 | HAL_INT_RXPHY
392 | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO,
393 HAL_INT_NOCARD = 0xffffffff
394 };
395
396 struct hal_rate_table {
397 int rateCount;
398 u_int8_t rateCodeToIndex[256];
399 struct {
400 u_int8_t valid;
401 u_int8_t phy;
402 u_int32_t rateKbps;
403 u_int8_t rateCode;
404 u_int8_t shortPreamble;
405 u_int8_t dot11Rate;
406 u_int8_t controlRate;
407 u_int16_t lpAckDuration;
408 u_int16_t spAckDuration;
409 } info[32];
410 };
411
412 #define HAL_RATESERIES_RTS_CTS 0x0001
413 #define HAL_RATESERIES_2040 0x0002
414 #define HAL_RATESERIES_HALFGI 0x0004
415
416 struct hal_11n_rate_series {
417 u_int Tries;
418 u_int Rate;
419 u_int PktDuration;
420 u_int ChSel;
421 u_int RateFlags;
422 };
423
424 struct hal_channel {
425 u_int16_t channel;
426 u_int32_t channelFlags;
427 u_int8_t privFlags;
428 int8_t maxRegTxPower;
429 int8_t maxTxPower;
430 int8_t minTxPower;
431 };
432
433 #define CHANNEL_CW_INT 0x00002
434 #define CHANNEL_CCK 0x00020
435 #define CHANNEL_OFDM 0x00040
436 #define CHANNEL_2GHZ 0x00080
437 #define CHANNEL_5GHZ 0x00100
438 #define CHANNEL_PASSIVE 0x00200
439 #define CHANNEL_DYN 0x00400
440 #define CHANNEL_HALF 0x04000
441 #define CHANNEL_QUARTER 0x08000
442 #define CHANNEL_HT20 0x10000
443 #define CHANNEL_HT40PLUS 0x20000
444 #define CHANNEL_HT40MINUS 0x40000
445
446 #define CHANNEL_INTERFERENCE 0x01
447 #define CHANNEL_DFS 0x02
448 #define CHANNEL_4MS_LIMIT 0x04
449 #define CHANNEL_DFS_CLEAR 0x08
450 #define CHANNEL_DISALLOW_ADHOC 0x10
451 #define CHANNEL_PER_11D_ADHOC 0x20
452
453 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
454 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
455 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
456 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
457 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
458 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
459 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
460 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
461 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
462 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
463 #define CHANNEL_ALL \
464 (CHANNEL_OFDM| \
465 CHANNEL_CCK| \
466 CHANNEL_2GHZ | \
467 CHANNEL_5GHZ | \
468 CHANNEL_HT20 | \
469 CHANNEL_HT40PLUS | \
470 CHANNEL_HT40MINUS)
471
472 struct hal_channel_internal {
473 u_int16_t channel;
474 u_int32_t channelFlags;
475 u_int8_t privFlags;
476 int8_t maxRegTxPower;
477 int8_t maxTxPower;
478 int8_t minTxPower;
479 bool bssSendHere;
480 u_int8_t gainI;
481 bool iqCalValid;
482 int32_t CalValid;
483 bool oneTimeCalsDone;
484 int8_t iCoff;
485 int8_t qCoff;
486 int16_t rawNoiseFloor;
487 int16_t noiseFloorAdjust;
488 int8_t antennaMax;
489 u_int32_t regDmnFlags;
490 u_int32_t conformanceTestLimit;
491 u_int64_t ah_tsf_last;
492 u_int64_t ah_channel_time;
493 u_int16_t mainSpur;
494 u_int64_t dfsTsf;
495 #ifdef ATH_NF_PER_CHAN
496 struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
497 #endif
498 };
499
500 #define HAL_SPUR_VAL_MASK 0x3FFF
501 #define HAL_SPUR_CHAN_WIDTH 87
502 #define HAL_BIN_WIDTH_BASE_100HZ 3125
503 #define HAL_MAX_BINS_ALLOWED 28
504
505 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
506 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
507 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
508 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
509 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
510 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
511 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
512 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
513 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
514 #define IS_CHAN_PUREG(_c) \
515 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
516 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
517 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
518 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
519 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
520 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
521 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
522 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
523 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
524 #define IS_CHAN_HT40(_c) ((((_c)->channelFlags & CHANNEL_HT40PLUS) != 0) \
525 || (((_c)->channelFlags & CHANNEL_HT40MINUS) != 0))
526 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
527 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
528 #define IS_CHAN_A_5MHZ_SPACED(_c) \
529 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
530 (((_c)->channel % 20) != 0) && \
531 (((_c)->channel % 10) != 0))
532
533 struct hal_keyval {
534 u_int8_t kv_type;
535 u_int8_t kv_pad;
536 u_int16_t kv_len;
537 u_int8_t kv_val[16];
538 u_int8_t kv_mic[8];
539 u_int8_t kv_txmic[8];
540 };
541
542 enum hal_key_type {
543 HAL_KEY_TYPE_CLEAR,
544 HAL_KEY_TYPE_WEP,
545 HAL_KEY_TYPE_AES,
546 HAL_KEY_TYPE_TKIP,
547 };
548
549 enum hal_cipher {
550 HAL_CIPHER_WEP = 0,
551 HAL_CIPHER_AES_OCB = 1,
552 HAL_CIPHER_AES_CCM = 2,
553 HAL_CIPHER_CKIP = 3,
554 HAL_CIPHER_TKIP = 4,
555 HAL_CIPHER_CLR = 5,
556 HAL_CIPHER_MIC = 127
557 };
558
559 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
560 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
561 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
562 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
563 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
564 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
565 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
566 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
567 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
568
569 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
570 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
571 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
572 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
573 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
574 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
575
576 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
577 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
578
579 #define SD_NO_CTL 0xE0
580 #define NO_CTL 0xff
581 #define CTL_MODE_M 7
582 #define CTL_11A 0
583 #define CTL_11B 1
584 #define CTL_11G 2
585 #define CTL_2GHT20 5
586 #define CTL_5GHT20 6
587 #define CTL_2GHT40 7
588 #define CTL_5GHT40 8
589
590 #define AR_EEPROM_MAC(i) (0x1d+(i))
591 #define EEP_SCALE 100
592 #define EEP_DELTA 10
593
594 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
595 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
596 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
597 #define AR_EEPROM_RFSILENT_POLARITY_S 1
598
599 enum {
600 CTRY_DEBUG = 0x1ff,
601 CTRY_DEFAULT = 0
602 };
603
604 enum reg_ext_bitmap {
605 REG_EXT_JAPAN_MIDBAND = 1,
606 REG_EXT_FCC_DFS_HT40 = 2,
607 REG_EXT_JAPAN_NONDFS_HT40 = 3,
608 REG_EXT_JAPAN_DFS_HT40 = 4
609 };
610
611 struct hal_country_entry {
612 u_int16_t countryCode;
613 u_int16_t regDmnEnum;
614 u_int16_t regDmn5G;
615 u_int16_t regDmn2G;
616 u_int8_t isMultidomain;
617 u_int8_t iso[3];
618 };
619
620 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
621 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
622
623 #define SM(_v, _f) (((_v) << _f##_S) & _f)
624 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
625 #define REG_RMW(_a, _r, _set, _clr) \
626 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
627 #define REG_RMW_FIELD(_a, _r, _f, _v) \
628 REG_WRITE(_a, _r, \
629 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
630 #define REG_SET_BIT(_a, _r, _f) \
631 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
632 #define REG_CLR_BIT(_a, _r, _f) \
633 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
634
635 #define HAL_COMP_BUF_MAX_SIZE 9216
636 #define HAL_COMP_BUF_ALIGN_SIZE 512
637
638 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
639
640 #define INIT_AIFS 2
641 #define INIT_CWMIN 15
642 #define INIT_CWMIN_11B 31
643 #define INIT_CWMAX 1023
644 #define INIT_SH_RETRY 10
645 #define INIT_LG_RETRY 10
646 #define INIT_SSH_RETRY 32
647 #define INIT_SLG_RETRY 32
648
649 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
650
651 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
652 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
653
654 #define IEEE80211_WEP_IVLEN 3
655 #define IEEE80211_WEP_KIDLEN 1
656 #define IEEE80211_WEP_CRCLEN 4
657 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
658 (IEEE80211_WEP_IVLEN + \
659 IEEE80211_WEP_KIDLEN + \
660 IEEE80211_WEP_CRCLEN))
661 #define IEEE80211_MAX_LEN (2300 + FCS_LEN + \
662 (IEEE80211_WEP_IVLEN + \
663 IEEE80211_WEP_KIDLEN + \
664 IEEE80211_WEP_CRCLEN))
665
666 #define MAX_REG_ADD_COUNT 129
667 #define MAX_RATE_POWER 63
668
669 #define LE_READ_2(p) \
670 ((u_int16_t) \
671 ((((const u_int8_t *)(p))[0]) | \
672 (((const u_int8_t *)(p))[1] << 8)))
673
674 #define LE_READ_4(p) \
675 ((u_int32_t) \
676 ((((const u_int8_t *)(p))[0]) | \
677 (((const u_int8_t *)(p))[1] << 8) | \
678 (((const u_int8_t *)(p))[2] << 16) | \
679 (((const u_int8_t *)(p))[3] << 24)))
680
681 enum hal_status {
682 HAL_OK = 0,
683 HAL_ENXIO,
684 HAL_ENOMEM,
685 HAL_EIO,
686 HAL_EEMAGIC,
687 HAL_EEVERSION,
688 HAL_EELOCKED,
689 HAL_EEBADSUM,
690 HAL_EEREAD,
691 HAL_EEBADMAC,
692 HAL_EESIZE,
693 HAL_EEWRITE,
694 HAL_EINVAL,
695 HAL_ENOTSUPP,
696 HAL_ESELFTEST,
697 HAL_EINPROGRESS
698 };
699
700 enum hal_power_mode {
701 HAL_PM_AWAKE = 0,
702 HAL_PM_FULL_SLEEP,
703 HAL_PM_NETWORK_SLEEP,
704 HAL_PM_UNDEFINED
705 };
706
707 enum hal_rfgain {
708 HAL_RFGAIN_INACTIVE = 0,
709 HAL_RFGAIN_READ_REQUESTED,
710 HAL_RFGAIN_NEED_CHANGE
711 };
712
713 #define HAL_ANTENNA_MIN_MODE 0
714 #define HAL_ANTENNA_FIXED_A 1
715 #define HAL_ANTENNA_FIXED_B 2
716 #define HAL_ANTENNA_MAX_MODE 3
717
718 struct hal_mib_stats {
719 u_int32_t ackrcv_bad;
720 u_int32_t rts_bad;
721 u_int32_t rts_good;
722 u_int32_t fcs_bad;
723 u_int32_t beacons;
724 };
725
726 enum hal_ant_setting {
727 HAL_ANT_VARIABLE = 0,
728 HAL_ANT_FIXED_A,
729 HAL_ANT_FIXED_B
730 };
731
732 enum hal_opmode {
733 HAL_M_STA = 1,
734 HAL_M_IBSS = 0,
735 HAL_M_HOSTAP = 6,
736 HAL_M_MONITOR = 8
737 };
738
739 enum {
740 HAL_SLOT_TIME_6 = 6,
741 HAL_SLOT_TIME_9 = 9,
742 HAL_SLOT_TIME_20 = 20,
743 };
744
745
746 enum hal_ht_macmode {
747 HAL_HT_MACMODE_20 = 0,
748 HAL_HT_MACMODE_2040 = 1,
749 };
750
751 enum hal_ht_extprotspacing {
752 HAL_HT_EXTPROTSPACING_20 = 0,
753 HAL_HT_EXTPROTSPACING_25 = 1,
754 };
755
756 struct hal_ht_cwm {
757 enum hal_ht_macmode ht_macmode;
758 enum hal_ht_extprotspacing ht_extprotspacing;
759 };
760
761 enum hal_freq_band {
762 HAL_FREQ_BAND_5GHZ = 0,
763 HAL_FREQ_BAND_2GHZ = 1,
764 };
765
766 enum {
767 HAL_TRUE_CHIP = 1
768 };
769
770 enum hal_bus_type {
771 HAL_BUS_TYPE_PCI,
772 HAL_BUS_TYPE_AHB
773 };
774
775 enum hal_ani_cmd {
776 HAL_ANI_PRESENT = 0x1,
777 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
778 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
779 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
780 HAL_ANI_FIRSTEP_LEVEL = 0x10,
781 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
782 HAL_ANI_MODE = 0x40,
783 HAL_ANI_PHYERR_RESET = 0x80,
784 HAL_ANI_ALL = 0xff
785 };
786
787 enum phytype {
788 PHY_DS,
789 PHY_FH,
790 PHY_OFDM,
791 PHY_HT,
792 PHY_MAX
793 };
794 #define PHY_CCK PHY_DS
795
796 enum start_adhoc_option {
797 START_ADHOC_NO_11A,
798 START_ADHOC_PER_11D,
799 START_ADHOC_IN_11A,
800 START_ADHOC_IN_11B,
801 };
802
803 enum hal_tp_scale {
804 HAL_TP_SCALE_MAX = 0,
805 HAL_TP_SCALE_50,
806 HAL_TP_SCALE_25,
807 HAL_TP_SCALE_12,
808 HAL_TP_SCALE_MIN
809 };
810
811 enum ser_reg_mode {
812 SER_REG_MODE_OFF = 0,
813 SER_REG_MODE_ON = 1,
814 SER_REG_MODE_AUTO = 2,
815 };
816
817 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
818 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
819 #define AR_PHY_CCA_MIN_BAD_VALUE -121
820 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
821 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
822
823 #define HAL_NF_CAL_HIST_MAX 5
824 #define NUM_NF_READINGS 6
825
826 struct hal_nfcal_hist {
827 int16_t nfCalBuffer[HAL_NF_CAL_HIST_MAX];
828 u_int8_t currIndex;
829 int16_t privNF;
830 u_int8_t invalidNFcount;
831 };
832
833 struct hal_beacon_state {
834 u_int32_t bs_nexttbtt;
835 u_int32_t bs_nextdtim;
836 u_int32_t bs_intval;
837 #define HAL_BEACON_PERIOD 0x0000ffff
838 #define HAL_BEACON_ENA 0x00800000
839 #define HAL_BEACON_RESET_TSF 0x01000000
840 u_int32_t bs_dtimperiod;
841 u_int16_t bs_cfpperiod;
842 u_int16_t bs_cfpmaxduration;
843 u_int32_t bs_cfpnext;
844 u_int16_t bs_timoffset;
845 u_int16_t bs_bmissthreshold;
846 u_int32_t bs_sleepduration;
847 };
848
849 struct hal_node_stats {
850 u_int32_t ns_avgbrssi;
851 u_int32_t ns_avgrssi;
852 u_int32_t ns_avgtxrssi;
853 u_int32_t ns_avgtxrate;
854 };
855
856 #define HAL_RSSI_EP_MULTIPLIER (1<<7)
857 #define HAL_RATE_EP_MULTIPLIER (1<<7)
858
859 enum hal_gpio_output_mux_type {
860 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT,
861 HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
862 HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
863 HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
864 HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
865 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
866 };
867
868 enum {
869 HAL_RESET_POWER_ON,
870 HAL_RESET_WARM,
871 HAL_RESET_COLD,
872 };
873
874 #define AH_USE_EEPROM 0x1
875 #define AH_IS_HB63 0x2
876
877 struct ath_hal {
878 u_int32_t ah_magic;
879 u_int16_t ah_devid;
880 u_int16_t ah_subvendorid;
881 struct ath_softc *ah_sc;
882 void __iomem *ah_sh;
883 u_int16_t ah_countryCode;
884 u_int32_t ah_macVersion;
885 u_int16_t ah_macRev;
886 u_int16_t ah_phyRev;
887 u_int16_t ah_analog5GhzRev;
888 u_int16_t ah_analog2GhzRev;
889 u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
890 u_int32_t ah_flags;
891 enum hal_opmode ah_opmode;
892 struct hal_ops_config ah_config;
893 struct hal_capabilities ah_caps;
894 int16_t ah_powerLimit;
895 u_int16_t ah_maxPowerLevel;
896 u_int ah_tpScale;
897 u_int16_t ah_currentRD;
898 u_int16_t ah_currentRDExt;
899 u_int16_t ah_currentRDInUse;
900 u_int16_t ah_currentRD5G;
901 u_int16_t ah_currentRD2G;
902 char ah_iso[4];
903 enum start_adhoc_option ah_adHocMode;
904 bool ah_commonMode;
905 struct hal_channel_internal ah_channels[150];
906 u_int ah_nchan;
907 struct hal_channel_internal *ah_curchan;
908 u_int16_t ah_rfsilent;
909 bool ah_rfkillEnabled;
910 bool ah_isPciExpress;
911 u_int16_t ah_txTrigLevel;
912 #ifndef ATH_NF_PER_CHAN
913 struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
914 #endif
915 };
916
917 enum wireless_mode {
918 WIRELESS_MODE_11a = 0,
919 WIRELESS_MODE_11b = 2,
920 WIRELESS_MODE_11g = 3,
921 WIRELESS_MODE_11NA_HT20 = 6,
922 WIRELESS_MODE_11NG_HT20 = 7,
923 WIRELESS_MODE_11NA_HT40PLUS = 8,
924 WIRELESS_MODE_11NA_HT40MINUS = 9,
925 WIRELESS_MODE_11NG_HT40PLUS = 10,
926 WIRELESS_MODE_11NG_HT40MINUS = 11,
927 WIRELESS_MODE_MAX
928 };
929
930 enum {
931 ATH9K_MODE_SEL_11A = 0x00001,
932 ATH9K_MODE_SEL_11B = 0x00002,
933 ATH9K_MODE_SEL_11G = 0x00004,
934 ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
935 ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
936 ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
937 ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
938 ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
939 ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
940 ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
941 ATH9K_MODE_SEL_11G |
942 ATH9K_MODE_SEL_11NG_HT20),
943 ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
944 ATH9K_MODE_SEL_11NA_HT20),
945 ATH9K_MODE_SEL_ALL = 0xffffffff
946 };
947
948 struct chan_centers {
949 u_int16_t synth_center;
950 u_int16_t ctl_center;
951 u_int16_t ext_center;
952 };
953
954 enum hal_status ath_hal_getcapability(struct ath_hal *ah,
955 enum hal_capability_type type,
956 u_int32_t capability,
957 u_int32_t *result);
958 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
959 u_int mode);
960 void ath9k_hw_detach(struct ath_hal *ah);
961 struct ath_hal *ath9k_hw_attach(u_int16_t devid,
962 struct ath_softc *sc,
963 void __iomem *mem,
964 enum hal_status *error);
965 bool ath9k_regd_init_channels(struct ath_hal *ah,
966 struct hal_channel *chans,
967 u_int maxchans, u_int *nchans,
968 u_int8_t *regclassids,
969 u_int maxregids, u_int *nregids,
970 u_int16_t cc, u_int32_t modeSelect,
971 bool enableOutdoor,
972 bool enableExtendedChannels);
973 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
974 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
975 enum hal_int ints);
976 bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
977 struct hal_channel *chan,
978 enum hal_ht_macmode macmode,
979 u_int8_t txchainmask, u_int8_t rxchainmask,
980 enum hal_ht_extprotspacing extprotspacing,
981 bool bChannelChange,
982 enum hal_status *status);
983 bool ath9k_hw_phy_disable(struct ath_hal *ah);
984 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
985 bool *isCalDone);
986 void ath9k_hw_ani_monitor(struct ath_hal *ah,
987 const struct hal_node_stats *stats,
988 struct hal_channel *chan);
989 bool ath9k_hw_calibrate(struct ath_hal *ah,
990 struct hal_channel *chan,
991 u_int8_t rxchainmask,
992 bool longcal,
993 bool *isCalDone);
994 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
995 struct hal_channel *chan);
996 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
997 u_int16_t assocId);
998 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
999 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
1000 u_int16_t assocId);
1001 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
1002 void ath9k_hw_reset_tsf(struct ath_hal *ah);
1003 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
1004 bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
1005 const u_int8_t *mac);
1006 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
1007 u_int16_t entry,
1008 const struct hal_keyval *k,
1009 const u_int8_t *mac,
1010 int xorKey);
1011 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
1012 u_int32_t setting);
1013 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
1014 bool ath9k_hw_intrpend(struct ath_hal *ah);
1015 bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
1016 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
1017 bool bIncTrigLevel);
1018 void ath9k_hw_procmibevent(struct ath_hal *ah,
1019 const struct hal_node_stats *stats);
1020 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
1021 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
1022 bool ath9k_hw_phycounters(struct ath_hal *ah);
1023 bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
1024 bool ath9k_hw_getcapability(struct ath_hal *ah,
1025 enum hal_capability_type type,
1026 u_int32_t capability,
1027 u_int32_t *result);
1028 bool ath9k_hw_setcapability(struct ath_hal *ah,
1029 enum hal_capability_type type,
1030 u_int32_t capability,
1031 u_int32_t setting,
1032 enum hal_status *status);
1033 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
1034 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
1035 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
1036 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
1037 const u_int8_t *mask);
1038 bool ath9k_hw_setpower(struct ath_hal *ah,
1039 enum hal_power_mode mode);
1040 enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
1041 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
1042 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
1043 bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
1044 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
1045 enum hal_ant_setting settings,
1046 struct hal_channel *chan,
1047 u_int8_t *tx_chainmask,
1048 u_int8_t *rx_chainmask,
1049 u_int8_t *antenna_cfgd);
1050 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
1051 enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
1052 u_int32_t cfg);
1053 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
1054 u_int32_t txdp);
1055 bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
1056 u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
1057 const struct hal_rate_table *rates,
1058 u_int32_t frameLen, u_int16_t rateix,
1059 bool shortPreamble);
1060 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1061 struct ath_desc *lastds,
1062 u_int durUpdateEn, u_int rtsctsRate,
1063 u_int rtsctsDuration,
1064 struct hal_11n_rate_series series[],
1065 u_int nseries, u_int flags);
1066 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
1067 struct ath_desc *ds,
1068 u_int burstDuration);
1069 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1070 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
1071 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
1072 u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
1073 u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
1074 struct hal_channel *chan);
1075 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
1076 bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
1077 struct hal_txq_info *qInfo);
1078 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
1079 const struct hal_txq_info *qInfo);
1080 struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
1081 const struct hal_channel *c);
1082 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1083 u_int pktLen, enum hal_pkt_type type,
1084 u_int txPower, u_int keyIx,
1085 enum hal_key_type keyType, u_int flags);
1086 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1087 u_int segLen, bool firstSeg,
1088 bool lastSeg,
1089 const struct ath_desc *ds0);
1090 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1091 u_int32_t *rxc_pcnt,
1092 u_int32_t *rxf_pcnt,
1093 u_int32_t *txf_pcnt);
1094 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1095 void ath9k_hw_beaconinit(struct ath_hal *ah,
1096 u_int32_t next_beacon, u_int32_t beacon_period);
1097 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1098 const struct hal_beacon_state *bs);
1099 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1100 u_int32_t size, u_int flags);
1101 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
1102 void ath9k_hw_rxena(struct ath_hal *ah);
1103 void ath9k_hw_setopmode(struct ath_hal *ah);
1104 bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
1105 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
1106 u_int32_t filter1);
1107 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
1108 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1109 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1110 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1111 enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
1112 struct ath_desc *ds, u_int32_t pa,
1113 struct ath_desc *nds, u_int64_t tsf);
1114 u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q);
1115 enum hal_status ath9k_hw_txprocdesc(struct ath_hal *ah,
1116 struct ath_desc *ds);
1117 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1118 u_int numDelims);
1119 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1120 u_int aggrLen);
1121 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1122 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
1123 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
1124 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1125 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1126 struct ath_desc *ds, u_int vmf);
1127 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
1128 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1129 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
1130 const struct hal_txq_info *qInfo);
1131 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
1132 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
1133 bool ath9k_hw_disable(struct ath_hal *ah);
1134 void ath9k_hw_rfdetach(struct ath_hal *ah);
1135 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1136 struct hal_channel_internal *chan,
1137 struct chan_centers *centers);
1138 bool ath9k_get_channel_edges(struct ath_hal *ah,
1139 u_int16_t flags, u_int16_t *low,
1140 u_int16_t *high);
1141 bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
1142 struct hal_channel *chans,
1143 u_int32_t nchans);
1144 #endif
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