target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_mei_bsp.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_mei_bsp.h
   4 ** PROJECT      : Danube
   5 ** MODULES      : MEI
   6 **
   7 ** DATE         : 1 Jan 2006
   8 ** AUTHOR       : TC Chen
   9 ** DESCRIPTION  : MEI Driver
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Version $Date      $Author     $Comment
  21 *******************************************************************************/
  22 #ifndef _IFXMIPS_MEI_BSP_H_
  23 #define _IFXMIPS_MEI_BSP_H_
  24
  25 /***    Register address offsets, relative to MEI_SPACE_ADDRESS ***/
  26 #define MEI_DATA_XFR_OFFSET                             (0x0000)
  27 #define MEI_VERSION_OFFSET                              (0x0004)
  28 #define MEI_ARC_GP_STAT_OFFSET                          (0x0008)
  29 #define MEI_DATA_XFR_STAT_OFFSET                        (0x000C)
  30 #define MEI_XFR_ADDR_OFFSET                             (0x0010)
  31 #define MEI_MAX_WAIT_OFFSET                             (0x0014)
  32 #define MEI_TO_ARC_INT_OFFSET                           (0x0018)
  33 #define ARC_TO_MEI_INT_OFFSET                           (0x001C)
  34 #define ARC_TO_MEI_INT_MASK_OFFSET                      (0x0020)
  35 #define MEI_DEBUG_WAD_OFFSET                            (0x0024)
  36 #define MEI_DEBUG_RAD_OFFSET                            (0x0028)
  37 #define MEI_DEBUG_DATA_OFFSET                           (0x002C)
  38 #define MEI_DEBUG_DEC_OFFSET                            (0x0030)
  39 #define MEI_CONFIG_OFFSET                               (0x0034)
  40 #define MEI_RST_CONTROL_OFFSET                          (0x0038)
  41 #define MEI_DBG_MASTER_OFFSET                           (0x003C)
  42 #define MEI_CLK_CONTROL_OFFSET                          (0x0040)
  43 #define MEI_BIST_CONTROL_OFFSET                         (0x0044)
  44 #define MEI_BIST_STAT_OFFSET                            (0x0048)
  45 #define MEI_XDATA_BASE_SH_OFFSET                        (0x004c)
  46 #define MEI_XDATA_BASE_OFFSET                           (0x0050)
  47 #define MEI_XMEM_BAR_BASE_OFFSET                        (0x0054)
  48 #define MEI_XMEM_BAR0_OFFSET                            (0x0054)
  49 #define MEI_XMEM_BAR1_OFFSET                            (0x0058)
  50 #define MEI_XMEM_BAR2_OFFSET                            (0x005C)
  51 #define MEI_XMEM_BAR3_OFFSET                            (0x0060)
  52 #define MEI_XMEM_BAR4_OFFSET                            (0x0064)
  53 #define MEI_XMEM_BAR5_OFFSET                            (0x0068)
  54 #define MEI_XMEM_BAR6_OFFSET                            (0x006C))
  55 #define MEI_XMEM_BAR7_OFFSET                            (0x0070)
  56 #define MEI_XMEM_BAR8_OFFSET                            (0x0074)
  57 #define MEI_XMEM_BAR9_OFFSET                            (0x0078)
  58 #define MEI_XMEM_BAR10_OFFSET                           (0x007C)
  59 #define MEI_XMEM_BAR11_OFFSET                           (0x0080)
  60 #define MEI_XMEM_BAR12_OFFSET                           (0x0084)
  61 #define MEI_XMEM_BAR13_OFFSET                           (0x0088)
  62 #define MEI_XMEM_BAR14_OFFSET                           (0x008C)
  63 #define MEI_XMEM_BAR15_OFFSET                           (0x0090)
  64 #define MEI_XMEM_BAR16_OFFSET                           (0x0094)
  65
  66 #define WHILE_DELAY 20000
  67 /*
  68 **      Define where in ME Processor's memory map the Stratify chip lives
  69 */
  70
  71 #define MAXSWAPSIZE             8 * 1024        //8k *(32bits)
  72
  73 //      Mailboxes
  74 #define MSG_LENGTH              16      // x16 bits
  75 #define YES_REPLY               1
  76 #define NO_REPLY                0
  77
  78 #define CMV_TIMEOUT             1000    //jiffies
  79
  80 //  Block size per BAR
  81 #define SDRAM_SEGMENT_SIZE      (64*1024)
  82 // Number of Bar registers
  83 #define MAX_BAR_REGISTERS       (17)
  84
  85 #define XDATA_REGISTER          (15)
  86
  87 #define IFXMIPS_MEI_IOCTL_CMV_WINHOST           IFX_ADSL_IOC_CMV_WINHOST
  88
  89 #define IFXMIPS_MEI_IOCTL_CMV_READ              IFX_ADSL_IOC_CMV_READ
  90 #define IFXMIPS_MEI_IOCTL_CMV_WRITE             IFX_ADSL_IOC_CMV_WRITE
  91
  92 #define IFXMIPS_MEI_IOCTL_GET_BASE_ADDRESS      IFX_ADSL_IOC_GET_BASE_ADDRESS
  93
  94 // ARC register addresss
  95 #define ARC_STATUS                              0x0
  96 #define ARC_LP_START                            0x2
  97 #define ARC_LP_END                              0x3
  98 #define ARC_DEBUG                               0x5
  99 #define ARC_INT_MASK                            0x10A
 100
 101 #define IRAM0_BASE                              (0x00000)
 102 #define IRAM1_BASE                              (0x04000)
 103 #define BRAM_BASE                               (0x0A000)
 104
 105 #define ADSL_BASE                               (0x20000)
 106 #define CRI_BASE                                (ADSL_BASE + 0x11F00)
 107 #define CRI_CCR0                                (CRI_BASE + 0x00)
 108 #define CRI_RST                                 (CRI_BASE + 0x04*4)
 109 #define ADSL_DILV_BASE                          (ADSL_BASE+0x20000)
 110
 111 //
 112 #define IRAM0_ADDR_BIT_MASK   0xFFF
 113 #define IRAM1_ADDR_BIT_MASK   0xFFF
 114 #define BRAM_ADDR_BIT_MASK    0xFFF
 115 #define RX_DILV_ADDR_BIT_MASK 0x1FFF
 116
 117 /***  Bit definitions ***/
 118
 119 #define FALSE   0
 120 #define TRUE    1
 121 #define BIT0    1<<0
 122 #define BIT1    1<<1
 123 #define BIT2    1<<2
 124 #define BIT3    1<<3
 125 #define BIT4    1<<4
 126 #define BIT5    1<<5
 127 #define BIT6    1<<6
 128 #define BIT7    1<<7
 129 #define BIT8    1<<8
 130 #define BIT9    1<<9
 131 #define BIT10   1<<10
 132 #define BIT11   1<<11
 133 #define BIT12   1<<12
 134 #define BIT13   1<<13
 135 #define BIT14   1<<14
 136 #define BIT15   1<<15
 137 #define BIT16   1<<16
 138 #define BIT17   1<<17
 139 #define BIT18   1<<18
 140 #define BIT19   1<<19
 141 #define BIT20   1<<20
 142 #define BIT21   1<<21
 143 #define BIT22   1<<22
 144 #define BIT23   1<<23
 145 #define BIT24   1<<24
 146 #define BIT25   1<<25
 147 #define BIT26   1<<26
 148 #define BIT27   1<<27
 149 #define BIT28   1<<28
 150 #define BIT29   1<<29
 151 #define BIT30   1<<30
 152 #define BIT31   1<<31
 153
 154 // CRI_CCR0 Register definitions
 155 #define CLK_2M_MODE_ENABLE                      BIT6
 156 #define ACL_CLK_MODE_ENABLE                     BIT4
 157 #define FDF_CLK_MODE_ENABLE                     BIT2
 158 #define STM_CLK_MODE_ENABLE                     BIT0
 159
 160 // CRI_RST Register definitions
 161 #define FDF_SRST                                BIT3
 162 #define MTE_SRST                                BIT2
 163 #define FCI_SRST                                BIT1
 164 #define AAI_SRST                                BIT0
 165
 166 //      MEI_TO_ARC_INTERRUPT Register definitions
 167 #define MEI_TO_ARC_INT1                 BIT3
 168 #define MEI_TO_ARC_INT0                 BIT2
 169 #define MEI_TO_ARC_CS_DONE              BIT1    //need to check
 170 #define MEI_TO_ARC_MSGAV                BIT0
 171
 172 //      ARC_TO_MEI_INTERRUPT Register definitions
 173 #define ARC_TO_MEI_INT1                 BIT8
 174 #define ARC_TO_MEI_INT0                 BIT7
 175 #define ARC_TO_MEI_CS_REQ               BIT6
 176 #define ARC_TO_MEI_DBG_DONE             BIT5
 177 #define ARC_TO_MEI_MSGACK               BIT4
 178 #define ARC_TO_MEI_NO_ACCESS            BIT3
 179 #define ARC_TO_MEI_CHECK_AAITX          BIT2
 180 #define ARC_TO_MEI_CHECK_AAIRX          BIT1
 181 #define ARC_TO_MEI_MSGAV                BIT0
 182
 183 //      ARC_TO_MEI_INTERRUPT_MASK Register definitions
 184 #define GP_INT1_EN                      BIT8
 185 #define GP_INT0_EN                      BIT7
 186 #define CS_REQ_EN                       BIT6
 187 #define DBG_DONE_EN                     BIT5
 188 #define MSGACK_EN                       BIT4
 189 #define NO_ACC_EN                       BIT3
 190 #define AAITX_EN                        BIT2
 191 #define AAIRX_EN                        BIT1
 192 #define MSGAV_EN                        BIT0
 193
 194 #define MEI_SOFT_RESET                  BIT0
 195
 196 #define HOST_MSTR                       BIT0
 197
 198 #define JTAG_MASTER_MODE                0x0
 199 #define MEI_MASTER_MODE                 HOST_MSTR
 200
 201 //      MEI_DEBUG_DECODE Register definitions
 202 #define MEI_DEBUG_DEC_MASK              (0x3)
 203 #define MEI_DEBUG_DEC_AUX_MASK          (0x0)
 204 #define MEI_DEBUG_DEC_DMP1_MASK         (0x1)
 205 #define MEI_DEBUG_DEC_DMP2_MASK         (0x2)
 206 #define MEI_DEBUG_DEC_CORE_MASK         (0x3)
 207
 208 #define AUX_STATUS                      (0x0)
 209 //      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
 210 //      page swap requests.
 211 #define MEI_TO_ARC_MAILBOX              (0xDFD0)
 212 #define MEI_TO_ARC_MAILBOXR             (MEI_TO_ARC_MAILBOX + 0x2C)
 213
 214 #define ARC_TO_MEI_MAILBOX              (0xDFA0)
 215 #define ARC_MEI_MAILBOXR                (ARC_TO_MEI_MAILBOX + 0x2C)
 216
 217 // Codeswap request messages are indicated by setting BIT31
 218 #define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK      (0x80000000)
 219
 220 // Clear Eoc messages received are indicated by setting BIT17
 221 #define OMB_CLEAREOC_INTERRUPT_CODE     (0x00020000)
 222
 223 /*
 224 **      Swap page header
 225 */
 226 //      Page must be loaded at boot time if size field has BIT31 set
 227 #define BOOT_FLAG       (BIT31)
 228 #define BOOT_FLAG_MASK  ~BOOT_FLAG
 229
 230 #define FREE_RELOAD             1
 231 #define FREE_SHOWTIME           2
 232 #define FREE_ALL                3
 233
 234 // marcos
 235 #define IFXMIPS_WRITE_REGISTER_L(data,addr)     do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
 236 #define IFXMIPS_READ_REGISTER_L(addr)   (*((volatile u32*)(addr)))
 237 #define SET_BIT(reg, mask)                  reg |= (mask)
 238 #define CLEAR_BIT(reg, mask)                reg &= (~mask)
 239 #define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
 240 #define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
 241 #define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
 242
 243 #define ALIGN_SIZE                          ( 1L<<10 )  //1K size align
 244 #define MEM_ALIGN(addr)             (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
 245
 246 // swap marco
 247 #define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
 248 #define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
 249
 250 //      Swap page header describes size in 32-bit words, load location, and image offset
 251 //      for program and/or data segments
 252 typedef struct _arc_swp_page_hdr {
 253         u32 p_offset;           //Offset bytes of progseg from beginning of image
 254         u32 p_dest;             //Destination addr of progseg on processor
 255         u32 p_size;             //Size in 32-bitwords of program segment
 256         u32 d_offset;           //Offset bytes of dataseg from beginning of image
 257         u32 d_dest;             //Destination addr of dataseg on processor
 258         u32 d_size;             //Size in 32-bitwords of data segment
 259 } ARC_SWP_PAGE_HDR;
 260
 261 /*
 262 **      Swap image header
 263 */
 264 #define GET_PROG        0       //      Flag used for program mem segment
 265 #define GET_DATA        1       //      Flag used for data mem segment
 266
 267 //      Image header contains size of image, checksum for image, and count of
 268 //      page headers. Following that are 'count' page headers followed by
 269 //      the code and/or data segments to be loaded
 270 typedef struct _arc_img_hdr {
 271         u32 size;               //      Size of binary image in bytes
 272         u32 checksum;           //      Checksum for image
 273         u32 count;              //      Count of swp pages in image
 274         ARC_SWP_PAGE_HDR page[1];       //      Should be "count" pages - '1' to make compiler happy
 275 } ARC_IMG_HDR;
 276
 277 typedef struct smmu_mem_info {
 278         int type;
 279         unsigned long nCopy;
 280         unsigned long size;
 281         unsigned char *address;
 282         unsigned char *org_address;
 283 } smmu_mem_info_t;
 284
 285 typedef struct ifxmips_mei_device_private {
 286         int modem_ready;
 287         int arcmsgav;
 288         int cmv_reply;
 289         int cmv_waiting;
 290         // Mei to ARC CMV count, reply count, ARC Indicator count
 291         int indicator_count;
 292         int cmv_count;
 293         int reply_count;
 294         unsigned long image_size;
 295         int nBar;
 296         u16 Recent_indicator[MSG_LENGTH];
 297
 298         u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
 299
 300         smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
 301         ARC_IMG_HDR *img_hdr;
 302         //  to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
 303         wait_queue_head_t wait_queue_arcmsgav;
 304         wait_queue_head_t wait_queue_modemready;
 305         MEI_mutex_t mei_cmv_sema;
 306 } ifxmips_mei_device_private_t;
 307
 308 #endif //_IFXMIPS_MEI_BSP_H_