target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 #ifdef CONFIG_PCI
  25 static void ar71xx_pci_irq_dispatch(void)
  26 {
  27         u32 pending;
  28
  29         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  30                   ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  31
  32         if (pending & PCI_INT_DEV0)
  33                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  34
  35         else if (pending & PCI_INT_DEV1)
  36                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  37
  38         else if (pending & PCI_INT_DEV2)
  39                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  40
  41         else if (pending & PCI_INT_CORE)
  42                 do_IRQ(AR71XX_PCI_IRQ_CORE);
  43
  44         else
  45                 spurious_interrupt();
  46 }
  47
  48 static void ar71xx_pci_irq_unmask(unsigned int irq)
  49 {
  50         irq -= AR71XX_PCI_IRQ_BASE;
  51         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  52                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  53 }
  54
  55 static void ar71xx_pci_irq_mask(unsigned int irq)
  56 {
  57         irq -= AR71XX_PCI_IRQ_BASE;
  58         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  59                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  60 }
  61
  62 static struct irq_chip ar71xx_pci_irq_chip = {
  63         .name           = "AR71XX PCI ",
  64         .mask           = ar71xx_pci_irq_mask,
  65         .unmask         = ar71xx_pci_irq_unmask,
  66         .mask_ack       = ar71xx_pci_irq_mask,
  67 };
  68
  69 static struct irqaction ar71xx_pci_irqaction = {
  70         .handler        = no_action,
  71         .name           = "cascade [AR71XX PCI]",
  72 };
  73
  74 static void __init ar71xx_pci_irq_init(void)
  75 {
  76         int i;
  77
  78         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  79         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  80
  81         for (i = AR71XX_PCI_IRQ_BASE;
  82              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  83                 irq_desc[i].status = IRQ_DISABLED;
  84                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  85                                          handle_level_irq);
  86         }
  87
  88         setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
  89 }
  90 #endif /* CONFIG_PCI */
  91
  92 static void ar71xx_gpio_irq_dispatch(void)
  93 {
  94         u32 pending;
  95
  96         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
  97                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
  98
  99         if (pending)
 100                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
 101         else
 102                 spurious_interrupt();
 103 }
 104
 105 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 106 {
 107         irq -= AR71XX_GPIO_IRQ_BASE;
 108         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 109                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 110 }
 111
 112 static void ar71xx_gpio_irq_mask(unsigned int irq)
 113 {
 114         irq -= AR71XX_GPIO_IRQ_BASE;
 115         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 116                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 117 }
 118
 119 #if 0
 120 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 121 {
 122         /* TODO: implement */
 123         return 0;
 124 }
 125 #else
 126 #define ar71xx_gpio_irq_set_type        NULL
 127 #endif
 128
 129 struct irq_chip ar71xx_gpio_irq_chip = {
 130         .name           = "AR71XX GPIO",
 131         .unmask         = ar71xx_gpio_irq_unmask,
 132         .mask           = ar71xx_gpio_irq_mask,
 133         .mask_ack       = ar71xx_gpio_irq_mask,
 134         .set_type       = ar71xx_gpio_irq_set_type,
 135 };
 136
 137 static struct irqaction ar71xx_gpio_irqaction = {
 138         .handler        = no_action,
 139         .name           = "cascade [AR71XX GPIO]",
 140 };
 141
 142 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 143 #define GPIO_INT_ALL    0xffff
 144
 145 static void __init ar71xx_gpio_irq_init(void)
 146 {
 147         int i;
 148
 149         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 150         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 151
 152         /* setup type of all GPIO interrupts to level sensitive */
 153         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 154
 155         /* setup polarity of all GPIO interrupts to active high */
 156         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 157
 158         for (i = AR71XX_GPIO_IRQ_BASE;
 159              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 160                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 161                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 162                                          handle_level_irq);
 163         }
 164
 165         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 166 }
 167
 168 static void ar71xx_misc_irq_dispatch(void)
 169 {
 170         u32 pending;
 171
 172         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 173             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 174
 175         if (pending & MISC_INT_UART)
 176                 do_IRQ(AR71XX_MISC_IRQ_UART);
 177
 178         else if (pending & MISC_INT_DMA)
 179                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 180
 181         else if (pending & MISC_INT_PERFC)
 182                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 183
 184         else if (pending & MISC_INT_TIMER)
 185                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 186
 187         else if (pending & MISC_INT_OHCI)
 188                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 189
 190         else if (pending & MISC_INT_ERROR)
 191                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 192
 193         else if (pending & MISC_INT_GPIO)
 194                 ar71xx_gpio_irq_dispatch();
 195
 196         else if (pending & MISC_INT_WDOG)
 197                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 198
 199         else
 200                 spurious_interrupt();
 201 }
 202
 203 static void ar71xx_misc_irq_unmask(unsigned int irq)
 204 {
 205         irq -= AR71XX_MISC_IRQ_BASE;
 206         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 207                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 208 }
 209
 210 static void ar71xx_misc_irq_mask(unsigned int irq)
 211 {
 212         irq -= AR71XX_MISC_IRQ_BASE;
 213         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 214                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 215 }
 216
 217 struct irq_chip ar71xx_misc_irq_chip = {
 218         .name           = "AR71XX MISC",
 219         .unmask         = ar71xx_misc_irq_unmask,
 220         .mask           = ar71xx_misc_irq_mask,
 221         .mask_ack       = ar71xx_misc_irq_mask,
 222 };
 223
 224 static struct irqaction ar71xx_misc_irqaction = {
 225         .handler        = no_action,
 226         .name           = "cascade [AR71XX MISC]",
 227 };
 228
 229 static void __init ar71xx_misc_irq_init(void)
 230 {
 231         int i;
 232
 233         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 234         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 235
 236         for (i = AR71XX_MISC_IRQ_BASE;
 237              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 238                 irq_desc[i].status = IRQ_DISABLED;
 239                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 240                                          handle_level_irq);
 241         }
 242
 243         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 244 }
 245
 246 static void ar913x_wmac_irq_dispatch(void)
 247 {
 248         do_IRQ(AR71XX_CPU_IRQ_WMAC);
 249 }
 250
 251 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
 252
 253 asmlinkage void plat_irq_dispatch(void)
 254 {
 255         unsigned long pending;
 256
 257         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 258
 259         if (pending & STATUSF_IP7)
 260                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 261
 262         else if (pending & STATUSF_IP2)
 263                 ar71xx_ip2_irq_handler();
 264
 265         else if (pending & STATUSF_IP4)
 266                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 267
 268         else if (pending & STATUSF_IP5)
 269                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 270
 271         else if (pending & STATUSF_IP3)
 272                 do_IRQ(AR71XX_CPU_IRQ_USB);
 273
 274         else if (pending & STATUSF_IP6)
 275                 ar71xx_misc_irq_dispatch();
 276
 277         else
 278                 spurious_interrupt();
 279 }
 280
 281 void __init arch_init_irq(void)
 282 {
 283         mips_cpu_irq_init();
 284
 285         ar71xx_misc_irq_init();
 286
 287         switch (ar71xx_soc) {
 288         case AR71XX_SOC_AR7130:
 289         case AR71XX_SOC_AR7141:
 290         case AR71XX_SOC_AR7161:
 291 #ifdef CONFIG_PCI
 292                 ar71xx_pci_irq_init();
 293                 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
 294 #endif
 295                 break;
 296         case AR71XX_SOC_AR9130:
 297         case AR71XX_SOC_AR9132:
 298                 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
 299                 break;
 300         default:
 301                 BUG();
 302         }
 303
 304         ar71xx_gpio_irq_init();
 305 }