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c5c5ca932308ed5a3e37505c5c7f841b39e39503
[openwrt.git] / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
3 +++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
4 @@ -728,6 +728,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1015,7 +1028,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-12-14 03:13:55.000000000 +0100
35 +++ linux.dev/arch/mips/Makefile 2006-12-14 04:09:50.000000000 +0100
36 @@ -586,6 +586,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-11-29 22:57:37.000000000 +0100
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-12-14 04:09:50.000000000 +0100
53 @@ -874,7 +874,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -902,6 +901,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-12-14 04:09:50.000000000 +0100
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/autoconf.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
124 +++ linux.dev/arch/mips/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
125 @@ -53,3 +53,4 @@
126 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
127 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
128 obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-12-14 04:09:50.000000000 +0100
133 @@ -0,0 +1,218 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
141 + *
142 + * This program is free software; you can redistribute it and/or modify it
143 + * under the terms of the GNU General Public License as published by the
144 + * Free Software Foundation; either version 2 of the License, or (at your
145 + * option) any later version.
146 + *
147 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
148 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
149 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
150 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
151 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
152 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
153 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
154 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
155 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
156 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
157 + *
158 + * You should have received a copy of the GNU General Public License along
159 + * with this program; if not, write to the Free Software Foundation, Inc.,
160 + * 675 Mass Ave, Cambridge, MA 02139, USA.
161 + *
162 + *
163 + **************************************************************************
164 + * May 2004 rkt, neb
165 + *
166 + * Initial Release
167 + *
168 + *
169 + *
170 + **************************************************************************
171 + */
172 +
173 +#include <linux/autoconf.h>
174 +#include <linux/init.h>
175 +#include <linux/pci.h>
176 +#include <linux/types.h>
177 +#include <linux/delay.h>
178 +
179 +#include <asm/cpu.h>
180 +#include <asm/io.h>
181 +
182 +#include <asm/rc32434/rc32434.h>
183 +#include <asm/rc32434/pci.h>
184 +
185 +#define PCI_ACCESS_READ 0
186 +#define PCI_ACCESS_WRITE 1
187 +
188 +
189 +#define PCI_CFG_SET(bus,slot,func,off) \
190 + (rc32434_pci->pcicfga = (0x80000000 | \
191 + ((bus) << 16) | ((slot)<<11) | \
192 + ((func)<<8) | (off)))
193 +
194 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
195 + unsigned int devfn, unsigned char where,
196 + u32 * data)
197 +{
198 + unsigned int slot = PCI_SLOT(devfn);
199 + u8 func = PCI_FUNC(devfn);
200 +
201 + /* Setup address */
202 + PCI_CFG_SET(bus->number, slot, func, where);
203 + rc32434_sync();
204 +
205 + if (access_type == PCI_ACCESS_WRITE)
206 + rc32434_pci->pcicfgd = *data;
207 + else
208 + *data = rc32434_pci->pcicfgd;
209 +
210 + rc32434_sync();
211 +
212 + return 0;
213 +}
214 +
215 +
216 +/*
217 + * We can't address 8 and 16 bit words directly. Instead we have to
218 + * read/write a 32bit word and mask/modify the data we actually want.
219 + */
220 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
221 + int where, u8 * val)
222 +{
223 + u32 data;
224 + int ret;
225 +
226 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
227 + *val = (data >> ((where & 3) << 3)) & 0xff;
228 + return ret;
229 +}
230 +
231 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
232 + int where, u16 * val)
233 +{
234 + u32 data;
235 + int ret;
236 +
237 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
238 + *val = (data >> ((where & 3) << 3)) & 0xffff;
239 + return ret;
240 +}
241 +
242 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
243 + int where, u32 * val)
244 +{
245 + int ret;
246 + int delay = 1;
247 +
248 + if (bus->number == 0 && PCI_SLOT(devfn) > 21)
249 + return 0;
250 +
251 +retry:
252 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
253 +
254 + /* PCI scan: check for invalid values, device may not have
255 + * finished initializing */
256 +
257 + if (where == PCI_VENDOR_ID) {
258 + if (ret == 0xffffffff || ret == 0x00000000 ||
259 + ret == 0x0000ffff || ret == 0xffff0000) {
260 +
261 + if (delay > 4)
262 + return 0;
263 +
264 + delay *= 2;
265 + msleep(delay);
266 + goto retry;
267 + }
268 + }
269 +
270 + return ret;
271 +}
272 +
273 +static int
274 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
275 + u8 val)
276 +{
277 + u32 data = 0;
278 +
279 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
280 + return -1;
281 +
282 + data = (data & ~(0xff << ((where & 3) << 3))) |
283 + (val << ((where & 3) << 3));
284 +
285 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
286 + return -1;
287 +
288 + return PCIBIOS_SUCCESSFUL;
289 +}
290 +
291 +
292 +static int
293 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
294 + u16 val)
295 +{
296 + u32 data = 0;
297 +
298 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
299 + return -1;
300 +
301 + data = (data & ~(0xffff << ((where & 3) << 3))) |
302 + (val << ((where & 3) << 3));
303 +
304 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
305 + return -1;
306 +
307 +
308 + return PCIBIOS_SUCCESSFUL;
309 +}
310 +
311 +
312 +static int
313 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
314 + u32 val)
315 +{
316 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
317 + return -1;
318 +
319 + return PCIBIOS_SUCCESSFUL;
320 +}
321 +
322 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
323 + int where, int size, u32 * val)
324 +{
325 + switch (size) {
326 + case 1:
327 + return read_config_byte(bus, devfn, where, (u8 *) val);
328 + case 2:
329 + return read_config_word(bus, devfn, where, (u16 *) val);
330 + default:
331 + return read_config_dword(bus, devfn, where, val);
332 + }
333 +}
334 +
335 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
336 + int where, int size, u32 val)
337 +{
338 + switch (size) {
339 + case 1:
340 + return write_config_byte(bus, devfn, where, (u8) val);
341 + case 2:
342 + return write_config_word(bus, devfn, where, (u16) val);
343 + default:
344 + return write_config_dword(bus, devfn, where, val);
345 + }
346 +}
347 +
348 +struct pci_ops rc32434_pci_ops = {
349 + .read = pci_config_read,
350 + .write = pci_config_write,
351 +};
352 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
353 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
354 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-12-14 04:09:50.000000000 +0100
355 @@ -0,0 +1,234 @@
356 +/**************************************************************************
357 + *
358 + * BRIEF MODULE DESCRIPTION
359 + * PCI initialization for IDT EB434 board
360 + *
361 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
362 + *
363 + * This program is free software; you can redistribute it and/or modify it
364 + * under the terms of the GNU General Public License as published by the
365 + * Free Software Foundation; either version 2 of the License, or (at your
366 + * option) any later version.
367 + *
368 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
369 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
370 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
371 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
372 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
373 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
374 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
375 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
377 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
378 + *
379 + * You should have received a copy of the GNU General Public License along
380 + * with this program; if not, write to the Free Software Foundation, Inc.,
381 + * 675 Mass Ave, Cambridge, MA 02139, USA.
382 + *
383 + *
384 + **************************************************************************
385 + * May 2004 rkt, neb
386 + *
387 + * Initial Release
388 + *
389 + *
390 + *
391 + **************************************************************************
392 + */
393 +
394 +#include <linux/autoconf.h>
395 +#include <linux/types.h>
396 +#include <linux/pci.h>
397 +#include <linux/kernel.h>
398 +#include <linux/init.h>
399 +
400 +#include <asm/rc32434/rc32434.h>
401 +#include <asm/rc32434/pci.h>
402 +
403 +#define PCI_ACCESS_READ 0
404 +#define PCI_ACCESS_WRITE 1
405 +
406 +/* define an unsigned array for the PCI registers */
407 +unsigned int korinaCnfgRegs[25] = {
408 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
409 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
410 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
411 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
412 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
413 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
414 +};
415 +static struct resource rc32434_res_pci_mem1;
416 +static struct resource rc32434_res_pci_mem2;
417 +
418 +static struct resource rc32434_res_pci_mem1 = {
419 + .name = "PCI MEM1",
420 + .start = 0x50000000,
421 + .end = 0x5FFFFFFF,
422 + .flags = IORESOURCE_MEM,
423 + .parent = &rc32434_res_pci_mem1,
424 + .sibling = NULL,
425 + .child = &rc32434_res_pci_mem2
426 +};
427 +
428 +static struct resource rc32434_res_pci_mem2 = {
429 + .name = "PCI Mem2",
430 + .start = 0x60000000,
431 + .end = 0x6FFFFFFF,
432 + .flags = IORESOURCE_MEM,
433 + .parent = &rc32434_res_pci_mem1,
434 + .sibling = NULL,
435 + .child = NULL
436 +};
437 +
438 +static struct resource rc32434_res_pci_io1 = {
439 + .name = "PCI I/O1",
440 + .start = 0x18800000,
441 + .end = 0x188FFFFF,
442 + .flags = IORESOURCE_IO,
443 +};
444 +
445 +extern struct pci_ops rc32434_pci_ops;
446 +
447 +#define PCI_MEM1_START PCI_ADDR_START
448 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
449 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
450 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
451 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
452 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
453 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
454 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
455 +
456 +
457 +struct pci_controller rc32434_controller2;
458 +
459 +struct pci_controller rc32434_controller = {
460 + .pci_ops = &rc32434_pci_ops,
461 + .mem_resource = &rc32434_res_pci_mem1,
462 + .io_resource = &rc32434_res_pci_io1,
463 + .mem_offset = 0,
464 + .io_offset = 0,
465 +
466 +};
467 +
468 +#ifdef __MIPSEB__
469 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
470 +#else
471 +#define PCI_ENDIAN_FLAG 0
472 +#endif
473 +
474 +static int __init rc32434_pcibridge_init(void)
475 +{
476 + unsigned int pcicValue, pcicData = 0;
477 + unsigned int dummyRead, pciCntlVal;
478 + int loopCount;
479 + unsigned int pciConfigAddr;
480 +
481 + pcicValue = rc32434_pci->pcic;
482 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
483 + if (!((pcicValue == PCIM_H_EA) ||
484 + (pcicValue == PCIM_H_IA_FIX) ||
485 + (pcicValue == PCIM_H_IA_RR))) {
486 + printk("PCI init error!!!\n");
487 + /* Not in Host Mode, return ERROR */
488 + return -1;
489 + }
490 + /* Enables the Idle Grant mode, Arbiter Parking */
491 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
492 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
493 + /* Zero out the PCI status & PCI Status Mask */
494 + for(;;)
495 + {
496 + pcicData = rc32434_pci->pcis;
497 + if (!(pcicData & PCIS_rip_m))
498 + break;
499 + }
500 +
501 + rc32434_pci->pcis = 0;
502 + rc32434_pci->pcism = 0xFFFFFFFF;
503 + /* Zero out the PCI decoupled registers */
504 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
505 + rc32434_pci->pcidas=0; /* clear the status */
506 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
507 + /* Mask PCI Messaging Interrupts */
508 + rc32434_pci_msg->pciiic = 0;
509 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
510 + rc32434_pci_msg->pciioic = 0;
511 + rc32434_pci_msg->pciioim = 0;
512 +
513 +
514 + /* Setup PCILB0 as Memory Window */
515 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
516 +
517 + /* setup the PCI map address as same as the local address */
518 +
519 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
520 +
521 +
522 + /* Setup PCILBA1 as MEM */
523 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
524 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
525 + rc32434_pci->pcilba[1].a = 0x60000000;
526 + rc32434_pci->pcilba[1].m = 0x60000000;
527 +
528 + /* setup PCILBA2 as IO Window*/
529 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
530 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
531 + rc32434_pci->pcilba[2].a = 0x18C00000;
532 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
533 +
534 + /* setup PCILBA2 as IO Window*/
535 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
536 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
537 +
538 + /* Setup PCILBA3 as IO Window */
539 + rc32434_pci->pcilba[3].a = 0x18800000;
540 + rc32434_pci->pcilba[3].m = 0x18800000;
541 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
542 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
543 +
544 + pciConfigAddr=(unsigned int)(0x80000004);
545 + for(loopCount=0;loopCount<24;loopCount++){
546 + rc32434_pci->pcicfga=pciConfigAddr;
547 + dummyRead=rc32434_pci->pcicfga;
548 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
549 + dummyRead=rc32434_pci->pcicfgd;
550 + pciConfigAddr += 4;
551 + }
552 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
553 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
554 +
555 + pciCntlVal=rc32434_pci->pcic;
556 + pciCntlVal &=~(PCIC_tnr_m);
557 + rc32434_pci->pcic = pciCntlVal;
558 + pciCntlVal=rc32434_pci->pcic;
559 + return 0;
560 +}
561 +
562 +/* Do platform specific device initialization at pci_enable_device() time */
563 +int pcibios_plat_dev_init(struct pci_dev *dev)
564 +{
565 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
566 + /* disable prefetched memory range */
567 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
568 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
569 +
570 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
571 + }
572 + return 0;
573 +}
574 +
575 +static int __init rc32434_pci_init(void)
576 +{
577 + printk("PCI: Initializing PCI\n");
578 +
579 + ioport_resource.start = rc32434_res_pci_io1.start;
580 + ioport_resource.end = rc32434_res_pci_io1.end;
581 +
582 + rc32434_pcibridge_init();
583 +
584 + register_pci_controller(&rc32434_controller);
585 + rc32434_sync();
586 +}
587 +
588 +arch_initcall(rc32434_pci_init);
589 +
590 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
591 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
592 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
593 @@ -0,0 +1,210 @@
594 +/*
595 + * RouterBoard 500 Platform devices
596 + *
597 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
598 + *
599 + * This program is free software; you can redistribute it and/or modify
600 + * it under the terms of the GNU General Public License as published by
601 + * the Free Software Foundation; either version 2 of the License, or
602 + * (at your option) any later version.
603 + *
604 + * This program is distributed in the hope that it will be useful,
605 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
606 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
607 + * GNU General Public License for more details.
608 + *
609 + * $Id$
610 + */
611 +#include <linux/kernel.h>
612 +#include <linux/init.h>
613 +#include <linux/module.h>
614 +#include <linux/ctype.h>
615 +#include <linux/string.h>
616 +#include <linux/platform_device.h>
617 +#include <asm/unaligned.h>
618 +#include <asm/io.h>
619 +
620 +#include <asm/rc32434/rc32434.h>
621 +#include <asm/rc32434/dma.h>
622 +#include <asm/rc32434/dma_v.h>
623 +#include <asm/rc32434/eth.h>
624 +#include <asm/rc32434/rb.h>
625 +
626 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
627 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
628 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
629 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
630 +
631 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
632 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
633 +
634 +static struct resource korina_dev0_res[] = {
635 + {
636 + .name = "korina_regs",
637 + .start = ETH0_PhysicalAddress,
638 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
639 + .flags = IORESOURCE_MEM,
640 + },
641 + {
642 + .name = "korina_rx",
643 + .start = ETH0_DMA_RX_IRQ,
644 + .end = ETH0_DMA_RX_IRQ,
645 + .flags = IORESOURCE_IRQ
646 + },
647 + {
648 + .name = "korina_tx",
649 + .start = ETH0_DMA_TX_IRQ,
650 + .end = ETH0_DMA_TX_IRQ,
651 + .flags = IORESOURCE_IRQ
652 + },
653 + {
654 + .name = "korina_ovr",
655 + .start = ETH0_RX_OVR_IRQ,
656 + .end = ETH0_RX_OVR_IRQ,
657 + .flags = IORESOURCE_IRQ
658 + },
659 + {
660 + .name = "korina_und",
661 + .start = ETH0_TX_UND_IRQ,
662 + .end = ETH0_TX_UND_IRQ,
663 + .flags = IORESOURCE_IRQ
664 + },
665 + {
666 + .name = "korina_dma_rx",
667 + .start = ETH0_RX_DMA_ADDR,
668 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
669 + .flags = IORESOURCE_MEM,
670 + },
671 + {
672 + .name = "korina_dma_tx",
673 + .start = ETH0_TX_DMA_ADDR,
674 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
675 + .flags = IORESOURCE_MEM,
676 + }
677 +};
678 +
679 +static struct korina_device korina_dev0_data = {
680 + .name = "korina0",
681 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
682 +};
683 +
684 +static struct platform_device korina_dev0 = {
685 + .id = 0,
686 + .name = "korina",
687 + .dev.platform_data = &korina_dev0_data,
688 + .resource = korina_dev0_res,
689 + .num_resources = ARRAY_SIZE(korina_dev0_res),
690 +};
691 +
692 +
693 +#define CF_GPIO_NUM 13
694 +
695 +static struct resource cf_slot0_res[] = {
696 + {
697 + .name = "cf_membase",
698 + .flags = IORESOURCE_MEM
699 + },
700 + {
701 + .name = "cf_irq",
702 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
703 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
704 + .flags = IORESOURCE_IRQ
705 + }
706 +};
707 +
708 +static struct cf_device cf_slot0_data = {
709 + .gpio_pin = 13
710 +};
711 +
712 +static struct platform_device cf_slot0 = {
713 + .id = 0,
714 + .name = "rb500-cf",
715 + .dev.platform_data = &cf_slot0_data,
716 + .resource = cf_slot0_res,
717 + .num_resources = ARRAY_SIZE(cf_slot0_res),
718 +};
719 +
720 +/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
721 +static struct resource nand_slot0_res[] = {
722 + {
723 + .name = "nand_membase",
724 + .flags = IORESOURCE_MEM
725 + }
726 +};
727 +
728 +static struct platform_device nand_slot0 = {
729 + .id = 0,
730 + .name = "rb500-nand",
731 + .resource = nand_slot0_res,
732 + .num_resources = ARRAY_SIZE(nand_slot0_res),
733 +};
734 +
735 +
736 +static struct platform_device *rb500_devs[] = {
737 + &korina_dev0,
738 + &nand_slot0,
739 + &cf_slot0
740 +};
741 +
742 +static void __init parse_mac_addr(char* macstr)
743 +{
744 + int i, j;
745 + unsigned char result, value;
746 +
747 + for (i=0; i<6; i++) {
748 + result = 0;
749 + if (i != 5 && *(macstr+2) != ':') {
750 + return;
751 + }
752 + for (j=0; j<2; j++) {
753 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
754 + toupper(*macstr)-'A'+10) < 16) {
755 + result = result*16 + value;
756 + macstr++;
757 + }
758 + else return;
759 + }
760 +
761 + macstr++;
762 + korina_dev0_data.mac[i] = result;
763 + }
764 +}
765 +
766 +
767 +/* DEVICE CONTROLLER 1 */
768 +#define CFG_DC_DEV1 (void*)0xb8010010
769 +#define CFG_DC_DEV2 (void*)0xb8010020
770 +#define CFG_DC_DEVBASE 0x0
771 +#define CFG_DC_DEVMASK 0x4
772 +#define CFG_DC_DEVC 0x8
773 +#define CFG_DC_DEVTC 0xC
774 +
775 +
776 +static int __init plat_setup_devices(void)
777 +{
778 + /* Look for the CF card reader */
779 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
780 + rb500_devs[1] = NULL;
781 + else {
782 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
783 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
784 + }
785 +
786 + /* There is always a NAND device */
787 + nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
788 + nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
789 +
790 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
791 +}
792 +
793 +static int __init setup_kmac(char *s)
794 +{
795 + printk("korina mac = %s\n",s);
796 + parse_mac_addr(s);
797 + return 0;
798 +}
799 +
800 +__setup("kmac=", setup_kmac);
801 +arch_initcall(plat_setup_devices);
802 +
803 +
804 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
805 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
806 +++ linux.dev/arch/mips/rb500/irq.c 2006-12-14 04:14:16.000000000 +0100
807 @@ -0,0 +1,264 @@
808 +/*
809 + * BRIEF MODULE DESCRIPTION
810 + * RC32434 interrupt routines.
811 + *
812 + * Copyright 2002 MontaVista Software Inc.
813 + * Author: MontaVista Software, Inc.
814 + * stevel@mvista.com or source@mvista.com
815 + *
816 + * This program is free software; you can redistribute it and/or modify it
817 + * under the terms of the GNU General Public License as published by the
818 + * Free Software Foundation; either version 2 of the License, or (at your
819 + * option) any later version.
820 + *
821 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
822 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
823 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
824 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
825 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
826 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
827 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
828 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
829 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
830 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
831 + *
832 + * You should have received a copy of the GNU General Public License along
833 + * with this program; if not, write to the Free Software Foundation, Inc.,
834 + * 675 Mass Ave, Cambridge, MA 02139, USA.
835 + */
836 +
837 +#include <linux/errno.h>
838 +#include <linux/init.h>
839 +#include <linux/kernel_stat.h>
840 +#include <linux/module.h>
841 +#include <linux/signal.h>
842 +#include <linux/sched.h>
843 +#include <linux/types.h>
844 +#include <linux/interrupt.h>
845 +#include <linux/ioport.h>
846 +#include <linux/timex.h>
847 +#include <linux/slab.h>
848 +#include <linux/random.h>
849 +#include <linux/delay.h>
850 +
851 +#include <asm/bitops.h>
852 +#include <asm/bootinfo.h>
853 +#include <asm/io.h>
854 +#include <asm/irq.h>
855 +#include <asm/time.h>
856 +#include <asm/mipsregs.h>
857 +#include <asm/system.h>
858 +#include <asm/rc32434/rc32434.h>
859 +#include <asm/rc32434/gpio.h>
860 +
861 +extern void set_debug_traps(void);
862 +extern irq_cpustat_t irq_stat [NR_CPUS];
863 +unsigned int local_bh_count[NR_CPUS];
864 +unsigned int local_irq_count[NR_CPUS];
865 +
866 +static unsigned int startup_irq(unsigned int irq);
867 +static void rb500_end_irq(unsigned int irq_nr);
868 +static void mask_and_ack_irq(unsigned int irq_nr);
869 +static void rb500_enable_irq(unsigned int irq_nr);
870 +static void rb500_disable_irq(unsigned int irq_nr);
871 +
872 +extern void __init init_generic_irq(void);
873 +
874 +typedef struct {
875 + u32 mask; /* mask of valid bits in pending/mask registers */
876 + volatile u32 *base_addr;
877 +} intr_group_t;
878 +
879 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
880 +
881 +#if (NR_IRQS < RC32434_NR_IRQS)
882 +#error Too little irqs defined. Did you override <asm/irq.h> ?
883 +#endif
884 +
885 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
886 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
887 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
888 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
889 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
890 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
891 +};
892 +
893 +#define READ_PEND(base) (*(base))
894 +#define READ_MASK(base) (*(base + 2))
895 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
896 +
897 +static inline int irq_to_group(unsigned int irq_nr)
898 +{
899 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
900 +}
901 +
902 +static inline int group_to_ip(unsigned int group)
903 +{
904 + return group + 2;
905 +}
906 +
907 +static inline void enable_local_irq(unsigned int ip)
908 +{
909 + int ipnum = 0x100 << ip;
910 + clear_c0_cause(ipnum);
911 + set_c0_status(ipnum);
912 +}
913 +
914 +static inline void disable_local_irq(unsigned int ip)
915 +{
916 + int ipnum = 0x100 << ip;
917 + clear_c0_status(ipnum);
918 +}
919 +
920 +static inline void ack_local_irq(unsigned int ip)
921 +{
922 + int ipnum = 0x100 << ip;
923 + clear_c0_cause(ipnum);
924 +}
925 +
926 +static void rb500_enable_irq(unsigned int irq_nr)
927 +{
928 + int ip = irq_nr - GROUP0_IRQ_BASE;
929 + unsigned int group, intr_bit;
930 + volatile unsigned int *addr;
931 +
932 +
933 + if (ip < 0)
934 + enable_local_irq(irq_nr);
935 + else {
936 + group = ip >> 5;
937 +
938 + ip &= (1<<5)-1;
939 + intr_bit = 1 << ip;
940 +
941 + enable_local_irq(group_to_ip(group));
942 +
943 + addr = intr_group[group].base_addr;
944 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
945 + }
946 +}
947 +
948 +static void rb500_disable_irq(unsigned int irq_nr)
949 +{
950 + int ip = irq_nr - GROUP0_IRQ_BASE;
951 + unsigned int group, intr_bit, mask;
952 + volatile unsigned int *addr;
953 +
954 + if (ip < 0) {
955 + disable_local_irq(irq_nr);
956 + }else{
957 + group = ip >> 5;
958 +
959 + ip &= (1<<5) -1;
960 + intr_bit = 1 << ip;
961 + addr = intr_group[group].base_addr;
962 + mask = READ_MASK(addr);
963 + mask |= intr_bit;
964 + WRITE_MASK(addr,mask);
965 +
966 + /*
967 + * if there are no more interrupts enabled in this
968 + * group, disable corresponding IP
969 + */
970 + if (mask == intr_group[group].mask)
971 + disable_local_irq(group_to_ip(group));
972 + }
973 +}
974 +
975 +static unsigned int startup_irq(unsigned int irq_nr)
976 +{
977 + rb500_enable_irq(irq_nr);
978 + return 0;
979 +}
980 +
981 +static void shutdown_irq(unsigned int irq_nr)
982 +{
983 + rb500_disable_irq(irq_nr);
984 + return;
985 +}
986 +
987 +static void mask_and_ack_irq(unsigned int irq_nr)
988 +{
989 + rb500_disable_irq(irq_nr);
990 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
991 +}
992 +
993 +static void rb500_end_irq(unsigned int irq_nr)
994 +{
995 +
996 + int ip = irq_nr - GROUP0_IRQ_BASE;
997 + unsigned int intr_bit, group;
998 + volatile unsigned int *addr;
999 +
1000 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1001 + printk("warning: end_irq %d did not enable (%x)\n",
1002 + irq_nr, irq_desc[irq_nr].status);
1003 + return;
1004 + }
1005 +
1006 + if (ip < 0) {
1007 + enable_local_irq(irq_nr);
1008 + } else {
1009 + group = ip >> 5;
1010 +
1011 + ip &= (1 << 5) - 1;
1012 + intr_bit = 1 << ip;
1013 +
1014 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1015 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1016 + }
1017 +
1018 + enable_local_irq(group_to_ip(group));
1019 +
1020 + addr = intr_group[group].base_addr;
1021 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1022 + }
1023 +}
1024 +
1025 +static struct hw_interrupt_type rc32434_irq_type = {
1026 + .typename = "RB500",
1027 + .startup = startup_irq,
1028 + .shutdown = shutdown_irq,
1029 + .enable = rb500_enable_irq,
1030 + .disable = rb500_disable_irq,
1031 + .ack = mask_and_ack_irq,
1032 + .end = rb500_end_irq,
1033 +};
1034 +
1035 +
1036 +void __init arch_init_irq(void)
1037 +{
1038 + int i;
1039 +
1040 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1041 + memset(irq_desc, 0, sizeof(irq_desc));
1042 +
1043 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1044 + irq_desc[i].status = IRQ_DISABLED;
1045 + irq_desc[i].action = NULL;
1046 + irq_desc[i].depth = 1;
1047 + irq_desc[i].chip = &rc32434_irq_type;
1048 + spin_lock_init(&irq_desc[i].lock);
1049 + }
1050 +}
1051 +
1052 +/* Main Interrupt dispatcher */
1053 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1054 +{
1055 + unsigned int ip, pend, group;
1056 + volatile unsigned int *addr;
1057 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1058 +
1059 + if (cp0_cause & CAUSEF_IP7) {
1060 + ll_timer_interrupt(7);
1061 + } else if ((ip = (cp0_cause & 0x7c00))) {
1062 + group = 21 - rc32434_clz(ip);
1063 +
1064 + addr = intr_group[group].base_addr;
1065 +
1066 + pend = READ_PEND(addr);
1067 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1068 + pend = 39 - rc32434_clz(pend);
1069 + do_IRQ((group << 5) + pend);
1070 + }
1071 +}
1072 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1073 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1074 +++ linux.dev/arch/mips/rb500/Makefile 2006-12-14 04:09:50.000000000 +0100
1075 @@ -0,0 +1,5 @@
1076 +#
1077 +# Makefile for the RB500 board specific parts of the kernel
1078 +#
1079 +
1080 +obj-y += irq.o time.o setup.o serial.o prom.o misc.o devices.o
1081 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1082 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1083 +++ linux.dev/arch/mips/rb500/misc.c 2006-12-14 04:09:50.000000000 +0100
1084 @@ -0,0 +1,56 @@
1085 +#include <linux/module.h>
1086 +#include <linux/kernel.h> /* printk() */
1087 +#include <linux/types.h> /* size_t */
1088 +#include <linux/pci.h>
1089 +#include <linux/spinlock.h>
1090 +#include <asm/rc32434/rb.h>
1091 +
1092 +#define GPIO_BADDR 0xb8050000
1093 +
1094 +
1095 +static volatile unsigned char *devCtl3Base = 0;
1096 +static unsigned char latchU5State = 0;
1097 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1098 +
1099 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1100 + unsigned flags, data;
1101 + unsigned i = 0;
1102 + spin_lock_irqsave(&clu5Lock, flags);
1103 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1104 + for (i = 0; i != len; ++i) {
1105 + if (val & (1 << i)) data |= (1 << (i + bit));
1106 + else data &= ~(1 << (i + bit));
1107 + }
1108 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1109 + spin_unlock_irqrestore(&clu5Lock, flags);
1110 +}
1111 +
1112 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1113 + unsigned flags;
1114 + spin_lock_irqsave(&clu5Lock, flags);
1115 + latchU5State = (latchU5State | orMask) & ~nandMask;
1116 + if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1117 + KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1118 + *devCtl3Base = latchU5State;
1119 + spin_unlock_irqrestore(&clu5Lock, flags);
1120 +}
1121 +
1122 +u32 gpio_get(gpio_func func)
1123 +{
1124 + return readl((void *) GPIO_BADDR + func);
1125 +}
1126 +
1127 +void gpio_set(gpio_func func, u32 mask, u32 value)
1128 +{
1129 + u32 val = readl((void *) GPIO_BADDR + func);
1130 +
1131 + val &= ~mask;
1132 + val |= value & mask;
1133 +
1134 + writel(val, (void *) GPIO_BADDR + func);
1135 +}
1136 +
1137 +EXPORT_SYMBOL(gpio_set);
1138 +EXPORT_SYMBOL(gpio_get);
1139 +EXPORT_SYMBOL(set434Reg);
1140 +EXPORT_SYMBOL(changeLatchU5);
1141 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1142 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1143 +++ linux.dev/arch/mips/rb500/prom.c 2006-12-14 05:15:05.000000000 +0100
1144 @@ -0,0 +1,161 @@
1145 +/*
1146 +* prom.c
1147 +**********************************************************************
1148 +* P . Sadik Oct 10, 2003
1149 +*
1150 +* Started change log
1151 +* idt_cpu_freq is make a kernel configuration parameter
1152 +* idt_cpu_freq is exported so that other modules can use it.
1153 +* Code cleanup
1154 +**********************************************************************
1155 +* P. Sadik Oct 20, 2003
1156 +*
1157 +* Removed NVRAM code from here, since they are already available under
1158 +* nvram directory.
1159 +* Added serial port initialisation.
1160 +**********************************************************************
1161 +**********************************************************************
1162 +* P. Sadik Oct 30, 2003
1163 +*
1164 +* Added reset_cons_port
1165 +**********************************************************************
1166 +
1167 + P.Christeas, 2005-2006
1168 + Port to 2.6, add 2.6 cmdline parsing
1169 +
1170 +*/
1171 +
1172 +#include <linux/autoconf.h>
1173 +#include <linux/init.h>
1174 +#include <linux/mm.h>
1175 +#include <linux/module.h>
1176 +#include <linux/string.h>
1177 +#include <linux/console.h>
1178 +#include <asm/bootinfo.h>
1179 +#include <linux/bootmem.h>
1180 +#include <linux/ioport.h>
1181 +#include <linux/blkdev.h>
1182 +#include <asm/rc32434/ddr.h>
1183 +
1184 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1185 +extern void __init setup_serial_port(void);
1186 +
1187 +unsigned int idt_cpu_freq = 132000000;
1188 +EXPORT_SYMBOL(idt_cpu_freq);
1189 +unsigned int board_type = 500;
1190 +EXPORT_SYMBOL(board_type);
1191 +unsigned int gpio_bootup_state = 0;
1192 +EXPORT_SYMBOL(gpio_bootup_state);
1193 +
1194 +
1195 +char mips_mac_address[18] = "08:00:06:05:40:01";
1196 +EXPORT_SYMBOL(mips_mac_address);
1197 +
1198 +/* what to append to cmdline when button is [not] pressed */
1199 +#define GPIO_INIT_NOBUTTON ""
1200 +#define GPIO_INIT_BUTTON " 2"
1201 +
1202 +#ifdef CONFIG_MIKROTIK_RB500
1203 +unsigned soft_reboot = 0;
1204 +EXPORT_SYMBOL(soft_reboot);
1205 +#endif
1206 +
1207 +#define SR_NMI 0x00180000 /* NMI */
1208 +#define SERIAL_SPEED_ENTRY 0x00000001
1209 +
1210 +#ifdef CONFIG_REMOTE_DEBUG
1211 +extern int remote_debug;
1212 +#endif
1213 +
1214 +extern unsigned long mips_machgroup;
1215 +extern unsigned long mips_machtype;
1216 +
1217 +#define FREQ_TAG "HZ="
1218 +#define GPIO_TAG "gpio="
1219 +#define KMAC_TAG "kmac="
1220 +#define MEM_TAG "mem="
1221 +#define BOARD_TAG "board="
1222 +#define IGNORE_CMDLINE_MEM 1
1223 +#define DEBUG_DDR
1224 +
1225 +void parse_soft_settings(unsigned *ptr, unsigned size);
1226 +void parse_hard_settings(unsigned *ptr, unsigned size);
1227 +
1228 +void __init prom_setup_cmdline(void);
1229 +
1230 +void __init prom_init(void)
1231 +{
1232 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1233 + phys_t memsize = 0-ddr->ddrmask;
1234 +
1235 + /* this should be the very first message, even before serial is properly initialized */
1236 + prom_setup_cmdline();
1237 + setup_serial_port();
1238 +
1239 + mips_machgroup = MACH_GROUP_MIKROTIK;
1240 + soft_reboot = read_c0_status() & SR_NMI;
1241 + pm_power_off = NULL;
1242 +
1243 + /*
1244 + * give all RAM to boot allocator,
1245 + * except for the first 0x400 and the last 0x200 bytes
1246 + */
1247 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1248 +}
1249 +
1250 +void prom_free_prom_memory(void)
1251 +{
1252 + /* FIXME: STUB */
1253 +}
1254 +
1255 +void __init prom_setup_cmdline(void){
1256 + char cmd_line[CL_SIZE];
1257 + char *cp;
1258 + int prom_argc;
1259 + char **prom_argv, **prom_envp;
1260 + int i;
1261 +
1262 + prom_argc = fw_arg0;
1263 + prom_argv = (char **) fw_arg1;
1264 + prom_envp = (char **) fw_arg2;
1265 +
1266 + cp=cmd_line;
1267 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1268 + however, our elf loader starts at [0] */
1269 + for(i=0;i<prom_argc;i++){
1270 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1271 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1272 + continue;
1273 + }
1274 +#ifdef IGNORE_CMDLINE_MEM
1275 + /* parses out the "mem=xx" arg */
1276 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1277 + continue;
1278 + }
1279 +#endif
1280 + if (i>0) *(cp++) = ' ';
1281 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1282 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1283 + }
1284 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1285 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1286 + }
1287 + strcpy(cp,prom_argv[i]);
1288 + cp+=strlen(prom_argv[i]);
1289 + }
1290 +
1291 + i=strlen(arcs_cmdline);
1292 + if (i>0){
1293 + *(cp++) = ' ';
1294 + strcpy(cp,arcs_cmdline);
1295 + cp+=strlen(arcs_cmdline);
1296 + }
1297 + if (gpio_bootup_state&0x02)
1298 + strcpy(cp,GPIO_INIT_NOBUTTON);
1299 + else
1300 + strcpy(cp,GPIO_INIT_BUTTON);
1301 + cmd_line[CL_SIZE-1] = '\0';
1302 +
1303 + strcpy(arcs_cmdline,cmd_line);
1304 +}
1305 +
1306 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1307 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1308 +++ linux.dev/arch/mips/rb500/serial.c 2006-12-14 04:09:50.000000000 +0100
1309 @@ -0,0 +1,77 @@
1310 +/**************************************************************************
1311 + *
1312 + * BRIEF MODULE DESCRIPTION
1313 + * Serial port initialisation.
1314 + *
1315 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1316 + *
1317 + * This program is free software; you can redistribute it and/or modify it
1318 + * under the terms of the GNU General Public License as published by the
1319 + * Free Software Foundation; either version 2 of the License, or (at your
1320 + * option) any later version.
1321 + *
1322 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1323 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1324 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1325 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1326 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1327 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1328 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1329 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1330 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1331 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1332 + *
1333 + * You should have received a copy of the GNU General Public License along
1334 + * with this program; if not, write to the Free Software Foundation, Inc.,
1335 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1336 + *
1337 + *
1338 + **************************************************************************
1339 + * May 2004 rkt, neb
1340 + *
1341 + * Initial Release
1342 + *
1343 + *
1344 + *
1345 + **************************************************************************
1346 + */
1347 +
1348 +
1349 +#include <linux/autoconf.h>
1350 +#include <linux/init.h>
1351 +#include <linux/sched.h>
1352 +#include <linux/pci.h>
1353 +#include <linux/interrupt.h>
1354 +#include <linux/tty.h>
1355 +#include <linux/serial.h>
1356 +#include <linux/serial_core.h>
1357 +
1358 +#include <asm/time.h>
1359 +#include <asm/cpu.h>
1360 +#include <asm/bootinfo.h>
1361 +#include <asm/irq.h>
1362 +#include <asm/serial.h>
1363 +#include <asm/rc32434/rc32434.h>
1364 +
1365 +extern unsigned int idt_cpu_freq;
1366 +
1367 +static struct uart_port serial_req = {
1368 + .type = PORT_16550A,
1369 + .line = 0,
1370 + .irq = RC32434_UART0_IRQ,
1371 + .flags = STD_COM_FLAGS,
1372 + .iotype = UPIO_MEM,
1373 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1374 +// .fifosize = 14
1375 + .regshift = 2
1376 +};
1377 +
1378 +int __init setup_serial_port(void)
1379 +{
1380 + serial_req.uartclk = idt_cpu_freq;
1381 +
1382 + if (early_serial_setup(&serial_req))
1383 + return -ENODEV;
1384 +
1385 + return(0);
1386 +}
1387 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1388 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1389 +++ linux.dev/arch/mips/rb500/setup.c 2006-12-14 04:51:12.000000000 +0100
1390 @@ -0,0 +1,81 @@
1391 +/*
1392 + * setup.c - boot time setup code
1393 + */
1394 +
1395 +#include <linux/init.h>
1396 +#include <linux/mm.h>
1397 +#include <linux/sched.h>
1398 +#include <linux/irq.h>
1399 +#include <linux/ioport.h>
1400 +#include <linux/pm.h>
1401 +#include <asm/bootinfo.h>
1402 +#include <asm/mipsregs.h>
1403 +#include <asm/pgtable.h>
1404 +#include <asm/reboot.h>
1405 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1406 +#include <asm/time.h>
1407 +#include <asm/io.h>
1408 +#include <asm/rc32434/rc32434.h>
1409 +#include <asm/rc32434/pci.h>
1410 +
1411 +#ifdef CONFIG_PCI
1412 +extern void *rc32434_time_init(void);
1413 +extern int __init rc32434_pcibridge_init(void);
1414 +#endif
1415 +
1416 +#define epldMask ((volatile unsigned char *)0xB900000d)
1417 +
1418 +static void rb_machine_restart(char *command)
1419 +{
1420 + /* just jump to the reset vector */
1421 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1422 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1423 +}
1424 +
1425 +static void rb_machine_halt(void)
1426 +{
1427 + for(;;) continue;
1428 +}
1429 +
1430 +#ifdef CONFIG_CPU_HAS_WB
1431 +void (*__wbflush) (void);
1432 +
1433 +static void rb_write_buffer_flush(void)
1434 +{
1435 + __asm__ __volatile__
1436 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1437 +}
1438 +#endif
1439 +
1440 +void __init plat_mem_setup(void)
1441 +{
1442 + unsigned int pciCntlVal;
1443 +
1444 + board_time_init = rc32434_time_init;
1445 +
1446 +#ifdef CONFIG_CPU_HAS_WB
1447 + __wbflush = rb_write_buffer_flush;
1448 +#endif
1449 + _machine_restart = rb_machine_restart;
1450 + _machine_halt = rb_machine_halt;
1451 + /*_machine_power_off = rb_machine_power_halt;*/
1452 + pm_power_off = rb_machine_halt;
1453 +
1454 + set_io_port_base(KSEG1);
1455 +
1456 + pciCntlVal=rc32434_pci->pcic;
1457 + pciCntlVal &= 0xFFFFFF7;
1458 + rc32434_pci->pcic = pciCntlVal;
1459 +
1460 +#ifdef CONFIG_PCI
1461 + /* Enable PCI interrupts in EPLD Mask register */
1462 + *epldMask = 0x0;
1463 + *(epldMask + 1) = 0x0;
1464 +#endif
1465 + write_c0_wired(0);
1466 +}
1467 +
1468 +const char *get_system_type(void)
1469 +{
1470 + return "MIPS RB500";
1471 +}
1472 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1473 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1474 +++ linux.dev/arch/mips/rb500/time.c 2006-12-14 04:48:33.000000000 +0100
1475 @@ -0,0 +1,93 @@
1476 +/*
1477 +****************************************************************************
1478 +* Carsten Langgaard, carstenl@mips.com
1479 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1480 +*
1481 +***************************************************************************
1482 +*
1483 +* This program is free software; you can distribute it and/or modify it
1484 +* under the terms of the GNU General Public License (Version 2) as
1485 +* published by the Free Software Foundation.
1486 +*
1487 +* This program is distributed in the hope it will be useful, but WITHOUT
1488 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1489 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1490 +* for more details.
1491 +*
1492 +* You should have received a copy of the GNU General Public License along
1493 +* with this program; if not, write to the Free Software Foundation, Inc.,
1494 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1495 +*
1496 +****************************************************************************
1497 +*
1498 +* Setting up the clock on the MIPS boards.
1499 +*
1500 +****************************************************************************
1501 +* P. Sadik Oct 10, 2003
1502 +*
1503 +* Started change log.
1504 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1505 +* Code cleanup
1506 +****************************************************************************
1507 +*/
1508 +
1509 +#include <linux/autoconf.h>
1510 +#include <linux/init.h>
1511 +#include <linux/kernel_stat.h>
1512 +#include <linux/sched.h>
1513 +#include <linux/spinlock.h>
1514 +#include <linux/mc146818rtc.h>
1515 +#include <linux/irq.h>
1516 +#include <linux/timex.h>
1517 +
1518 +#include <asm/mipsregs.h>
1519 +#include <asm/ptrace.h>
1520 +#include <asm/debug.h>
1521 +#include <asm/rc32434/rc32434.h>
1522 +
1523 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1524 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1525 +extern unsigned int mips_hpt_frequency;
1526 +extern unsigned int idt_cpu_freq;
1527 +
1528 +/*
1529 + * Figure out the r4k offset, the amount to increment the compare
1530 + * register for each time tick. There is no RTC available.
1531 + *
1532 + * The RC32434 counts at half the CPU *core* speed.
1533 + */
1534 +static unsigned long __init cal_r4koff(void)
1535 +{
1536 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1537 + return (mips_hpt_frequency / HZ);
1538 +}
1539 +
1540 +
1541 +void __init rc32434_time_init(void)
1542 +{
1543 + unsigned int est_freq, flags;
1544 +
1545 + local_irq_save(flags);
1546 +
1547 + printk("calculating r4koff... ");
1548 + r4k_offset = cal_r4koff();
1549 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1550 +
1551 + est_freq = 2*r4k_offset*HZ;
1552 + est_freq += 5000; /* round */
1553 + est_freq -= est_freq%10000;
1554 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1555 + (est_freq%1000000)*100/1000000);
1556 + local_irq_restore(flags);
1557 +}
1558 +
1559 +void __init plat_timer_setup(struct irqaction *irq)
1560 +{
1561 + /* we are using the cpu counter for timer interrupts */
1562 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1563 +
1564 + /* to generate the first timer interrupt */
1565 + r4k_cur = (read_c0_count() + r4k_offset);
1566 + write_c0_compare(r4k_cur);
1567 +}
1568 +
1569 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1570 --- linux.old/drivers/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
1571 +++ linux.dev/drivers/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
1572 @@ -16,6 +16,7 @@
1573
1574 # Build the PCI MSI interrupt support
1575 obj-$(CONFIG_PCI_MSI) += msi.o
1576 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1577
1578 # Build the Hypertransport interrupt support
1579 obj-$(CONFIG_HT_IRQ) += htirq.o
1580 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1581 --- linux.old/include/asm-mips/bootinfo.h 2006-11-29 22:57:37.000000000 +0100
1582 +++ linux.dev/include/asm-mips/bootinfo.h 2006-12-14 04:09:50.000000000 +0100
1583 @@ -212,6 +212,8 @@
1584 #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
1585 #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
1586
1587 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1588 +
1589 #define CL_SIZE COMMAND_LINE_SIZE
1590
1591 const char *get_system_type(void);
1592 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1593 --- linux.old/include/asm-mips/cpu.h 2006-11-29 22:57:37.000000000 +0100
1594 +++ linux.dev/include/asm-mips/cpu.h 2006-12-14 04:09:50.000000000 +0100
1595 @@ -200,7 +200,8 @@
1596 #define CPU_SB1A 62
1597 #define CPU_74K 63
1598 #define CPU_R14000 64
1599 -#define CPU_LAST 64
1600 +#define CPU_RC32300 65
1601 +#define CPU_LAST 65
1602
1603 /*
1604 * ISA Level encodings
1605 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
1606 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
1607 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-12-14 04:09:50.000000000 +0100
1608 @@ -0,0 +1,173 @@
1609 +#ifndef __IDT_DDR_H__
1610 +#define __IDT_DDR_H__
1611 +
1612 +/*******************************************************************************
1613 + *
1614 + * Copyright 2002 Integrated Device Technology, Inc.
1615 + * All rights reserved.
1616 + *
1617 + * DDR register definition.
1618 + *
1619 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1620 + *
1621 + * Author : ryan.holmQVist@idt.com
1622 + * Date : 20011005
1623 + * Update :
1624 + * $Log: ddr.h,v $
1625 + * Revision 1.2 2002/06/06 18:34:03 astichte
1626 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1627 + *
1628 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1629 + * jba File moved from vcode/include/idt/acacia
1630 + *
1631 + *
1632 + ******************************************************************************/
1633 +
1634 +enum
1635 +{
1636 + DDR0_PhysicalAddress = 0x18018000,
1637 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
1638 +
1639 + DDR0_VirtualAddress = 0xb8018000,
1640 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
1641 +} ;
1642 +
1643 +typedef struct DDR_s
1644 +{
1645 + u32 ddrbase ;
1646 + u32 ddrmask ;
1647 + u32 res1;
1648 + u32 res2;
1649 + u32 ddrc ;
1650 + u32 ddrabase ;
1651 + u32 ddramask ;
1652 + u32 ddramap ;
1653 + u32 ddrcust;
1654 + u32 ddrrdc;
1655 + u32 ddrspare;
1656 +} volatile *DDR_t ;
1657 +
1658 +enum
1659 +{
1660 + DDR0BASE_baseaddr_b = 16,
1661 + DDR0BASE_baseaddr_m = 0xffff0000,
1662 +
1663 + DDR0MASK_mask_b = 16,
1664 + DDR0MASK_mask_m = 0xffff0000,
1665 +
1666 + DDR1BASE_baseaddr_b = 16,
1667 + DDR1BASE_baseaddr_m = 0xffff0000,
1668 +
1669 + DDR1MASK_mask_b = 16,
1670 + DDR1MASK_mask_m = 0xffff0000,
1671 +
1672 + DDRC_ata_b = 5,
1673 + DDRC_ata_m = 0x000000E0,
1674 + DDRC_dbw_b = 8,
1675 + DDRC_dbw_m = 0x00000100,
1676 + DDRC_wr_b = 9,
1677 + DDRC_wr_m = 0x00000600,
1678 + DDRC_ps_b = 11,
1679 + DDRC_ps_m = 0x00001800,
1680 + DDRC_dtype_b = 13,
1681 + DDRC_dtype_m = 0x0000e000,
1682 + DDRC_rfc_b = 16,
1683 + DDRC_rfc_m = 0x000f0000,
1684 + DDRC_rp_b = 20,
1685 + DDRC_rp_m = 0x00300000,
1686 + DDRC_ap_b = 22,
1687 + DDRC_ap_m = 0x00400000,
1688 + DDRC_rcd_b = 23,
1689 + DDRC_rcd_m = 0x01800000,
1690 + DDRC_cl_b = 25,
1691 + DDRC_cl_m = 0x06000000,
1692 + DDRC_dbm_b = 27,
1693 + DDRC_dbm_m = 0x08000000,
1694 + DDRC_sds_b = 28,
1695 + DDRC_sds_m = 0x10000000,
1696 + DDRC_atp_b = 29,
1697 + DDRC_atp_m = 0x60000000,
1698 + DDRC_re_b = 31,
1699 + DDRC_re_m = 0x80000000,
1700 +
1701 + DDRRDC_ces_b = 0,
1702 + DDRRDC_ces_m = 0x00000001,
1703 + DDRRDC_ace_b = 1,
1704 + DDRRDC_ace_m = 0x00000002,
1705 +
1706 + DDRABASE_baseaddr_b = 16,
1707 + DDRABASE_baseaddr_m = 0xffff0000,
1708 +
1709 + DDRAMASK_mask_b = 16,
1710 + DDRAMASK_mask_m = 0xffff0000,
1711 +
1712 + DDRAMAP_map_b = 16,
1713 + DDRAMAP_map_m = 0xffff0000,
1714 +
1715 + DDRCUST_cs_b = 0,
1716 + DDRCUST_cs_m = 0x00000003,
1717 + DDRCUST_we_b = 2,
1718 + DDRCUST_we_m = 0x00000004,
1719 + DDRCUST_ras_b = 3,
1720 + DDRCUST_ras_m = 0x00000008,
1721 + DDRCUST_cas_b = 4,
1722 + DDRCUST_cas_m = 0x00000010,
1723 + DDRCUST_cke_b = 5,
1724 + DDRCUST_cke_m = 0x00000020,
1725 + DDRCUST_ba_b = 6,
1726 + DDRCUST_ba_m = 0x000000c0,
1727 +
1728 + RCOUNT_rcount_b = 0,
1729 + RCOUNT_rcount_m = 0x0000ffff,
1730 +
1731 + RCOMPARE_rcompare_b = 0,
1732 + RCOMPARE_rcompare_m = 0x0000ffff,
1733 +
1734 + RTC_ce_b = 0,
1735 + RTC_ce_m = 0x00000001,
1736 + RTC_to_b = 1,
1737 + RTC_to_m = 0x00000002,
1738 + RTC_rqe_b = 2,
1739 + RTC_rqe_m = 0x00000004,
1740 +
1741 + DDRDQSC_dm_b = 0,
1742 + DDRDQSC_dm_m = 0x00000003,
1743 + DDRDQSC_dqsbs_b = 2,
1744 + DDRDQSC_dqsbs_m = 0x000000fc,
1745 + DDRDQSC_db_b = 8,
1746 + DDRDQSC_db_m = 0x00000100,
1747 + DDRDQSC_dbsp_b = 9,
1748 + DDRDQSC_dbsp_m = 0x01fffe00,
1749 + DDRDQSC_bdp_b = 25,
1750 + DDRDQSC_bdp_m = 0x7e000000,
1751 +
1752 + DDRDLLC_eao_b = 0,
1753 + DDRDLLC_eao_m = 0x00000001,
1754 + DDRDLLC_eo_b = 1,
1755 + DDRDLLC_eo_m = 0x0000003e,
1756 + DDRDLLC_fs_b = 6,
1757 + DDRDLLC_fs_m = 0x000000c0,
1758 + DDRDLLC_as_b = 8,
1759 + DDRDLLC_as_m = 0x00000700,
1760 + DDRDLLC_sp_b = 11,
1761 + DDRDLLC_sp_m = 0x001ff800,
1762 +
1763 + DDRDLLFC_men_b = 0,
1764 + DDRDLLFC_men_m = 0x00000001,
1765 + DDRDLLFC_aen_b = 1,
1766 + DDRDLLFC_aen_m = 0x00000002,
1767 + DDRDLLFC_ff_b = 2,
1768 + DDRDLLFC_ff_m = 0x00000004,
1769 +
1770 + DDRDLLTA_addr_b = 2,
1771 + DDRDLLTA_addr_m = 0xfffffffc,
1772 +
1773 + DDRDLLED_dbe_b = 0,
1774 + DDRDLLED_dbe_m = 0x00000001,
1775 + DDRDLLED_dte_b = 1,
1776 + DDRDLLED_dte_m = 0x00000002,
1777 +
1778 +
1779 +} ;
1780 +
1781 +#endif // __IDT_DDR_H__
1782 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
1783 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
1784 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-12-14 04:09:50.000000000 +0100
1785 @@ -0,0 +1,132 @@
1786 +#ifndef __IDT_DEV_H__
1787 +#define __IDT_DEV_H__
1788 +
1789 +/*******************************************************************************
1790 + *
1791 + * Copyright 2002 Integrated Device Technology, Inc.
1792 + * All rights reserved.
1793 + *
1794 + * Device Controller register definition.
1795 + *
1796 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1797 + *
1798 + * Author : John.Ahrens@idt.com
1799 + * Date : 200112013
1800 + * Update :
1801 + * $Log: dev.h,v $
1802 + * Revision 1.2 2002/06/06 18:34:03 astichte
1803 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1804 + *
1805 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1806 + * jba File moved from vcode/include/idt/acacia
1807 + *
1808 + *
1809 + ******************************************************************************/
1810 +
1811 +enum
1812 +{
1813 + DEV0_PhysicalAddress = 0x18010000,
1814 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
1815 +
1816 + DEV0_VirtualAddress = 0xb8010000,
1817 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
1818 +} ;
1819 +
1820 +typedef struct DEVICE_s
1821 +{
1822 + u32 devbase ; // Device Base
1823 + u32 devmask ; // Device Mask
1824 + u32 devc ; // Device Control
1825 + u32 devtc ; // Device Timing Control
1826 +} volatile *DEVICE_t ;
1827 +
1828 +enum
1829 +{
1830 + DEV_Count = 3,
1831 +} ;
1832 +
1833 +typedef struct DEV_s
1834 +{
1835 + struct DEVICE_s dev [DEV_Count] ;
1836 + u32 btcs ; // Bus timeout control / status
1837 + u32 btcompare ; // Compare
1838 + u32 btaddr ; // Timeout address.
1839 + u32 devdacs ; // Decoupled access control.
1840 + u32 devdaa ; // Decoupled access address.
1841 + u32 devdad ; // Decoupled access address.
1842 + u32 devspare ; // spare.
1843 +} volatile *DEV_t ;
1844 +
1845 +enum
1846 +{
1847 + DEVBASE_baseaddr_b = 16,
1848 + DEVBASE_baseaddr_m = 0xffff0000,
1849 + DEVMASK_mask_b = 16,
1850 + DEVMASK_mask_m = 0xffff0000,
1851 +
1852 + DEVC_ds_b = 0,
1853 + DEVC_ds_m = 0x00000003,
1854 + DEVC_ds_8_v = 0, // 8-bit device.
1855 + DEVC_ds_16_v = 1, // reserved
1856 + DEVC_ds_res_v = 2, // reserved.
1857 + DEVC_ds_res2_v = 3, // reserved.
1858 + DEVC_be_b = 2,
1859 + DEVC_be_m = 0x00000004,
1860 + DEVC_wp_b = 3,
1861 + DEVC_wp_m = 0x00000008,
1862 + DEVC_csd_b = 4,
1863 + DEVC_csd_m = 0x000000f0,
1864 + DEVC_oed_b = 8,
1865 + DEVC_oed_m = 0x00000f00,
1866 + DEVC_bwd_b = 12,
1867 + DEVC_bwd_m = 0x0000f000,
1868 + DEVC_rws_b = 16,
1869 + DEVC_rws_m = 0x003f0000,
1870 + DEVC_wws_b = 22,
1871 + DEVC_wws_m = 0x0fc00000,
1872 + DEVC_bre_b = 28,
1873 + DEVC_bre_m = 0x10000000,
1874 + DEVC_bwe_b = 29,
1875 + DEVC_bwe_m = 0x20000000,
1876 + DEVC_wam_b = 30,
1877 + DEVC_wam_m = 0x40000000,
1878 +
1879 + DEVTC_prd_b = 0,
1880 + DEVTC_prd_m = 0x0000000f,
1881 + DEVTC_pwd_b = 4,
1882 + DEVTC_pwd_m = 0x000000f0,
1883 + DEVTC_wdh_b = 8,
1884 + DEVTC_wdh_m = 0x00000700,
1885 + DEVTC_csh_b = 11,
1886 + DEVTC_csh_m = 0x00001800,
1887 +
1888 + BTCS_tt_b = 0,
1889 + BTCS_tt_m = 0x00000001,
1890 + BTCS_tt_write = 0,
1891 + BTCS_tt_read = 1,
1892 + BTCS_bto_b = 1, // In btcs
1893 + BTCS_bto_m = 0x00000002, // In btcs
1894 + BTCS_bte_b = 2, // In btcs
1895 + BTCS_bte_m = 0x00000004, // In btcs
1896 +
1897 + BTCOMPARE_compare_b = 0, // In btcompare
1898 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
1899 +
1900 + DEVDACS_op_b = 0, // In devdacs
1901 + DEVDACS_op_m = 0x00000001, // In devdacs
1902 + DEVDACS_op_write_v = 0,
1903 + DEVDACS_op_read_v = 1,
1904 + DEVDACS_size_b = 1, // In devdacs
1905 + DEVDACS_size_m = 0x00000006, // In devdacs
1906 + DEVDACS_size_byte_v = 0,
1907 + DEVDACS_size_halfword = 1,
1908 + DEVDACS_size_triplebyte = 2,
1909 + DEVDACS_size_word = 3,
1910 + DEVDACS_err_b = 3, // In devdacs
1911 + DEVDACS_err_m = 0x00000008, // In devdacs
1912 + DEVDACS_f_b = 4, // In devdacs
1913 + DEVDACS_f_m = 0x00000010, // In devdacs
1914 +} ;
1915 +
1916 +#endif //__IDT_DEV_H__
1917 +
1918 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
1919 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
1920 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-12-14 04:09:50.000000000 +0100
1921 @@ -0,0 +1,201 @@
1922 +#ifndef __IDT_DMA_H__
1923 +#define __IDT_DMA_H__
1924 +
1925 +/*******************************************************************************
1926 + *
1927 + * Copyright 2002 Integrated Device Technology, Inc.
1928 + * All rights reserved.
1929 + *
1930 + * DMA register definition.
1931 + *
1932 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1933 + *
1934 + * Author : ryan.holmQVist@idt.com
1935 + * Date : 20011005
1936 + * Update :
1937 + * $Log: dma.h,v $
1938 + * Revision 1.3 2002/06/06 18:34:03 astichte
1939 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1940 + *
1941 + * Revision 1.2 2002/06/05 18:30:46 astichte
1942 + * Removed IDTField
1943 + *
1944 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1945 + * jba File moved from vcode/include/idt/acacia
1946 + *
1947 + *
1948 + ******************************************************************************/
1949 +
1950 +enum
1951 +{
1952 + DMA0_PhysicalAddress = 0x18040000,
1953 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
1954 +
1955 + DMA0_VirtualAddress = 0xb8040000,
1956 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
1957 +} ;
1958 +
1959 +/*
1960 + * DMA descriptor (in physical memory).
1961 + */
1962 +
1963 +typedef struct DMAD_s
1964 +{
1965 + u32 control ; // Control. use DMAD_*
1966 + u32 ca ; // Current Address.
1967 + u32 devcs ; // Device control and status.
1968 + u32 link ; // Next descriptor in chain.
1969 +} volatile *DMAD_t ;
1970 +
1971 +enum
1972 +{
1973 + DMAD_size = sizeof (struct DMAD_s),
1974 + DMAD_count_b = 0, // in DMAD_t -> control
1975 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
1976 + DMAD_ds_b = 20, // in DMAD_t -> control
1977 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
1978 + DMAD_ds_ethRcv_v = 0,
1979 + DMAD_ds_ethXmt_v = 0,
1980 + DMAD_ds_memToFifo_v = 0,
1981 + DMAD_ds_fifoToMem_v = 0,
1982 + DMAD_ds_pciToMem_v = 0,
1983 + DMAD_ds_memToPci_v = 0,
1984 +
1985 + DMAD_devcmd_b = 22, // in DMAD_t -> control
1986 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
1987 + DMAD_devcmd_byte_v = 0, //memory-to-memory
1988 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
1989 + DMAD_devcmd_word_v = 2, //memory-to-memory
1990 + DMAD_devcmd_2words_v = 3, //memory-to-memory
1991 + DMAD_devcmd_4words_v = 4, //memory-to-memory
1992 + DMAD_devcmd_6words_v = 5, //memory-to-memory
1993 + DMAD_devcmd_8words_v = 6, //memory-to-memory
1994 + DMAD_devcmd_16words_v = 7, //memory-to-memory
1995 + DMAD_cof_b = 25, // chain on finished
1996 + DMAD_cof_m = 0x02000000, //
1997 + DMAD_cod_b = 26, // chain on done
1998 + DMAD_cod_m = 0x04000000, //
1999 + DMAD_iof_b = 27, // interrupt on finished
2000 + DMAD_iof_m = 0x08000000, //
2001 + DMAD_iod_b = 28, // interrupt on done
2002 + DMAD_iod_m = 0x10000000, //
2003 + DMAD_t_b = 29, // terminated
2004 + DMAD_t_m = 0x20000000, //
2005 + DMAD_d_b = 30, // done
2006 + DMAD_d_m = 0x40000000, //
2007 + DMAD_f_b = 31, // finished
2008 + DMAD_f_m = 0x80000000, //
2009 +} ;
2010 +
2011 +/*
2012 + * DMA register (within Internal Register Map).
2013 + */
2014 +
2015 +struct DMA_Chan_s
2016 +{
2017 + u32 dmac ; // Control.
2018 + u32 dmas ; // Status.
2019 + u32 dmasm ; // Mask.
2020 + u32 dmadptr ; // Descriptor pointer.
2021 + u32 dmandptr ; // Next descriptor pointer.
2022 +};
2023 +
2024 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2025 +
2026 +//DMA_Channels use DMACH_count instead
2027 +
2028 +enum
2029 +{
2030 + DMAC_run_b = 0, //
2031 + DMAC_run_m = 0x00000001, //
2032 + DMAC_dm_b = 1, // done mask
2033 + DMAC_dm_m = 0x00000002, //
2034 + DMAC_mode_b = 2, //
2035 + DMAC_mode_m = 0x0000000c, //
2036 + DMAC_mode_auto_v = 0,
2037 + DMAC_mode_burst_v = 1,
2038 + DMAC_mode_transfer_v = 2, //usually used
2039 + DMAC_mode_reserved_v = 3,
2040 + DMAC_a_b = 4, //
2041 + DMAC_a_m = 0x00000010, //
2042 +
2043 + DMAS_f_b = 0, // finished (sticky)
2044 + DMAS_f_m = 0x00000001, //
2045 + DMAS_d_b = 1, // done (sticky)
2046 + DMAS_d_m = 0x00000002, //
2047 + DMAS_c_b = 2, // chain (sticky)
2048 + DMAS_c_m = 0x00000004, //
2049 + DMAS_e_b = 3, // error (sticky)
2050 + DMAS_e_m = 0x00000008, //
2051 + DMAS_h_b = 4, // halt (sticky)
2052 + DMAS_h_m = 0x00000010, //
2053 +
2054 + DMASM_f_b = 0, // finished (1=mask)
2055 + DMASM_f_m = 0x00000001, //
2056 + DMASM_d_b = 1, // done (1=mask)
2057 + DMASM_d_m = 0x00000002, //
2058 + DMASM_c_b = 2, // chain (1=mask)
2059 + DMASM_c_m = 0x00000004, //
2060 + DMASM_e_b = 3, // error (1=mask)
2061 + DMASM_e_m = 0x00000008, //
2062 + DMASM_h_b = 4, // halt (1=mask)
2063 + DMASM_h_m = 0x00000010, //
2064 +} ;
2065 +
2066 +/*
2067 + * DMA channel definitions
2068 + */
2069 +
2070 +enum
2071 +{
2072 + DMACH_ethRcv = 0,
2073 + DMACH_ethXmt = 1,
2074 + DMACH_memToFifo = 2,
2075 + DMACH_fifoToMem = 3,
2076 + DMACH_pciToMem = 4,
2077 + DMACH_memToPci = 5,
2078 +
2079 + DMACH_count //must be last
2080 +};
2081 +
2082 +
2083 +typedef struct DMAC_s
2084 +{
2085 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2086 +} volatile *DMA_t ;
2087 +
2088 +
2089 +/*
2090 + * External DMA parameters
2091 +*/
2092 +#if 0
2093 +enum
2094 +{
2095 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2096 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2097 + DMADEVCMD_ts_byte_v = 0,
2098 + DMADEVCMD_ts_halfword_v = 1,
2099 + DMADEVCMD_ts_word_v = 2,
2100 + DMADEVCMD_ts_2word_v = 3,
2101 + DMADEVCMD_ts_4word_v = 4,
2102 + DMADEVCMD_ts_6word_v = 5,
2103 + DMADEVCMD_ts_8word_v = 6,
2104 + DMADEVCMD_ts_16word_v = 7
2105 +};
2106 +#endif
2107 +
2108 +#if 1 // aws - Compatibility.
2109 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2110 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2111 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2112 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2113 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2114 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2115 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2116 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2117 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2118 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2119 +#endif // aws - Compatibility.
2120 +
2121 +#endif // __IDT_DMA_H__
2122 +
2123 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2124 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2125 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-12-14 04:09:50.000000000 +0100
2126 @@ -0,0 +1,72 @@
2127 +#ifndef __IDT_DMA_V_H__
2128 +#define __IDT_DMA_V_H__
2129 +
2130 +/*******************************************************************************
2131 + *
2132 + * Copyright 2002 Integrated Device Technology, Inc.
2133 + * All rights reserved.
2134 + *
2135 + * DMA register definition.
2136 + *
2137 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2138 + *
2139 + * Author : ryan.holmQVist@idt.com
2140 + * Date : 20011005
2141 + * Update :
2142 + * $Log: dma.h,v $
2143 + * Revision 1.3 2002/06/06 18:34:03 astichte
2144 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2145 + *
2146 + * Revision 1.2 2002/06/05 18:30:46 astichte
2147 + * Removed IDTField
2148 + *
2149 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2150 + * jba File moved from vcode/include/idt/acacia
2151 + *
2152 + *
2153 + ******************************************************************************/
2154 +#include <asm/rc32434/dma.h>
2155 +#include <asm/rc32434/rc32434.h>
2156 +#define DMA_CHAN_OFFSET 0x14
2157 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2158 +#define DMA_COUNT(count) \
2159 + ((count) & DMAD_count_m)
2160 +
2161 +#define DMA_HALT_TIMEOUT 500
2162 +
2163 +
2164 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2165 +{
2166 + int timeout=1;
2167 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2168 + local_writel(0, &ch->dmac);
2169 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2170 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2171 + local_writel(0, &ch->dmas);
2172 + break;
2173 + }
2174 + }
2175 + }
2176 +
2177 + return timeout ? 0 : 1;
2178 +}
2179 +
2180 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2181 +{
2182 + local_writel(0, &ch->dmandptr);
2183 + local_writel(dma_addr, &ch->dmadptr);
2184 +}
2185 +
2186 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2187 +{
2188 + local_writel(dma_addr, &ch->dmandptr);
2189 +}
2190 +
2191 +#endif // __IDT_DMA_V_H__
2192 +
2193 +
2194 +
2195 +
2196 +
2197 +
2198 +
2199 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2200 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2201 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-12-14 04:09:50.000000000 +0100
2202 @@ -0,0 +1,320 @@
2203 +#ifndef __IDT_ETH_H__
2204 +#define __IDT_ETH_H__
2205 +
2206 +/*******************************************************************************
2207 + *
2208 + * Copyright 2002 Integrated Device Technology, Inc.
2209 + * All rights reserved.
2210 + *
2211 + * Ethernet register definition.
2212 + *
2213 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2214 + *
2215 + * Author : Allen.Stichter@idt.com
2216 + * Date : 20020605
2217 + * Update :
2218 + * $Log: eth.h,v $
2219 + * Revision 1.3 2002/06/06 18:34:04 astichte
2220 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2221 + *
2222 + * Revision 1.2 2002/06/05 18:19:46 astichte
2223 + * Added
2224 + *
2225 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2226 + * jba File moved from vcode/include/idt/acacia
2227 + *
2228 + ******************************************************************************/
2229 +
2230 +enum
2231 +{
2232 + ETH0_PhysicalAddress = 0x18060000,
2233 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2234 +
2235 + ETH0_VirtualAddress = 0xb8060000,
2236 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2237 +} ;
2238 +
2239 +typedef struct
2240 +{
2241 + u32 ethintfc ;
2242 + u32 ethfifott ;
2243 + u32 etharc ;
2244 + u32 ethhash0 ;
2245 + u32 ethhash1 ;
2246 + u32 ethu0 [4] ; // Reserved.
2247 + u32 ethpfs ;
2248 + u32 ethmcp ;
2249 + u32 eth_u1 [10] ; // Reserved.
2250 + u32 ethspare ;
2251 + u32 eth_u2 [42] ; // Reserved.
2252 + u32 ethsal0 ;
2253 + u32 ethsah0 ;
2254 + u32 ethsal1 ;
2255 + u32 ethsah1 ;
2256 + u32 ethsal2 ;
2257 + u32 ethsah2 ;
2258 + u32 ethsal3 ;
2259 + u32 ethsah3 ;
2260 + u32 ethrbc ;
2261 + u32 ethrpc ;
2262 + u32 ethrupc ;
2263 + u32 ethrfc ;
2264 + u32 ethtbc ;
2265 + u32 ethgpf ;
2266 + u32 eth_u9 [50] ; // Reserved.
2267 + u32 ethmac1 ;
2268 + u32 ethmac2 ;
2269 + u32 ethipgt ;
2270 + u32 ethipgr ;
2271 + u32 ethclrt ;
2272 + u32 ethmaxf ;
2273 + u32 eth_u10 ; // Reserved.
2274 + u32 ethmtest ;
2275 + u32 miimcfg ;
2276 + u32 miimcmd ;
2277 + u32 miimaddr ;
2278 + u32 miimwtd ;
2279 + u32 miimrdd ;
2280 + u32 miimind ;
2281 + u32 eth_u11 ; // Reserved.
2282 + u32 eth_u12 ; // Reserved.
2283 + u32 ethcfsa0 ;
2284 + u32 ethcfsa1 ;
2285 + u32 ethcfsa2 ;
2286 +} volatile *ETH_t;
2287 +
2288 +enum
2289 +{
2290 + ETHINTFC_en_b = 0,
2291 + ETHINTFC_en_m = 0x00000001,
2292 + ETHINTFC_its_b = 1,
2293 + ETHINTFC_its_m = 0x00000002,
2294 + ETHINTFC_rip_b = 2,
2295 + ETHINTFC_rip_m = 0x00000004,
2296 + ETHINTFC_jam_b = 3,
2297 + ETHINTFC_jam_m = 0x00000008,
2298 + ETHINTFC_ovr_b = 4,
2299 + ETHINTFC_ovr_m = 0x00000010,
2300 + ETHINTFC_und_b = 5,
2301 + ETHINTFC_und_m = 0x00000020,
2302 + ETHINTFC_iom_b = 6,
2303 + ETHINTFC_iom_m = 0x000000c0,
2304 +
2305 + ETHFIFOTT_tth_b = 0,
2306 + ETHFIFOTT_tth_m = 0x0000007f,
2307 +
2308 + ETHARC_pro_b = 0,
2309 + ETHARC_pro_m = 0x00000001,
2310 + ETHARC_am_b = 1,
2311 + ETHARC_am_m = 0x00000002,
2312 + ETHARC_afm_b = 2,
2313 + ETHARC_afm_m = 0x00000004,
2314 + ETHARC_ab_b = 3,
2315 + ETHARC_ab_m = 0x00000008,
2316 +
2317 + ETHSAL_byte5_b = 0,
2318 + ETHSAL_byte5_m = 0x000000ff,
2319 + ETHSAL_byte4_b = 8,
2320 + ETHSAL_byte4_m = 0x0000ff00,
2321 + ETHSAL_byte3_b = 16,
2322 + ETHSAL_byte3_m = 0x00ff0000,
2323 + ETHSAL_byte2_b = 24,
2324 + ETHSAL_byte2_m = 0xff000000,
2325 +
2326 + ETHSAH_byte1_b = 0,
2327 + ETHSAH_byte1_m = 0x000000ff,
2328 + ETHSAH_byte0_b = 8,
2329 + ETHSAH_byte0_m = 0x0000ff00,
2330 +
2331 + ETHGPF_ptv_b = 0,
2332 + ETHGPF_ptv_m = 0x0000ffff,
2333 +
2334 + ETHPFS_pfd_b = 0,
2335 + ETHPFS_pfd_m = 0x00000001,
2336 +
2337 + ETHCFSA0_cfsa4_b = 0,
2338 + ETHCFSA0_cfsa4_m = 0x000000ff,
2339 + ETHCFSA0_cfsa5_b = 8,
2340 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2341 +
2342 + ETHCFSA1_cfsa2_b = 0,
2343 + ETHCFSA1_cfsa2_m = 0x000000ff,
2344 + ETHCFSA1_cfsa3_b = 8,
2345 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2346 +
2347 + ETHCFSA2_cfsa0_b = 0,
2348 + ETHCFSA2_cfsa0_m = 0x000000ff,
2349 + ETHCFSA2_cfsa1_b = 8,
2350 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2351 +
2352 + ETHMAC1_re_b = 0,
2353 + ETHMAC1_re_m = 0x00000001,
2354 + ETHMAC1_paf_b = 1,
2355 + ETHMAC1_paf_m = 0x00000002,
2356 + ETHMAC1_rfc_b = 2,
2357 + ETHMAC1_rfc_m = 0x00000004,
2358 + ETHMAC1_tfc_b = 3,
2359 + ETHMAC1_tfc_m = 0x00000008,
2360 + ETHMAC1_lb_b = 4,
2361 + ETHMAC1_lb_m = 0x00000010,
2362 + ETHMAC1_mr_b = 31,
2363 + ETHMAC1_mr_m = 0x80000000,
2364 +
2365 + ETHMAC2_fd_b = 0,
2366 + ETHMAC2_fd_m = 0x00000001,
2367 + ETHMAC2_flc_b = 1,
2368 + ETHMAC2_flc_m = 0x00000002,
2369 + ETHMAC2_hfe_b = 2,
2370 + ETHMAC2_hfe_m = 0x00000004,
2371 + ETHMAC2_dc_b = 3,
2372 + ETHMAC2_dc_m = 0x00000008,
2373 + ETHMAC2_cen_b = 4,
2374 + ETHMAC2_cen_m = 0x00000010,
2375 + ETHMAC2_pe_b = 5,
2376 + ETHMAC2_pe_m = 0x00000020,
2377 + ETHMAC2_vpe_b = 6,
2378 + ETHMAC2_vpe_m = 0x00000040,
2379 + ETHMAC2_ape_b = 7,
2380 + ETHMAC2_ape_m = 0x00000080,
2381 + ETHMAC2_ppe_b = 8,
2382 + ETHMAC2_ppe_m = 0x00000100,
2383 + ETHMAC2_lpe_b = 9,
2384 + ETHMAC2_lpe_m = 0x00000200,
2385 + ETHMAC2_nb_b = 12,
2386 + ETHMAC2_nb_m = 0x00001000,
2387 + ETHMAC2_bp_b = 13,
2388 + ETHMAC2_bp_m = 0x00002000,
2389 + ETHMAC2_ed_b = 14,
2390 + ETHMAC2_ed_m = 0x00004000,
2391 +
2392 + ETHIPGT_ipgt_b = 0,
2393 + ETHIPGT_ipgt_m = 0x0000007f,
2394 +
2395 + ETHIPGR_ipgr2_b = 0,
2396 + ETHIPGR_ipgr2_m = 0x0000007f,
2397 + ETHIPGR_ipgr1_b = 8,
2398 + ETHIPGR_ipgr1_m = 0x00007f00,
2399 +
2400 + ETHCLRT_maxret_b = 0,
2401 + ETHCLRT_maxret_m = 0x0000000f,
2402 + ETHCLRT_colwin_b = 8,
2403 + ETHCLRT_colwin_m = 0x00003f00,
2404 +
2405 + ETHMAXF_maxf_b = 0,
2406 + ETHMAXF_maxf_m = 0x0000ffff,
2407 +
2408 + ETHMTEST_tb_b = 2,
2409 + ETHMTEST_tb_m = 0x00000004,
2410 +
2411 + ETHMCP_div_b = 0,
2412 + ETHMCP_div_m = 0x000000ff,
2413 +
2414 + MIIMCFG_rsv_b = 0,
2415 + MIIMCFG_rsv_m = 0x0000000c,
2416 +
2417 + MIIMCMD_rd_b = 0,
2418 + MIIMCMD_rd_m = 0x00000001,
2419 + MIIMCMD_scn_b = 1,
2420 + MIIMCMD_scn_m = 0x00000002,
2421 +
2422 + MIIMADDR_regaddr_b = 0,
2423 + MIIMADDR_regaddr_m = 0x0000001f,
2424 + MIIMADDR_phyaddr_b = 8,
2425 + MIIMADDR_phyaddr_m = 0x00001f00,
2426 +
2427 + MIIMWTD_wdata_b = 0,
2428 + MIIMWTD_wdata_m = 0x0000ffff,
2429 +
2430 + MIIMRDD_rdata_b = 0,
2431 + MIIMRDD_rdata_m = 0x0000ffff,
2432 +
2433 + MIIMIND_bsy_b = 0,
2434 + MIIMIND_bsy_m = 0x00000001,
2435 + MIIMIND_scn_b = 1,
2436 + MIIMIND_scn_m = 0x00000002,
2437 + MIIMIND_nv_b = 2,
2438 + MIIMIND_nv_m = 0x00000004,
2439 +
2440 +} ;
2441 +
2442 +/*
2443 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2444 + */
2445 +enum
2446 +{
2447 + ETHRX_fd_b = 0,
2448 + ETHRX_fd_m = 0x00000001,
2449 + ETHRX_ld_b = 1,
2450 + ETHRX_ld_m = 0x00000002,
2451 + ETHRX_rok_b = 2,
2452 + ETHRX_rok_m = 0x00000004,
2453 + ETHRX_fm_b = 3,
2454 + ETHRX_fm_m = 0x00000008,
2455 + ETHRX_mp_b = 4,
2456 + ETHRX_mp_m = 0x00000010,
2457 + ETHRX_bp_b = 5,
2458 + ETHRX_bp_m = 0x00000020,
2459 + ETHRX_vlt_b = 6,
2460 + ETHRX_vlt_m = 0x00000040,
2461 + ETHRX_cf_b = 7,
2462 + ETHRX_cf_m = 0x00000080,
2463 + ETHRX_ovr_b = 8,
2464 + ETHRX_ovr_m = 0x00000100,
2465 + ETHRX_crc_b = 9,
2466 + ETHRX_crc_m = 0x00000200,
2467 + ETHRX_cv_b = 10,
2468 + ETHRX_cv_m = 0x00000400,
2469 + ETHRX_db_b = 11,
2470 + ETHRX_db_m = 0x00000800,
2471 + ETHRX_le_b = 12,
2472 + ETHRX_le_m = 0x00001000,
2473 + ETHRX_lor_b = 13,
2474 + ETHRX_lor_m = 0x00002000,
2475 + ETHRX_ces_b = 14,
2476 + ETHRX_ces_m = 0x00004000,
2477 + ETHRX_length_b = 16,
2478 + ETHRX_length_m = 0xffff0000,
2479 +
2480 + ETHTX_fd_b = 0,
2481 + ETHTX_fd_m = 0x00000001,
2482 + ETHTX_ld_b = 1,
2483 + ETHTX_ld_m = 0x00000002,
2484 + ETHTX_oen_b = 2,
2485 + ETHTX_oen_m = 0x00000004,
2486 + ETHTX_pen_b = 3,
2487 + ETHTX_pen_m = 0x00000008,
2488 + ETHTX_cen_b = 4,
2489 + ETHTX_cen_m = 0x00000010,
2490 + ETHTX_hen_b = 5,
2491 + ETHTX_hen_m = 0x00000020,
2492 + ETHTX_tok_b = 6,
2493 + ETHTX_tok_m = 0x00000040,
2494 + ETHTX_mp_b = 7,
2495 + ETHTX_mp_m = 0x00000080,
2496 + ETHTX_bp_b = 8,
2497 + ETHTX_bp_m = 0x00000100,
2498 + ETHTX_und_b = 9,
2499 + ETHTX_und_m = 0x00000200,
2500 + ETHTX_of_b = 10,
2501 + ETHTX_of_m = 0x00000400,
2502 + ETHTX_ed_b = 11,
2503 + ETHTX_ed_m = 0x00000800,
2504 + ETHTX_ec_b = 12,
2505 + ETHTX_ec_m = 0x00001000,
2506 + ETHTX_lc_b = 13,
2507 + ETHTX_lc_m = 0x00002000,
2508 + ETHTX_td_b = 14,
2509 + ETHTX_td_m = 0x00004000,
2510 + ETHTX_crc_b = 15,
2511 + ETHTX_crc_m = 0x00008000,
2512 + ETHTX_le_b = 16,
2513 + ETHTX_le_m = 0x00010000,
2514 + ETHTX_cc_b = 17,
2515 + ETHTX_cc_m = 0x001E0000,
2516 +} ;
2517 +
2518 +#endif // __IDT_ETH_H__
2519 +
2520 +
2521 +
2522 +
2523 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2524 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2525 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-12-14 04:09:50.000000000 +0100
2526 @@ -0,0 +1,63 @@
2527 +#ifndef __IDT_ETH_V_H__
2528 +#define __IDT_ETH_V_H__
2529 +
2530 +/*******************************************************************************
2531 + *
2532 + * Copyright 2002 Integrated Device Technology, Inc.
2533 + * All rights reserved.
2534 + *
2535 + * Ethernet register definition.
2536 + *
2537 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2538 + *
2539 + * Author : Allen.Stichter@idt.com
2540 + * Date : 20020605
2541 + * Update :
2542 + * $Log: eth.h,v $
2543 + * Revision 1.3 2002/06/06 18:34:04 astichte
2544 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2545 + *
2546 + * Revision 1.2 2002/06/05 18:19:46 astichte
2547 + * Added
2548 + *
2549 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2550 + * jba File moved from vcode/include/idt/acacia
2551 + *
2552 + ******************************************************************************/
2553 +
2554 +#include <asm/rc32434/eth.h>
2555 +
2556 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2557 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2558 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2559 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2560 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2561 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2562 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2563 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2564 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2565 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2566 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2567 +
2568 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2569 +
2570 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2571 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2572 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2573 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2574 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2575 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2576 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
2577 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
2578 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
2579 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
2580 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
2581 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
2582 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
2583 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
2584 +#endif // __IDT_ETH_V_H__
2585 +
2586 +
2587 +
2588 +
2589 +
2590 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
2591 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
2592 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-12-14 04:09:50.000000000 +0100
2593 @@ -0,0 +1,181 @@
2594 +#ifndef __IDT_GPIO_H__
2595 +#define __IDT_GPIO_H__
2596 +
2597 +/*******************************************************************************
2598 + *
2599 + * Copyright 2002 Integrated Device Technology, Inc.
2600 + * All rights reserved.
2601 + *
2602 + * GPIO register definition.
2603 + *
2604 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
2605 + *
2606 + * Author : ryan.holmQVist@idt.com
2607 + * Date : 20011005
2608 + * Update :
2609 + * $Log: gpio.h,v $
2610 + * Revision 1.2 2002/06/06 18:34:04 astichte
2611 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2612 + *
2613 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2614 + * jba File moved from vcode/include/idt/acacia
2615 + *
2616 + *
2617 + ******************************************************************************/
2618 +
2619 +enum
2620 +{
2621 + GPIO0_PhysicalAddress = 0x18050000,
2622 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
2623 +
2624 + GPIO0_VirtualAddress = 0xb8050000,
2625 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
2626 +} ;
2627 +
2628 +typedef struct
2629 +{
2630 + u32 gpiofunc; /* GPIO Function Register
2631 + * gpiofunc[x]==0 bit = gpio
2632 + * func[x]==1 bit = altfunc
2633 + */
2634 + u32 gpiocfg; /* GPIO Configuration Register
2635 + * gpiocfg[x]==0 bit = input
2636 + * gpiocfg[x]==1 bit = output
2637 + */
2638 + u32 gpiod; /* GPIO Data Register
2639 + * gpiod[x] read/write gpio pinX status
2640 + */
2641 + u32 gpioilevel; /* GPIO Interrupt Status Register
2642 + * interrupt level (see gpioistat)
2643 + */
2644 + u32 gpioistat; /* Gpio Interrupt Status Register
2645 + * istat[x] = (gpiod[x] == level[x])
2646 + * cleared in ISR (STICKY bits)
2647 + */
2648 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
2649 +} volatile * GPIO_t ;
2650 +
2651 +typedef enum
2652 +{
2653 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
2654 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
2655 + GPIO_input_v = 0, // gpiocfg use pin as input.
2656 + GPIO_output_v = 1, // gpiocfg use pin as output.
2657 + GPIO_pin0_b = 0,
2658 + GPIO_pin0_m = 0x00000001,
2659 + GPIO_pin1_b = 1,
2660 + GPIO_pin1_m = 0x00000002,
2661 + GPIO_pin2_b = 2,
2662 + GPIO_pin2_m = 0x00000004,
2663 + GPIO_pin3_b = 3,
2664 + GPIO_pin3_m = 0x00000008,
2665 + GPIO_pin4_b = 4,
2666 + GPIO_pin4_m = 0x00000010,
2667 + GPIO_pin5_b = 5,
2668 + GPIO_pin5_m = 0x00000020,
2669 + GPIO_pin6_b = 6,
2670 + GPIO_pin6_m = 0x00000040,
2671 + GPIO_pin7_b = 7,
2672 + GPIO_pin7_m = 0x00000080,
2673 + GPIO_pin8_b = 8,
2674 + GPIO_pin8_m = 0x00000100,
2675 + GPIO_pin9_b = 9,
2676 + GPIO_pin9_m = 0x00000200,
2677 + GPIO_pin10_b = 10,
2678 + GPIO_pin10_m = 0x00000400,
2679 + GPIO_pin11_b = 11,
2680 + GPIO_pin11_m = 0x00000800,
2681 + GPIO_pin12_b = 12,
2682 + GPIO_pin12_m = 0x00001000,
2683 + GPIO_pin13_b = 13,
2684 + GPIO_pin13_m = 0x00002000,
2685 + GPIO_pin14_b = 14,
2686 + GPIO_pin14_m = 0x00004000,
2687 + GPIO_pin15_b = 15,
2688 + GPIO_pin15_m = 0x00008000,
2689 + GPIO_pin16_b = 16,
2690 + GPIO_pin16_m = 0x00010000,
2691 + GPIO_pin17_b = 17,
2692 + GPIO_pin17_m = 0x00020000,
2693 + GPIO_pin18_b = 18,
2694 + GPIO_pin18_m = 0x00040000,
2695 + GPIO_pin19_b = 19,
2696 + GPIO_pin19_m = 0x00080000,
2697 + GPIO_pin20_b = 20,
2698 + GPIO_pin20_m = 0x00100000,
2699 + GPIO_pin21_b = 21,
2700 + GPIO_pin21_m = 0x00200000,
2701 + GPIO_pin22_b = 22,
2702 + GPIO_pin22_m = 0x00400000,
2703 + GPIO_pin23_b = 23,
2704 + GPIO_pin23_m = 0x00800000,
2705 + GPIO_pin24_b = 24,
2706 + GPIO_pin24_m = 0x01000000,
2707 + GPIO_pin25_b = 25,
2708 + GPIO_pin25_m = 0x02000000,
2709 + GPIO_pin26_b = 26,
2710 + GPIO_pin26_m = 0x04000000,
2711 + GPIO_pin27_b = 27,
2712 + GPIO_pin27_m = 0x08000000,
2713 + GPIO_pin28_b = 28,
2714 + GPIO_pin28_m = 0x10000000,
2715 + GPIO_pin29_b = 29,
2716 + GPIO_pin29_m = 0x20000000,
2717 + GPIO_pin30_b = 30,
2718 + GPIO_pin30_m = 0x40000000,
2719 + GPIO_pin31_b = 31,
2720 + GPIO_pin31_m = 0x80000000,
2721 +
2722 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
2723 +
2724 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
2725 + GPIO_u0sout_m = GPIO_pin0_m,
2726 + GPIO_u0sout_cfg_v = GPIO_output_v,
2727 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
2728 + GPIO_u0sinp_m = GPIO_pin1_m,
2729 + GPIO_u0sinp_cfg_v = GPIO_input_v,
2730 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
2731 + GPIO_u0rtsn_m = GPIO_pin2_m,
2732 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
2733 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
2734 + GPIO_u0ctsn_m = GPIO_pin3_m,
2735 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
2736 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
2737 + GPIO_maddr22_m = GPIO_pin4_m,
2738 + GPIO_maddr22_cfg_v = GPIO_output_v,
2739 +
2740 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
2741 + GPIO_maddr23_m = GPIO_pin5_m,
2742 + GPIO_maddr23_cfg_v = GPIO_output_v,
2743 +
2744 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
2745 + GPIO_maddr24_m = GPIO_pin6_m,
2746 + GPIO_maddr24_cfg_v = GPIO_output_v,
2747 +
2748 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
2749 + GPIO_maddr25_m = GPIO_pin7_m,
2750 + GPIO_maddr25_cfg_v = GPIO_output_v,
2751 +
2752 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
2753 + GPIO_cpu_m = GPIO_pin8_m,
2754 + GPIO_cpu_cfg_v = GPIO_output_v,
2755 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
2756 + GPIO_afspare6_m = GPIO_pin9_m,
2757 + GPIO_afspare6_cfg_v = GPIO_input_v,
2758 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
2759 + GPIO_afspare4_m = GPIO_pin10_m,
2760 + GPIO_afspare4_cfg_v = GPIO_input_v,
2761 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
2762 + GPIO_afspare3_m = GPIO_pin11_m,
2763 + GPIO_afspare3_cfg_v = GPIO_input_v,
2764 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
2765 + GPIO_afspare2_m = GPIO_pin12_m,
2766 + GPIO_afspare2_cfg_v = GPIO_input_v,
2767 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
2768 + GPIO_pcimuintn_m = GPIO_pin13_m,
2769 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
2770 +
2771 +} GPIO_DEFS_t;
2772 +
2773 +#endif // __IDT_GPIO_H__
2774 +
2775 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
2776 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
2777 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100
2778 @@ -0,0 +1,8 @@
2779 +#ifndef __ASM_MACH_MIPS_IRQ_H
2780 +#define __ASM_MACH_MIPS_IRQ_H
2781 +
2782 +#include <linux/autoconf.h>
2783 +
2784 +#define NR_IRQS 256
2785 +
2786 +#endif /* __ASM_MACH_MIPS_IRQ_H */
2787 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
2788 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
2789 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100
2790 @@ -0,0 +1,695 @@
2791 +/**************************************************************************
2792 + *
2793 + * BRIEF MODULE DESCRIPTION
2794 + * PCI register definitio
2795 + *
2796 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2797 + *
2798 + * This program is free software; you can redistribute it and/or modify it
2799 + * under the terms of the GNU General Public License as published by the
2800 + * Free Software Foundation; either version 2 of the License, or (at your
2801 + * option) any later version.
2802 + *
2803 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2804 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2805 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2806 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2807 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2808 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2809 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2810 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2811 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2812 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2813 + *
2814 + * You should have received a copy of the GNU General Public License along
2815 + * with this program; if not, write to the Free Software Foundation, Inc.,
2816 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2817 + *
2818 + *
2819 + **************************************************************************
2820 + * May 2004 rkt, neb.
2821 + *
2822 + * Initial Release
2823 + *
2824 + *
2825 + *
2826 + **************************************************************************
2827 + */
2828 +
2829 +#ifndef __IDT_PCI_H__
2830 +#define __IDT_PCI_H__
2831 +
2832 +enum
2833 +{
2834 + PCI0_PhysicalAddress = 0x18080000,
2835 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
2836 +
2837 + PCI0_VirtualAddress = 0xB8080000,
2838 + PCI_VirtualAddress = PCI0_VirtualAddress,
2839 +} ;
2840 +
2841 +enum
2842 +{
2843 + PCI_LbaCount = 4, // Local base addresses.
2844 +} ;
2845 +
2846 +typedef struct
2847 +{
2848 + u32 a ; // Address.
2849 + u32 c ; // Control.
2850 + u32 m ; // mapping.
2851 +} PCI_Map_s ;
2852 +
2853 +typedef struct
2854 +{
2855 + u32 pcic ;
2856 + u32 pcis ;
2857 + u32 pcism ;
2858 + u32 pcicfga ;
2859 + u32 pcicfgd ;
2860 + PCI_Map_s pcilba [PCI_LbaCount] ;
2861 + u32 pcidac ;
2862 + u32 pcidas ;
2863 + u32 pcidasm ;
2864 + u32 pcidad ;
2865 + u32 pcidma8c ;
2866 + u32 pcidma9c ;
2867 + u32 pcitc ;
2868 +} volatile *PCI_t ;
2869 +
2870 +// PCI messaging unit.
2871 +enum
2872 +{
2873 + PCIM_Count = 2,
2874 +} ;
2875 +typedef struct
2876 +{
2877 + u32 pciim [PCIM_Count] ;
2878 + u32 pciom [PCIM_Count] ;
2879 + u32 pciid ;
2880 + u32 pciiic ;
2881 + u32 pciiim ;
2882 + u32 pciiod ;
2883 + u32 pciioic ;
2884 + u32 pciioim ;
2885 +} volatile *PCIM_t ;
2886 +
2887 +/*******************************************************************************
2888 + *
2889 + * PCI Control Register
2890 + *
2891 + ******************************************************************************/
2892 +enum
2893 +{
2894 + PCIC_en_b = 0,
2895 + PCIC_en_m = 0x00000001,
2896 + PCIC_tnr_b = 1,
2897 + PCIC_tnr_m = 0x00000002,
2898 + PCIC_sce_b = 2,
2899 + PCIC_sce_m = 0x00000004,
2900 + PCIC_ien_b = 3,
2901 + PCIC_ien_m = 0x00000008,
2902 + PCIC_aaa_b = 4,
2903 + PCIC_aaa_m = 0x00000010,
2904 + PCIC_eap_b = 5,
2905 + PCIC_eap_m = 0x00000020,
2906 + PCIC_pcim_b = 6,
2907 + PCIC_pcim_m = 0x000001c0,
2908 + PCIC_pcim_disabled_v = 0,
2909 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
2910 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
2911 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
2912 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
2913 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
2914 + PCIC_pcim_reserved6_v = 6,
2915 + PCIC_pcim_reserved7_v = 7,
2916 + PCIC_igm_b = 9,
2917 + PCIC_igm_m = 0x00000200,
2918 +} ;
2919 +
2920 +/*******************************************************************************
2921 + *
2922 + * PCI Status Register
2923 + *
2924 + ******************************************************************************/
2925 +enum {
2926 + PCIS_eed_b = 0,
2927 + PCIS_eed_m = 0x00000001,
2928 + PCIS_wr_b = 1,
2929 + PCIS_wr_m = 0x00000002,
2930 + PCIS_nmi_b = 2,
2931 + PCIS_nmi_m = 0x00000004,
2932 + PCIS_ii_b = 3,
2933 + PCIS_ii_m = 0x00000008,
2934 + PCIS_cwe_b = 4,
2935 + PCIS_cwe_m = 0x00000010,
2936 + PCIS_cre_b = 5,
2937 + PCIS_cre_m = 0x00000020,
2938 + PCIS_mdpe_b = 6,
2939 + PCIS_mdpe_m = 0x00000040,
2940 + PCIS_sta_b = 7,
2941 + PCIS_sta_m = 0x00000080,
2942 + PCIS_rta_b = 8,
2943 + PCIS_rta_m = 0x00000100,
2944 + PCIS_rma_b = 9,
2945 + PCIS_rma_m = 0x00000200,
2946 + PCIS_sse_b = 10,
2947 + PCIS_sse_m = 0x00000400,
2948 + PCIS_ose_b = 11,
2949 + PCIS_ose_m = 0x00000800,
2950 + PCIS_pe_b = 12,
2951 + PCIS_pe_m = 0x00001000,
2952 + PCIS_tae_b = 13,
2953 + PCIS_tae_m = 0x00002000,
2954 + PCIS_rle_b = 14,
2955 + PCIS_rle_m = 0x00004000,
2956 + PCIS_bme_b = 15,
2957 + PCIS_bme_m = 0x00008000,
2958 + PCIS_prd_b = 16,
2959 + PCIS_prd_m = 0x00010000,
2960 + PCIS_rip_b = 17,
2961 + PCIS_rip_m = 0x00020000,
2962 +} ;
2963 +
2964 +/*******************************************************************************
2965 + *
2966 + * PCI Status Mask Register
2967 + *
2968 + ******************************************************************************/
2969 +enum {
2970 + PCISM_eed_b = 0,
2971 + PCISM_eed_m = 0x00000001,
2972 + PCISM_wr_b = 1,
2973 + PCISM_wr_m = 0x00000002,
2974 + PCISM_nmi_b = 2,
2975 + PCISM_nmi_m = 0x00000004,
2976 + PCISM_ii_b = 3,
2977 + PCISM_ii_m = 0x00000008,
2978 + PCISM_cwe_b = 4,
2979 + PCISM_cwe_m = 0x00000010,
2980 + PCISM_cre_b = 5,
2981 + PCISM_cre_m = 0x00000020,
2982 + PCISM_mdpe_b = 6,
2983 + PCISM_mdpe_m = 0x00000040,
2984 + PCISM_sta_b = 7,
2985 + PCISM_sta_m = 0x00000080,
2986 + PCISM_rta_b = 8,
2987 + PCISM_rta_m = 0x00000100,
2988 + PCISM_rma_b = 9,
2989 + PCISM_rma_m = 0x00000200,
2990 + PCISM_sse_b = 10,
2991 + PCISM_sse_m = 0x00000400,
2992 + PCISM_ose_b = 11,
2993 + PCISM_ose_m = 0x00000800,
2994 + PCISM_pe_b = 12,
2995 + PCISM_pe_m = 0x00001000,
2996 + PCISM_tae_b = 13,
2997 + PCISM_tae_m = 0x00002000,
2998 + PCISM_rle_b = 14,
2999 + PCISM_rle_m = 0x00004000,
3000 + PCISM_bme_b = 15,
3001 + PCISM_bme_m = 0x00008000,
3002 + PCISM_prd_b = 16,
3003 + PCISM_prd_m = 0x00010000,
3004 + PCISM_rip_b = 17,
3005 + PCISM_rip_m = 0x00020000,
3006 +} ;
3007 +
3008 +/*******************************************************************************
3009 + *
3010 + * PCI Configuration Address Register
3011 + *
3012 + ******************************************************************************/
3013 +enum {
3014 + PCICFGA_reg_b = 2,
3015 + PCICFGA_reg_m = 0x000000fc,
3016 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
3017 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
3018 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
3019 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
3020 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
3021 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
3022 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
3023 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
3024 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
3025 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
3026 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
3027 + PCICFGA_reg_pba0m_v = 0x48>>2,
3028 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
3029 + PCICFGA_reg_pba1m_v = 0x50>>2,
3030 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
3031 + PCICFGA_reg_pba2m_v = 0x58>>2,
3032 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
3033 + PCICFGA_reg_pba3m_v = 0x60>>2,
3034 + PCICFGA_reg_pmgt_v = 0x64>>2,
3035 + PCICFGA_func_b = 8,
3036 + PCICFGA_func_m = 0x00000700,
3037 + PCICFGA_dev_b = 11,
3038 + PCICFGA_dev_m = 0x0000f800,
3039 + PCICFGA_dev_internal_v = 0,
3040 + PCICFGA_bus_b = 16,
3041 + PCICFGA_bus_m = 0x00ff0000,
3042 + PCICFGA_bus_type0_v = 0, //local bus
3043 + PCICFGA_en_b = 31, // read only
3044 + PCICFGA_en_m = 0x80000000,
3045 +} ;
3046 +
3047 +enum {
3048 + PCFGID_vendor_b = 0,
3049 + PCFGID_vendor_m = 0x0000ffff,
3050 + PCFGID_vendor_IDT_v = 0x111d,
3051 + PCFGID_device_b = 16,
3052 + PCFGID_device_m = 0xffff0000,
3053 + PCFGID_device_Korinade_v = 0x0214,
3054 +
3055 + PCFG04_command_ioena_b = 1,
3056 + PCFG04_command_ioena_m = 0x00000001,
3057 + PCFG04_command_memena_b = 2,
3058 + PCFG04_command_memena_m = 0x00000002,
3059 + PCFG04_command_bmena_b = 3,
3060 + PCFG04_command_bmena_m = 0x00000004,
3061 + PCFG04_command_mwinv_b = 5,
3062 + PCFG04_command_mwinv_m = 0x00000010,
3063 + PCFG04_command_parena_b = 7,
3064 + PCFG04_command_parena_m = 0x00000040,
3065 + PCFG04_command_serrena_b = 9,
3066 + PCFG04_command_serrena_m = 0x00000100,
3067 + PCFG04_command_fastbbena_b = 10,
3068 + PCFG04_command_fastbbena_m = 0x00000200,
3069 + PCFG04_status_b = 16,
3070 + PCFG04_status_m = 0xffff0000,
3071 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
3072 + PCFG04_status_66MHz_m = 0x00200000,
3073 + PCFG04_status_fbb_b = 23,
3074 + PCFG04_status_fbb_m = 0x00800000,
3075 + PCFG04_status_mdpe_b = 24,
3076 + PCFG04_status_mdpe_m = 0x01000000,
3077 + PCFG04_status_dst_b = 25,
3078 + PCFG04_status_dst_m = 0x06000000,
3079 + PCFG04_status_sta_b = 27,
3080 + PCFG04_status_sta_m = 0x08000000,
3081 + PCFG04_status_rta_b = 28,
3082 + PCFG04_status_rta_m = 0x10000000,
3083 + PCFG04_status_rma_b = 29,
3084 + PCFG04_status_rma_m = 0x20000000,
3085 + PCFG04_status_sse_b = 30,
3086 + PCFG04_status_sse_m = 0x40000000,
3087 + PCFG04_status_pe_b = 31,
3088 + PCFG04_status_pe_m = 0x40000000,
3089 +
3090 + PCFG08_revId_b = 0,
3091 + PCFG08_revId_m = 0x000000ff,
3092 + PCFG08_classCode_b = 0,
3093 + PCFG08_classCode_m = 0xffffff00,
3094 + PCFG08_classCode_bridge_v = 06,
3095 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
3096 + PCFG0C_cacheline_b = 0,
3097 + PCFG0C_cacheline_m = 0x000000ff,
3098 + PCFG0C_masterLatency_b = 8,
3099 + PCFG0C_masterLatency_m = 0x0000ff00,
3100 + PCFG0C_headerType_b = 16,
3101 + PCFG0C_headerType_m = 0x00ff0000,
3102 + PCFG0C_bist_b = 24,
3103 + PCFG0C_bist_m = 0xff000000,
3104 +
3105 + PCIPBA_msi_b = 0,
3106 + PCIPBA_msi_m = 0x00000001,
3107 + PCIPBA_p_b = 3,
3108 + PCIPBA_p_m = 0x00000004,
3109 + PCIPBA_baddr_b = 8,
3110 + PCIPBA_baddr_m = 0xffffff00,
3111 +
3112 + PCFGSS_vendorId_b = 0,
3113 + PCFGSS_vendorId_m = 0x0000ffff,
3114 + PCFGSS_id_b = 16,
3115 + PCFGSS_id_m = 0xffff0000,
3116 +
3117 + PCFG3C_interruptLine_b = 0,
3118 + PCFG3C_interruptLine_m = 0x000000ff,
3119 + PCFG3C_interruptPin_b = 8,
3120 + PCFG3C_interruptPin_m = 0x0000ff00,
3121 + PCFG3C_minGrant_b = 16,
3122 + PCFG3C_minGrant_m = 0x00ff0000,
3123 + PCFG3C_maxLat_b = 24,
3124 + PCFG3C_maxLat_m = 0xff000000,
3125 +
3126 + PCIPBAC_msi_b = 0,
3127 + PCIPBAC_msi_m = 0x00000001,
3128 + PCIPBAC_p_b = 1,
3129 + PCIPBAC_p_m = 0x00000002,
3130 + PCIPBAC_size_b = 2,
3131 + PCIPBAC_size_m = 0x0000007c,
3132 + PCIPBAC_sb_b = 7,
3133 + PCIPBAC_sb_m = 0x00000080,
3134 + PCIPBAC_pp_b = 8,
3135 + PCIPBAC_pp_m = 0x00000100,
3136 + PCIPBAC_mr_b = 9,
3137 + PCIPBAC_mr_m = 0x00000600,
3138 + PCIPBAC_mr_read_v =0, //no prefetching
3139 + PCIPBAC_mr_readLine_v =1,
3140 + PCIPBAC_mr_readMult_v =2,
3141 + PCIPBAC_mrl_b = 11,
3142 + PCIPBAC_mrl_m = 0x00000800,
3143 + PCIPBAC_mrm_b = 12,
3144 + PCIPBAC_mrm_m = 0x00001000,
3145 + PCIPBAC_trp_b = 13,
3146 + PCIPBAC_trp_m = 0x00002000,
3147 +
3148 + PCFG40_trdyTimeout_b = 0,
3149 + PCFG40_trdyTimeout_m = 0x000000ff,
3150 + PCFG40_retryLim_b = 8,
3151 + PCFG40_retryLim_m = 0x0000ff00,
3152 +};
3153 +
3154 +/*******************************************************************************
3155 + *
3156 + * PCI Local Base Address [0|1|2|3] Register
3157 + *
3158 + ******************************************************************************/
3159 +enum {
3160 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
3161 + PCILBA_baddr_m = 0xffffff00,
3162 +} ;
3163 +/*******************************************************************************
3164 + *
3165 + * PCI Local Base Address Control Register
3166 + *
3167 + ******************************************************************************/
3168 +enum {
3169 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
3170 + PCILBAC_msi_m = 0x00000001,
3171 + PCILBAC_msi_mem_v = 0,
3172 + PCILBAC_msi_io_v = 1,
3173 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
3174 + PCILBAC_size_m = 0x0000007c,
3175 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
3176 + PCILBAC_sb_m = 0x00000080,
3177 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
3178 + PCILBAC_rt_m = 0x00000100,
3179 + PCILBAC_rt_noprefetch_v = 0, // mem read
3180 + PCILBAC_rt_prefetch_v = 1, // mem readline
3181 +} ;
3182 +
3183 +/*******************************************************************************
3184 + *
3185 + * PCI Local Base Address [0|1|2|3] Mapping Register
3186 + *
3187 + ******************************************************************************/
3188 +enum {
3189 + PCILBAM_maddr_b = 8,
3190 + PCILBAM_maddr_m = 0xffffff00,
3191 +} ;
3192 +
3193 +/*******************************************************************************
3194 + *
3195 + * PCI Decoupled Access Control Register
3196 + *
3197 + ******************************************************************************/
3198 +enum {
3199 + PCIDAC_den_b = 0,
3200 + PCIDAC_den_m = 0x00000001,
3201 +} ;
3202 +
3203 +/*******************************************************************************
3204 + *
3205 + * PCI Decoupled Access Status Register
3206 + *
3207 + ******************************************************************************/
3208 +enum {
3209 + PCIDAS_d_b = 0,
3210 + PCIDAS_d_m = 0x00000001,
3211 + PCIDAS_b_b = 1,
3212 + PCIDAS_b_m = 0x00000002,
3213 + PCIDAS_e_b = 2,
3214 + PCIDAS_e_m = 0x00000004,
3215 + PCIDAS_ofe_b = 3,
3216 + PCIDAS_ofe_m = 0x00000008,
3217 + PCIDAS_off_b = 4,
3218 + PCIDAS_off_m = 0x00000010,
3219 + PCIDAS_ife_b = 5,
3220 + PCIDAS_ife_m = 0x00000020,
3221 + PCIDAS_iff_b = 6,
3222 + PCIDAS_iff_m = 0x00000040,
3223 +} ;
3224 +
3225 +/*******************************************************************************
3226 + *
3227 + * PCI DMA Channel 8 Configuration Register
3228 + *
3229 + ******************************************************************************/
3230 +enum
3231 +{
3232 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
3233 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
3234 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
3235 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
3236 +} ;
3237 +
3238 +/*******************************************************************************
3239 + *
3240 + * PCI DMA Channel 9 Configuration Register
3241 + *
3242 + ******************************************************************************/
3243 +enum
3244 +{
3245 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
3246 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
3247 +} ;
3248 +
3249 +/*******************************************************************************
3250 + *
3251 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
3252 + *
3253 + ******************************************************************************/
3254 +enum {
3255 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
3256 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
3257 + // These are for reads (DMA channel 8)
3258 + PCIDMAD_devcmd_mr_v = 0, //memory read
3259 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
3260 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
3261 + PCIDMAD_devcmd_ior_v = 3, //I/O read
3262 + // These are for writes (DMA channel 9)
3263 + PCIDMAD_devcmd_mw_v = 0, //memory write
3264 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
3265 + PCIDMAD_devcmd_iow_v = 3, //I/O write
3266 +
3267 + // Swap byte field applies to both DMA channel 8 and 9
3268 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
3269 + PCIDMAD_sb_m = 0x01000000, // swap byte field
3270 +} ;
3271 +
3272 +
3273 +/*******************************************************************************
3274 + *
3275 + * PCI Target Control Register
3276 + *
3277 + ******************************************************************************/
3278 +enum
3279 +{
3280 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
3281 + PCITC_rtimer_m = 0x000000ff,
3282 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
3283 + PCITC_dtimer_m = 0x0000ff00,
3284 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
3285 + PCITC_rdr_m = 0x00040000,
3286 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
3287 + PCITC_ddt_m = 0x00080000,
3288 +} ;
3289 +/*******************************************************************************
3290 + *
3291 + * PCI messaging unit [applies to both inbound and outbound registers ]
3292 + *
3293 + ******************************************************************************/
3294 +enum
3295 +{
3296 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3297 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
3298 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3299 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
3300 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3301 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
3302 +};
3303 +
3304 +
3305 +
3306 +
3307 +
3308 +
3309 +#define PCI_MSG_VirtualAddress 0xB8088010
3310 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
3311 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
3312 +
3313 +#define PCIM_SHFT 0x6
3314 +#define PCIM_BIT_LEN 0x7
3315 +#define PCIM_H_EA 0x3
3316 +#define PCIM_H_IA_FIX 0x4
3317 +#define PCIM_H_IA_RR 0x5
3318 +#if 0
3319 +#define PCI_ADDR_START 0x13000000
3320 +#endif
3321 +
3322 +#define PCI_ADDR_START 0x50000000
3323 +
3324 +#define CPUTOPCI_MEM_WIN 0x02000000
3325 +#define CPUTOPCI_IO_WIN 0x00100000
3326 +#define PCILBA_SIZE_SHFT 2
3327 +#define PCILBA_SIZE_MASK 0x1F
3328 +#define SIZE_256MB 0x1C
3329 +#define SIZE_128MB 0x1B
3330 +#define SIZE_64MB 0x1A
3331 +#define SIZE_32MB 0x19
3332 +#define SIZE_16MB 0x18
3333 +#define SIZE_4MB 0x16
3334 +#define SIZE_2MB 0x15
3335 +#define SIZE_1MB 0x14
3336 +#define KORINA_CONFIG0_ADDR 0x80000000
3337 +#define KORINA_CONFIG1_ADDR 0x80000004
3338 +#define KORINA_CONFIG2_ADDR 0x80000008
3339 +#define KORINA_CONFIG3_ADDR 0x8000000C
3340 +#define KORINA_CONFIG4_ADDR 0x80000010
3341 +#define KORINA_CONFIG5_ADDR 0x80000014
3342 +#define KORINA_CONFIG6_ADDR 0x80000018
3343 +#define KORINA_CONFIG7_ADDR 0x8000001C
3344 +#define KORINA_CONFIG8_ADDR 0x80000020
3345 +#define KORINA_CONFIG9_ADDR 0x80000024
3346 +#define KORINA_CONFIG10_ADDR 0x80000028
3347 +#define KORINA_CONFIG11_ADDR 0x8000002C
3348 +#define KORINA_CONFIG12_ADDR 0x80000030
3349 +#define KORINA_CONFIG13_ADDR 0x80000034
3350 +#define KORINA_CONFIG14_ADDR 0x80000038
3351 +#define KORINA_CONFIG15_ADDR 0x8000003C
3352 +#define KORINA_CONFIG16_ADDR 0x80000040
3353 +#define KORINA_CONFIG17_ADDR 0x80000044
3354 +#define KORINA_CONFIG18_ADDR 0x80000048
3355 +#define KORINA_CONFIG19_ADDR 0x8000004C
3356 +#define KORINA_CONFIG20_ADDR 0x80000050
3357 +#define KORINA_CONFIG21_ADDR 0x80000054
3358 +#define KORINA_CONFIG22_ADDR 0x80000058
3359 +#define KORINA_CONFIG23_ADDR 0x8000005C
3360 +#define KORINA_CONFIG24_ADDR 0x80000060
3361 +#define KORINA_CONFIG25_ADDR 0x80000064
3362 +#define KORINA_CMD (PCFG04_command_ioena_m | \
3363 + PCFG04_command_memena_m | \
3364 + PCFG04_command_bmena_m | \
3365 + PCFG04_command_mwinv_m | \
3366 + PCFG04_command_parena_m | \
3367 + PCFG04_command_serrena_m )
3368 +
3369 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
3370 + PCFG04_status_sta_m | \
3371 + PCFG04_status_rta_m | \
3372 + PCFG04_status_rma_m | \
3373 + PCFG04_status_sse_m | \
3374 + PCFG04_status_pe_m)
3375 +
3376 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
3377 +
3378 +#define KORINA_REVID 0
3379 +#define KORINA_CLASS_CODE 0
3380 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
3381 + KORINA_REVID)
3382 +
3383 +#define KORINA_CACHE_LINE_SIZE 4
3384 +#define KORINA_MASTER_LAT 0x3c
3385 +#define KORINA_HEADER_TYPE 0
3386 +#define KORINA_BIST 0
3387 +
3388 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
3389 + (KORINA_HEADER_TYPE<<16) | \
3390 + (KORINA_MASTER_LAT<<8) | \
3391 + KORINA_CACHE_LINE_SIZE )
3392 +
3393 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
3394 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
3395 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
3396 + internal Registers */
3397 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
3398 +
3399 +#define KORINA_CNFG4 KORINA_BAR0
3400 +#define KORINA_CNFG5 KORINA_BAR1
3401 +#define KORINA_CNFG6 KORINA_BAR2
3402 +#define KORINA_CNFG7 KORINA_BAR3
3403 +
3404 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
3405 +#define KORINA_SUBSYSTEM_ID 0x0214
3406 +#define KORINA_CNFG8 0
3407 +#define KORINA_CNFG9 0
3408 +#define KORINA_CNFG10 0
3409 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
3410 + KORINA_SUBSYSTEM_ID)
3411 +#define KORINA_INT_LINE 1
3412 +#define KORINA_INT_PIN 1
3413 +#define KORINA_MIN_GNT 8
3414 +#define KORINA_MAX_LAT 0x38
3415 +#define KORINA_CNFG12 0
3416 +#define KORINA_CNFG13 0
3417 +#define KORINA_CNFG14 0
3418 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
3419 + (KORINA_MIN_GNT<<16) | \
3420 + (KORINA_INT_PIN<<8) | \
3421 + KORINA_INT_LINE)
3422 +#define KORINA_RETRY_LIMIT 0x80
3423 +#define KORINA_TRDY_LIMIT 0x80
3424 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
3425 + KORINA_TRDY_LIMIT)
3426 +#define PCI_PBAxC_R 0x0
3427 +#define PCI_PBAxC_RL 0x1
3428 +#define PCI_PBAxC_RM 0x2
3429 +#define SIZE_SHFT 2
3430 +
3431 +#if defined(__MIPSEB__)
3432 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
3433 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3434 + PCIPBAC_pp_m | \
3435 + (SIZE_128MB<<SIZE_SHFT) | \
3436 + PCIPBAC_p_m)
3437 +#else
3438 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
3439 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3440 + PCIPBAC_pp_m | \
3441 + (SIZE_128MB<<SIZE_SHFT) | \
3442 + PCIPBAC_p_m)
3443 +#endif
3444 +#define KORINA_CNFG17 KORINA_PBA0C
3445 +#define KORINA_PBA0M 0x0
3446 +#define KORINA_CNFG18 KORINA_PBA0M
3447 +
3448 +#if defined(__MIPSEB__)
3449 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3450 + PCIPBAC_msi_m)
3451 +#else
3452 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
3453 + PCIPBAC_msi_m)
3454 +#endif
3455 +#define KORINA_CNFG19 KORINA_PBA1C
3456 +#define KORINA_PBA1M 0x0
3457 +#define KORINA_CNFG20 KORINA_PBA1M
3458 +
3459 +#if defined(__MIPSEB__)
3460 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3461 + PCIPBAC_msi_m)
3462 +#else
3463 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
3464 + PCIPBAC_msi_m)
3465 +#endif
3466 +#define KORINA_CNFG21 KORINA_PBA2C
3467 +#define KORINA_PBA2M 0x18000000
3468 +#define KORINA_CNFG22 KORINA_PBA2M
3469 +#define KORINA_PBA3C 0
3470 +#define KORINA_CNFG23 KORINA_PBA3C
3471 +#define KORINA_PBA3M 0
3472 +#define KORINA_CNFG24 KORINA_PBA3M
3473 +
3474 +
3475 +
3476 +#define PCITC_DTIMER_VAL 8
3477 +#define PCITC_RTIMER_VAL 0x10
3478 +
3479 +
3480 +
3481 +
3482 +#endif // __IDT_PCI_H__
3483 +
3484 +
3485 +
3486 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
3487 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
3488 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-12-14 04:09:50.000000000 +0100
3489 @@ -0,0 +1,84 @@
3490 +/*
3491 + * Copyright (C) 2004 IDT Inc.
3492 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
3493 + *
3494 + * This program is free software; you can redistribute it and/or modify
3495 + * it under the terms of the GNU General Public License as published by
3496 + * the Free Software Foundation; either version 2 of the License, or
3497 + * (at your option) any later version.
3498 + *
3499 + * This program is distributed in the hope that it will be useful,
3500 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3501 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3502 + * GNU General Public License for more details.
3503 + *
3504 + */
3505 +#ifndef __MIPS_RB_H__
3506 +#define __MIPS_RB_H__
3507 +#include <linux/genhd.h>
3508 +
3509 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
3510 +#define DEV0BASE 0x010000
3511 +#define DEV0MASK 0x010004
3512 +#define DEV0C 0x010008
3513 +#define DEV0TC 0x01000C
3514 +#define DEV1BASE 0x010010
3515 +#define DEV1MASK 0x010014
3516 +#define DEV1C 0x010018
3517 +#define DEV1TC 0x01001C
3518 +#define DEV2BASE 0x010020
3519 +#define DEV2MASK 0x010024
3520 +#define DEV2C 0x010028
3521 +#define DEV2TC 0x01002C
3522 +#define DEV3BASE 0x010030
3523 +#define DEV3MASK 0x010034
3524 +#define DEV3C 0x010038
3525 +#define DEV3TC 0x01003C
3526 +#define BTCS 0x010040
3527 +#define BTCOMPARE 0x010044
3528 +#define GPIOFUNC 0x050000
3529 +#define GPIOCFG 0x050004
3530 +#define GPIOD 0x050008
3531 +#define GPIOILEVEL 0x05000C
3532 +#define GPIOISTAT 0x050010
3533 +#define GPIONMIEN 0x050014
3534 +#define IMASK6 0x038038
3535 +
3536 +#define LO_WPX (1 << 0)
3537 +#define LO_ALE (1 << 1)
3538 +#define LO_CLE (1 << 2)
3539 +#define LO_CEX (1 << 3)
3540 +#define LO_FOFF (1 << 5)
3541 +#define LO_SPICS (1 << 6)
3542 +#define LO_ULED (1 << 7)
3543 +
3544 +typedef enum {
3545 + FUNC = 0x00,
3546 + CFG = 0x04,
3547 + DATA = 0x08,
3548 + ILEVEL = 0x0c,
3549 + ISTAT = 0x10,
3550 + NMIEN = 0x14
3551 +} gpio_func;
3552 +
3553 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
3554 +extern unsigned get434Reg(unsigned regOffs);
3555 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
3556 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
3557 +extern u32 gpio_get(gpio_func func);
3558 +
3559 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
3560 +
3561 +struct korina_device {
3562 + char *name;
3563 + unsigned char mac[6];
3564 + struct net_device *dev;
3565 +};
3566 +
3567 +struct cf_device {
3568 + int gpio_pin;
3569 + void *dev;
3570 + struct gendisk *gd;
3571 +};
3572 +
3573 +#endif
3574 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
3575 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
3576 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-12-14 04:09:50.000000000 +0100
3577 @@ -0,0 +1,122 @@
3578 +/*
3579 + ***************************************************************************
3580 + * Definitions for IDT RC323434 CPU.
3581 + *
3582 + ****************************************************************************
3583 + * Kiran Rao
3584 + *
3585 + * Original form
3586 + ****************************************************************************
3587 + * P. Sadik Oct 08, 2003
3588 + *
3589 + * Started revision history
3590 + * Made IDT_BUS_FREQ a kernel configuration parameter
3591 + ****************************************************************************
3592 + * P. Sadik Oct 10, 2003
3593 + *
3594 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
3595 + * idt_cpu_freq is used everywhere
3596 + ****************************************************************************
3597 + * P. Sadik Oct 20, 2003
3598 + *
3599 + * Removed RC32434_BASE_BAUD
3600 + ****************************************************************************
3601 +*/
3602 +#ifndef _RC32434_H_
3603 +#define _RC32434_H_
3604 +
3605 +#include <linux/autoconf.h>
3606 +#include <linux/delay.h>
3607 +#include <asm/io.h>
3608 +
3609 +#define RC32434_REG_BASE 0x18000000
3610 +
3611 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
3612 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
3613 +
3614 +
3615 +#define IDT_CLOCK_MULT 2
3616 +#define MIPS_CPU_TIMER_IRQ 7
3617 +/* Interrupt Controller */
3618 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
3619 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
3620 +#define IC_GROUP_OFFSET 0x0C
3621 +
3622 +#define NUM_INTR_GROUPS 5
3623 +/* 16550 UARTs */
3624 +
3625 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
3626 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
3627 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
3628 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
3629 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
3630 +
3631 +
3632 +#ifdef __MIPSEB__
3633 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
3634 +#else
3635 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
3636 +#endif
3637 +
3638 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
3639 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
3640 +
3641 +#define local_readl(addr) __raw_readl(addr)
3642 +#define local_writel(l,addr) __raw_writel(l,addr)
3643 +
3644 +/* cpu pipeline flush */
3645 +static inline void rc32434_sync(void)
3646 +{
3647 + __asm__ volatile ("sync");
3648 +}
3649 +
3650 +static inline void rc32434_sync_udelay(int us)
3651 +{
3652 + __asm__ volatile ("sync");
3653 + udelay(us);
3654 +}
3655 +
3656 +static inline void rc32434_sync_delay(int ms)
3657 +{
3658 + __asm__ volatile ("sync");
3659 + mdelay(ms);
3660 +}
3661 +
3662 +/*
3663 + * C access to CLZ and CLO instructions
3664 + * (count leading zeroes/ones).
3665 + */
3666 +static inline int rc32434_clz(unsigned long val)
3667 +{
3668 + int ret;
3669 + __asm__ volatile (
3670 + ".set\tnoreorder\n\t"
3671 + ".set\tnoat\n\t"
3672 + ".set\tmips32\n\t"
3673 + "clz\t%0,%1\n\t"
3674 + ".set\tmips0\n\t"
3675 + ".set\tat\n\t"
3676 + ".set\treorder"
3677 + : "=r" (ret)
3678 + : "r" (val));
3679 +
3680 + return ret;
3681 +}
3682 +static inline int rc32434_clo(unsigned long val)
3683 +{
3684 + int ret;
3685 + __asm__ volatile (
3686 + ".set\tnoreorder\n\t"
3687 + ".set\tnoat\n\t"
3688 + ".set\tmips32\n\t"
3689 + "clo\t%0,%1\n\t"
3690 + ".set\tmips0\n\t"
3691 + ".set\tat\n\t"
3692 + ".set\treorder"
3693 + : "=r" (ret)
3694 + : "r" (val));
3695 +
3696 + return ret;
3697 +}
3698 +
3699 +#endif /* _RC32434_H_ */
3700
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