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ar71xx: the watchdog uses the reference clock on the AR933x SoCs
[openwrt.git] / target / linux / ar71xx / files / drivers / spi / spi_vsc7385.c
1 /*
2 * SPI driver for the Vitesse VSC7385 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Atheros' 2.6.15 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/bitops.h>
20 #include <linux/firmware.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/vsc7385.h>
23
24 #define DRV_NAME "spi-vsc7385"
25 #define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver"
26 #define DRV_VERSION "0.1.0"
27
28 #define VSC73XX_BLOCK_MAC 0x1
29 #define VSC73XX_BLOCK_2 0x2
30 #define VSC73XX_BLOCK_MII 0x3
31 #define VSC73XX_BLOCK_4 0x4
32 #define VSC73XX_BLOCK_5 0x5
33 #define VSC73XX_BLOCK_SYSTEM 0x7
34
35 #define VSC73XX_SUBBLOCK_PORT_0 0
36 #define VSC73XX_SUBBLOCK_PORT_1 1
37 #define VSC73XX_SUBBLOCK_PORT_2 2
38 #define VSC73XX_SUBBLOCK_PORT_3 3
39 #define VSC73XX_SUBBLOCK_PORT_4 4
40 #define VSC73XX_SUBBLOCK_PORT_MAC 6
41
42 /* MAC Block registers */
43 #define VSC73XX_MAC_CFG 0x0
44 #define VSC73XX_ADVPORTM 0x19
45 #define VSC73XX_RXOCT 0x50
46 #define VSC73XX_TXOCT 0x51
47 #define VSC73XX_C_RX0 0x52
48 #define VSC73XX_C_RX1 0x53
49 #define VSC73XX_C_RX2 0x54
50 #define VSC73XX_C_TX0 0x55
51 #define VSC73XX_C_TX1 0x56
52 #define VSC73XX_C_TX2 0x57
53 #define VSC73XX_C_CFG 0x58
54
55 /* MAC_CFG register bits */
56 #define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31)
57 #define VSC73XX_MAC_CFG_PORT_RST (1 << 29)
58 #define VSC73XX_MAC_CFG_TX_EN (1 << 28)
59 #define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27)
60 #define VSC73XX_MAC_CFG_FDX (1 << 18)
61 #define VSC73XX_MAC_CFG_GIGE (1 << 17)
62 #define VSC73XX_MAC_CFG_RX_EN (1 << 16)
63 #define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15)
64 #define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14)
65 #define VSC73XX_MAC_CFG_100_BASE_T (1 << 13)
66 #define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6)
67 #define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5)
68 #define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4)
69 #define VSC73XX_MAC_CFG_BIT2 (1 << 2)
70 #define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3)
71
72 /* ADVPORTM register bits */
73 #define VSC73XX_ADVPORTM_IFG_PPM (1 << 7)
74 #define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6)
75 #define VSC73XX_ADVPORTM_EXT_PORT (1 << 5)
76 #define VSC73XX_ADVPORTM_INV_GTX (1 << 4)
77 #define VSC73XX_ADVPORTM_ENA_GTX (1 << 3)
78 #define VSC73XX_ADVPORTM_DDR_MODE (1 << 2)
79 #define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1)
80 #define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0)
81
82 /* MII Block registers */
83 #define VSC73XX_MII_STAT 0x0
84 #define VSC73XX_MII_CMD 0x1
85 #define VSC73XX_MII_DATA 0x2
86
87 /* System Block registers */
88 #define VSC73XX_ICPU_SIPAD 0x01
89 #define VSC73XX_ICPU_CLOCK_DELAY 0x05
90 #define VSC73XX_ICPU_CTRL 0x10
91 #define VSC73XX_ICPU_ADDR 0x11
92 #define VSC73XX_ICPU_SRAM 0x12
93 #define VSC73XX_ICPU_MBOX_VAL 0x15
94 #define VSC73XX_ICPU_MBOX_SET 0x16
95 #define VSC73XX_ICPU_MBOX_CLR 0x17
96 #define VSC73XX_ICPU_CHIPID 0x18
97 #define VSC73XX_ICPU_GPIO 0x34
98
99 #define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8)
100 #define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7)
101 #define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3)
102 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2)
103 #define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1)
104 #define VSC73XX_ICPU_CTRL_SRST (1 << 0)
105
106 #define VSC73XX_ICPU_CHIPID_ID_SHIFT 12
107 #define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff
108 #define VSC73XX_ICPU_CHIPID_REV_SHIFT 28
109 #define VSC73XX_ICPU_CHIPID_REV_MASK 0xf
110 #define VSC73XX_ICPU_CHIPID_ID_7385 0x7385
111 #define VSC73XX_ICPU_CHIPID_ID_7395 0x7395
112
113 #define VSC73XX_CMD_MODE_READ 0
114 #define VSC73XX_CMD_MODE_WRITE 1
115 #define VSC73XX_CMD_MODE_SHIFT 4
116 #define VSC73XX_CMD_BLOCK_SHIFT 5
117 #define VSC73XX_CMD_BLOCK_MASK 0x7
118 #define VSC73XX_CMD_SUBBLOCK_MASK 0xf
119
120 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
121 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
122
123 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
124 VSC73XX_ICPU_CTRL_BOOT_EN | \
125 VSC73XX_ICPU_CTRL_EXT_ACC_EN)
126
127 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
128 VSC73XX_ICPU_CTRL_BOOT_EN | \
129 VSC73XX_ICPU_CTRL_CLK_EN | \
130 VSC73XX_ICPU_CTRL_SRST)
131
132 #define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \
133 VSC73XX_ADVPORTM_EXC_COL_CONT | \
134 VSC73XX_ADVPORTM_EXT_PORT | \
135 VSC73XX_ADVPORTM_INV_GTX | \
136 VSC73XX_ADVPORTM_ENA_GTX | \
137 VSC73XX_ADVPORTM_DDR_MODE | \
138 VSC73XX_ADVPORTM_IO_LOOPBACK | \
139 VSC73XX_ADVPORTM_HOST_LOOPBACK)
140
141 #define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \
142 VSC73XX_ADVPORTM_ENA_GTX | \
143 VSC73XX_ADVPORTM_DDR_MODE)
144
145 #define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
146 VSC73XX_MAC_CFG_MAC_RX_RST | \
147 VSC73XX_MAC_CFG_MAC_TX_RST)
148
149 #define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \
150 VSC73XX_MAC_CFG_FDX | \
151 VSC73XX_MAC_CFG_GIGE | \
152 VSC73XX_MAC_CFG_RX_EN)
153
154 #define VSC73XX_RESET_DELAY 100
155
156 struct vsc7385 {
157 struct spi_device *spi;
158 struct mutex lock;
159 struct vsc7385_platform_data *pdata;
160 };
161
162 static int vsc7385_is_addr_valid(u8 block, u8 subblock)
163 {
164 switch (block) {
165 case VSC73XX_BLOCK_MAC:
166 switch (subblock) {
167 case 0 ... 4:
168 case 6:
169 return 1;
170 }
171 break;
172
173 case VSC73XX_BLOCK_2:
174 case VSC73XX_BLOCK_SYSTEM:
175 switch (subblock) {
176 case 0:
177 return 1;
178 }
179 break;
180
181 case VSC73XX_BLOCK_MII:
182 case VSC73XX_BLOCK_4:
183 case VSC73XX_BLOCK_5:
184 switch (subblock) {
185 case 0 ... 1:
186 return 1;
187 }
188 break;
189 }
190
191 return 0;
192 }
193
194 static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock)
195 {
196 u8 ret;
197
198 ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT;
199 ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT;
200 ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK;
201
202 return ret;
203 }
204
205 static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
206 u32 *value)
207 {
208 u8 cmd[4];
209 u8 buf[4];
210 struct spi_transfer t[2];
211 struct spi_message m;
212 int err;
213
214 if (!vsc7385_is_addr_valid(block, subblock))
215 return -EINVAL;
216
217 spi_message_init(&m);
218
219 memset(&t, 0, sizeof(t));
220
221 t[0].tx_buf = cmd;
222 t[0].len = sizeof(cmd);
223 spi_message_add_tail(&t[0], &m);
224
225 t[1].rx_buf = buf;
226 t[1].len = sizeof(buf);
227 spi_message_add_tail(&t[1], &m);
228
229 cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock);
230 cmd[1] = reg;
231 cmd[2] = 0;
232 cmd[3] = 0;
233
234 mutex_lock(&vsc->lock);
235 err = spi_sync(vsc->spi, &m);
236 mutex_unlock(&vsc->lock);
237
238 if (err)
239 return err;
240
241 *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) |
242 (((u32) buf[2]) << 8) | ((u32) buf[3]);
243
244 return 0;
245 }
246
247
248 static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
249 u32 value)
250 {
251 u8 cmd[2];
252 u8 buf[4];
253 struct spi_transfer t[2];
254 struct spi_message m;
255 int err;
256
257 if (!vsc7385_is_addr_valid(block, subblock))
258 return -EINVAL;
259
260 spi_message_init(&m);
261
262 memset(&t, 0, sizeof(t));
263
264 t[0].tx_buf = cmd;
265 t[0].len = sizeof(cmd);
266 spi_message_add_tail(&t[0], &m);
267
268 t[1].tx_buf = buf;
269 t[1].len = sizeof(buf);
270 spi_message_add_tail(&t[1], &m);
271
272 cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock);
273 cmd[1] = reg;
274
275 buf[0] = (value >> 24) & 0xff;
276 buf[1] = (value >> 16) & 0xff;
277 buf[2] = (value >> 8) & 0xff;
278 buf[3] = value & 0xff;
279
280 mutex_lock(&vsc->lock);
281 err = spi_sync(vsc->spi, &m);
282 mutex_unlock(&vsc->lock);
283
284 return err;
285 }
286
287 static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block,
288 u8 subblock, u8 reg, u32 value,
289 u32 read_mask, u32 read_val)
290 {
291 struct spi_device *spi = vsc->spi;
292 u32 t;
293 int err;
294
295 err = vsc7385_write(vsc, block, subblock, reg, value);
296 if (err)
297 return err;
298
299 err = vsc7385_read(vsc, block, subblock, reg, &t);
300 if (err)
301 return err;
302
303 if ((t & read_mask) != read_val) {
304 dev_err(&spi->dev, "register write error\n");
305 return -EIO;
306 }
307
308 return 0;
309 }
310
311 static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val)
312 {
313 return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
314 VSC73XX_ICPU_CLOCK_DELAY, val);
315 }
316
317 static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val)
318 {
319 return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
320 VSC73XX_ICPU_CLOCK_DELAY, val);
321 }
322
323 static inline int vsc7385_icpu_stop(struct vsc7385 *vsc)
324 {
325 return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
326 VSC73XX_ICPU_CTRL_STOP);
327 }
328
329 static inline int vsc7385_icpu_start(struct vsc7385 *vsc)
330 {
331 return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
332 VSC73XX_ICPU_CTRL_START);
333 }
334
335 static inline int vsc7385_icpu_reset(struct vsc7385 *vsc)
336 {
337 int rc;
338
339 rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR,
340 0x0000);
341 if (rc)
342 dev_err(&vsc->spi->dev,
343 "could not reset microcode, err=%d\n", rc);
344
345 return rc;
346 }
347
348 static int vsc7385_upload_ucode(struct vsc7385 *vsc)
349 {
350 struct spi_device *spi = vsc->spi;
351 const struct firmware *firmware;
352 char *ucode_name;
353 unsigned char *dp;
354 unsigned int curVal;
355 int i;
356 int diffs;
357 int rc;
358
359 ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name
360 : "vsc7385_ucode.bin";
361 rc = request_firmware(&firmware, ucode_name, &spi->dev);
362 if (rc) {
363 dev_err(&spi->dev, "request_firmware failed, err=%d\n",
364 rc);
365 return rc;
366 }
367
368 rc = vsc7385_icpu_stop(vsc);
369 if (rc)
370 goto out;
371
372 rc = vsc7385_icpu_reset(vsc);
373 if (rc)
374 goto out;
375
376 dev_info(&spi->dev, "uploading microcode...\n");
377
378 dp = (unsigned char *) firmware->data;
379 for (i = 0; i < firmware->size; i++) {
380 rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
381 VSC73XX_ICPU_SRAM, *dp++);
382 if (rc) {
383 dev_err(&spi->dev, "could not load microcode, err=%d\n",
384 rc);
385 goto out;
386 }
387 }
388
389 rc = vsc7385_icpu_reset(vsc);
390 if (rc)
391 goto out;
392
393 dev_info(&spi->dev, "verifying microcode...\n");
394
395 dp = (unsigned char *) firmware->data;
396 diffs = 0;
397 for (i = 0; i < firmware->size; i++) {
398 rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
399 VSC73XX_ICPU_SRAM, &curVal);
400 if (rc) {
401 dev_err(&spi->dev, "could not read microcode %d\n",
402 rc);
403 goto out;
404 }
405
406 if (curVal > 0xff) {
407 dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n",
408 i, *dp, curVal);
409 rc = -EIO;
410 goto out;
411 }
412
413 if ((curVal & 0xff) != *dp) {
414 diffs++;
415 dev_err(&spi->dev, "verify error: %04x : %02x %02x\n",
416 i, *dp, curVal);
417
418 if (diffs > 4)
419 break;
420 }
421 dp++;
422 }
423
424 if (diffs) {
425 dev_err(&spi->dev, "microcode verification failed\n");
426 rc = -EIO;
427 goto out;
428 }
429
430 dev_info(&spi->dev, "microcode uploaded\n");
431
432 rc = vsc7385_icpu_start(vsc);
433
434 out:
435 release_firmware(firmware);
436 return rc;
437 }
438
439 static int vsc7385_setup(struct vsc7385 *vsc)
440 {
441 struct vsc7385_platform_data *pdata = vsc->pdata;
442 u32 t;
443 int err;
444
445 err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0,
446 VSC73XX_ICPU_CLOCK_DELAY,
447 VSC7385_CLOCK_DELAY,
448 VSC7385_CLOCK_DELAY_MASK,
449 VSC7385_CLOCK_DELAY);
450 if (err)
451 goto err;
452
453 err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC,
454 VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM,
455 VSC7385_ADVPORTM_INIT,
456 VSC7385_ADVPORTM_MASK,
457 VSC7385_ADVPORTM_INIT);
458 if (err)
459 goto err;
460
461 err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
462 VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET);
463 if (err)
464 goto err;
465
466 t = VSC73XX_MAC_CFG_INIT;
467 t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg);
468 t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel);
469 if (pdata->mac_cfg.bit2)
470 t |= VSC73XX_MAC_CFG_BIT2;
471
472 err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
473 VSC73XX_MAC_CFG, t);
474 if (err)
475 goto err;
476
477 return 0;
478
479 err:
480 return err;
481 }
482
483 static int vsc7385_detect(struct vsc7385 *vsc)
484 {
485 struct spi_device *spi = vsc->spi;
486 u32 t;
487 u32 id;
488 u32 rev;
489 int err;
490
491 err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
492 VSC73XX_ICPU_MBOX_VAL, &t);
493 if (err) {
494 dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err);
495 return err;
496 }
497
498 if (t == 0xffffffff) {
499 dev_dbg(&spi->dev, "assert chip reset\n");
500 if (vsc->pdata->reset)
501 vsc->pdata->reset();
502
503 }
504
505 err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
506 VSC73XX_ICPU_CHIPID, &t);
507 if (err) {
508 dev_err(&spi->dev, "unable to read chip id, err=%d\n", err);
509 return err;
510 }
511
512 id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK;
513 switch (id) {
514 case VSC73XX_ICPU_CHIPID_ID_7385:
515 case VSC73XX_ICPU_CHIPID_ID_7395:
516 break;
517 default:
518 dev_err(&spi->dev, "unsupported chip, id=%04x\n", id);
519 return -ENODEV;
520 }
521
522 rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) &
523 VSC73XX_ICPU_CHIPID_REV_MASK;
524 dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev);
525
526 return 0;
527 }
528
529 static int __devinit vsc7385_probe(struct spi_device *spi)
530 {
531 struct vsc7385 *vsc;
532 struct vsc7385_platform_data *pdata;
533 int err;
534
535 printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n");
536
537 pdata = spi->dev.platform_data;
538 if (!pdata) {
539 dev_err(&spi->dev, "no platform data specified\n");
540 return -ENODEV;
541 }
542
543 vsc = kzalloc(sizeof(*vsc), GFP_KERNEL);
544 if (!vsc) {
545 dev_err(&spi->dev, "no memory for private data\n");
546 return -ENOMEM;
547 }
548
549 mutex_init(&vsc->lock);
550 vsc->pdata = pdata;
551 vsc->spi = spi_dev_get(spi);
552 dev_set_drvdata(&spi->dev, vsc);
553
554 spi->mode = SPI_MODE_0;
555 spi->bits_per_word = 8;
556 err = spi_setup(spi);
557 if (err) {
558 dev_err(&spi->dev, "spi_setup failed, err=%d\n", err);
559 goto err_drvdata;
560 }
561
562 err = vsc7385_detect(vsc);
563 if (err) {
564 dev_err(&spi->dev, "no chip found, err=%d\n", err);
565 goto err_drvdata;
566 }
567
568 err = vsc7385_upload_ucode(vsc);
569 if (err)
570 goto err_drvdata;
571
572 err = vsc7385_setup(vsc);
573 if (err)
574 goto err_drvdata;
575
576 return 0;
577
578 err_drvdata:
579 dev_set_drvdata(&spi->dev, NULL);
580 kfree(vsc);
581 return err;
582 }
583
584 static int __devexit vsc7385_remove(struct spi_device *spi)
585 {
586 struct vsc7385_data *vsc;
587
588 vsc = dev_get_drvdata(&spi->dev);
589 dev_set_drvdata(&spi->dev, NULL);
590 kfree(vsc);
591
592 return 0;
593 }
594
595 static struct spi_driver vsc7385_driver = {
596 .driver = {
597 .name = DRV_NAME,
598 .bus = &spi_bus_type,
599 .owner = THIS_MODULE,
600 },
601 .probe = vsc7385_probe,
602 .remove = __devexit_p(vsc7385_remove),
603 };
604
605 static int __init vsc7385_init(void)
606 {
607 return spi_register_driver(&vsc7385_driver);
608 }
609 module_init(vsc7385_init);
610
611 static void __exit vsc7385_exit(void)
612 {
613 spi_unregister_driver(&vsc7385_driver);
614 }
615 module_exit(vsc7385_exit);
616
617 MODULE_DESCRIPTION(DRV_DESC);
618 MODULE_VERSION(DRV_VERSION);
619 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
620 MODULE_LICENSE("GPL v2");
621
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