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c8a08eb926d0635746200bc0a2c7099e2857c092
[openwrt.git] / target / linux / brcm-2.6 / patches / 003-bcm4710_cache_fixes.patch
1 diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kernel/genex.S
2 --- linux-2.6.17/arch/mips/kernel/genex.S 2006-06-18 03:49:35.000000000 +0200
3 +++ linux-2.6.17-owrt/arch/mips/kernel/genex.S 2006-06-18 15:36:58.000000000 +0200
4 @@ -73,6 +73,10 @@
5 .set push
6 .set mips3
7 .set noat
8 +#ifdef CONFIG_BCM4710
9 + nop
10 + nop
11 +#endif
12 mfc0 k1, CP0_CAUSE
13 li k0, 31<<2
14 andi k1, k1, 0x7c
15 diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k.c
16 --- linux-2.6.17/arch/mips/mm/c-r4k.c 2006-06-18 03:49:35.000000000 +0200
17 +++ linux-2.6.17-owrt/arch/mips/mm/c-r4k.c 2006-06-18 15:36:58.000000000 +0200
18 @@ -14,6 +14,12 @@
19 #include <linux/mm.h>
20 #include <linux/bitops.h>
21
22 +#ifdef CONFIG_BCM4710
23 +#include "../bcm947xx/include/typedefs.h"
24 +#include "../bcm947xx/include/sbconfig.h"
25 +#include <asm/paccess.h>
26 +#endif
27 +
28 #include <asm/bcache.h>
29 #include <asm/bootinfo.h>
30 #include <asm/cache.h>
31 @@ -30,6 +36,9 @@
32 #include <asm/cacheflush.h> /* for run_uncached() */
33
34
35 +/* For enabling BCM4710 cache workarounds */
36 +int bcm4710 = 0;
37 +
38 /*
39 * Special Variant of smp_call_function for use by cache functions:
40 *
41 @@ -94,7 +103,9 @@
42 {
43 unsigned long dc_lsize = cpu_dcache_line_size();
44
45 - if (dc_lsize == 16)
46 + if (bcm4710)
47 + r4k_blast_dcache_page = blast_dcache_page;
48 + else if (dc_lsize == 16)
49 r4k_blast_dcache_page = blast_dcache16_page;
50 else if (dc_lsize == 32)
51 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
52 @@ -106,7 +117,9 @@
53 {
54 unsigned long dc_lsize = cpu_dcache_line_size();
55
56 - if (dc_lsize == 16)
57 + if (bcm4710)
58 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
59 + else if (dc_lsize == 16)
60 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
61 else if (dc_lsize == 32)
62 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
63 @@ -118,7 +131,9 @@
64 {
65 unsigned long dc_lsize = cpu_dcache_line_size();
66
67 - if (dc_lsize == 16)
68 + if (bcm4710)
69 + r4k_blast_dcache = blast_dcache;
70 + else if (dc_lsize == 16)
71 r4k_blast_dcache = blast_dcache16;
72 else if (dc_lsize == 32)
73 r4k_blast_dcache = blast_dcache32;
74 @@ -683,6 +698,8 @@
75 unsigned long addr = (unsigned long) arg;
76
77 R4600_HIT_CACHEOP_WAR_IMPL;
78 + BCM4710_PROTECTED_FILL_TLB(addr);
79 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
80 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
81 if (!cpu_icache_snoops_remote_store && scache_size)
82 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
83 @@ -1189,6 +1206,16 @@
84 static inline void coherency_setup(void)
85 {
86 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
87 +#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
88 + if (BCM330X(current_cpu_data.processor_id)) {
89 + __u32 cm = read_c0_diag();
90 + /* Enable icache */
91 + cm |= (1 << 31);
92 + /* Enable dcache */
93 + cm |= (1 << 30);
94 + write_c0_diag(cm);
95 + }
96 +#endif
97
98 /*
99 * c0_status.cu=0 specifies that updates by the sc instruction use
100 @@ -1227,6 +1254,15 @@
101
102 /* Default cache error handler for R4000 and R5000 family */
103 set_uncached_handler (0x100, &except_vec2_generic, 0x80);
104 +
105 + /* Check if special workarounds are required */
106 +#ifdef CONFIG_BCM4710
107 + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
108 + printk("Enabling BCM4710A0 cache workarounds.\n");
109 + bcm4710 = 1;
110 + } else
111 +#endif
112 + bcm4710 = 0;
113
114 probe_pcache();
115 setup_scache();
116 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
117 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 15:34:19.000000000 +0200
118 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 15:36:58.000000000 +0200
119 @@ -38,6 +38,10 @@
120
121 /* #define DEBUG_TLB */
122
123 +#ifdef CONFIG_BCM4710
124 +extern int bcm4710;
125 +#endif
126 +
127 static __init int __attribute__((unused)) r45k_bvahwbug(void)
128 {
129 /* XXX: We should probe for the presence of this bug, but we don't. */
130 @@ -1184,6 +1188,12 @@
131 memset(relocs, 0, sizeof(relocs));
132 memset(final_handler, 0, sizeof(final_handler));
133
134 +#ifdef CONFIG_BCM4710
135 + if (bcm4710) {
136 + i_nop(&p);
137 + }
138 +#endif
139 +
140 /*
141 * create the plain linear handler
142 */
143 diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm-mips/r4kcache.h
144 --- linux-2.6.17/include/asm-mips/r4kcache.h 2006-06-18 03:49:35.000000000 +0200
145 +++ linux-2.6.17-owrt/include/asm-mips/r4kcache.h 2006-06-18 15:56:57.000000000 +0200
146 @@ -17,6 +17,18 @@
147 #include <asm/cpu-features.h>
148 #include <asm/mipsmtregs.h>
149
150 +#ifdef CONFIG_BCM4710
151 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
152 +
153 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
154 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
155 +#else
156 +#define BCM4710_DUMMY_RREG()
157 +
158 +#define BCM4710_FILL_TLB(addr)
159 +#define BCM4710_PROTECTED_FILL_TLB(addr)
160 +#endif
161 +
162 /*
163 * This macro return a properly sign-extended address suitable as base address
164 * for indexed cache operations. Two issues here:
165 @@ -150,6 +162,7 @@
166 static inline void flush_dcache_line_indexed(unsigned long addr)
167 {
168 __dflush_prologue
169 + BCM4710_DUMMY_RREG();
170 cache_op(Index_Writeback_Inv_D, addr);
171 __dflush_epilogue
172 }
173 @@ -169,6 +182,7 @@
174 static inline void flush_dcache_line(unsigned long addr)
175 {
176 __dflush_prologue
177 + BCM4710_DUMMY_RREG();
178 cache_op(Hit_Writeback_Inv_D, addr);
179 __dflush_epilogue
180 }
181 @@ -176,6 +190,7 @@
182 static inline void invalidate_dcache_line(unsigned long addr)
183 {
184 __dflush_prologue
185 + BCM4710_DUMMY_RREG();
186 cache_op(Hit_Invalidate_D, addr);
187 __dflush_epilogue
188 }
189 @@ -208,6 +223,7 @@
190 */
191 static inline void protected_flush_icache_line(unsigned long addr)
192 {
193 + BCM4710_DUMMY_RREG();
194 protected_cache_op(Hit_Invalidate_I, addr);
195 }
196
197 @@ -219,6 +235,7 @@
198 */
199 static inline void protected_writeback_dcache_line(unsigned long addr)
200 {
201 + BCM4710_DUMMY_RREG();
202 protected_cache_op(Hit_Writeback_Inv_D, addr);
203 }
204
205 @@ -339,8 +356,52 @@
206 : "r" (base), \
207 "i" (op));
208
209 +static inline void blast_dcache(void)
210 +{
211 + unsigned long start = KSEG0;
212 + unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
213 + unsigned long end = (start + dcache_size);
214 +
215 + do {
216 + BCM4710_DUMMY_RREG();
217 + cache_op(Index_Writeback_Inv_D, start);
218 + start += current_cpu_data.dcache.linesz;
219 + } while(start < end);
220 +}
221 +
222 +static inline void blast_dcache_page(unsigned long page)
223 +{
224 + unsigned long start = page;
225 + unsigned long end = start + PAGE_SIZE;
226 +
227 + BCM4710_FILL_TLB(start);
228 + do {
229 + BCM4710_DUMMY_RREG();
230 + cache_op(Hit_Writeback_Inv_D, start);
231 + start += current_cpu_data.dcache.linesz;
232 + } while(start < end);
233 +}
234 +
235 +static inline void blast_dcache_page_indexed(unsigned long page)
236 +{
237 + unsigned long start = page;
238 + unsigned long end = start + PAGE_SIZE;
239 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
240 + unsigned long ws_end = current_cpu_data.dcache.ways <<
241 + current_cpu_data.dcache.waybit;
242 + unsigned long ws, addr;
243 + for (ws = 0; ws < ws_end; ws += ws_inc) {
244 + start = page + ws;
245 + for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
246 + BCM4710_DUMMY_RREG();
247 + cache_op(Index_Writeback_Inv_D, addr);
248 + }
249 + }
250 +}
251 +
252 +
253 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
254 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
255 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
256 static inline void blast_##pfx##cache##lsize(void) \
257 { \
258 unsigned long start = INDEX_BASE; \
259 @@ -352,6 +413,7 @@
260 \
261 __##pfx##flush_prologue \
262 \
263 + war \
264 for (ws = 0; ws < ws_end; ws += ws_inc) \
265 for (addr = start; addr < end; addr += lsize * 32) \
266 cache##lsize##_unroll32(addr|ws,indexop); \
267 @@ -366,6 +428,7 @@
268 \
269 __##pfx##flush_prologue \
270 \
271 + war \
272 do { \
273 cache##lsize##_unroll32(start,hitop); \
274 start += lsize * 32; \
275 @@ -384,6 +447,8 @@
276 current_cpu_data.desc.waybit; \
277 unsigned long ws, addr; \
278 \
279 + war \
280 + \
281 __##pfx##flush_prologue \
282 \
283 for (ws = 0; ws < ws_end; ws += ws_inc) \
284 @@ -393,24 +458,25 @@
285 __##pfx##flush_epilogue \
286 }
287
288 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
289 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
290 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
291 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
292 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
293 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
294 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
295 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
296 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
297 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
298 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
299 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
300 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
301 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
302 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
303 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
304 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
305 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
306
307 /* build blast_xxx_range, protected_blast_xxx_range */
308 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
309 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \
310 static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
311 unsigned long end) \
312 { \
313 unsigned long lsize = cpu_##desc##_line_size(); \
314 unsigned long addr = start & ~(lsize - 1); \
315 unsigned long aend = (end - 1) & ~(lsize - 1); \
316 + war \
317 \
318 __##pfx##flush_prologue \
319 \
320 @@ -424,13 +490,13 @@
321 __##pfx##flush_epilogue \
322 }
323
324 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
325 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
326 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
327 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
328 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
329 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);)
330 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
331 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
332 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);)
333 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
334 /* blast_inv_dcache_range */
335 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
336 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
337 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
338 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
339
340 #endif /* _ASM_R4KCACHE_H */
341 diff -Nur linux-2.6.17/include/asm-mips/stackframe.h linux-2.6.17-owrt/include/asm-mips/stackframe.h
342 --- linux-2.6.17/include/asm-mips/stackframe.h 2006-06-18 03:49:35.000000000 +0200
343 +++ linux-2.6.17-owrt/include/asm-mips/stackframe.h 2006-06-18 15:36:58.000000000 +0200
344 @@ -361,6 +361,10 @@
345 .macro RESTORE_SP_AND_RET
346 LONG_L sp, PT_R29(sp)
347 .set mips3
348 +#ifdef CONFIG_BCM4710
349 + nop
350 + nop
351 +#endif
352 eret
353 .set mips0
354 .endm
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