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fix pci init for brcm-2.4 with atheros wifi cards
[openwrt.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / include / sbchipc.h
1 /*
2 * SiliconBackplane Chipcommon core hardware definitions.
3 *
4 * The chipcommon core provides chip identification, SB control,
5 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6 * gpio interface, extbus, and support for serial and parallel flashes.
7 *
8 * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
9 * Copyright 2006, Broadcom Corporation
10 * All Rights Reserved.
11 *
12 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16 *
17 */
18
19 #ifndef _SBCHIPC_H
20 #define _SBCHIPC_H
21
22
23 #ifndef _LANGUAGE_ASSEMBLY
24
25 /* cpp contortions to concatenate w/arg prescan */
26 #ifndef PAD
27 #define _PADLINE(line) pad ## line
28 #define _XSTR(line) _PADLINE(line)
29 #define PAD _XSTR(__LINE__)
30 #endif /* PAD */
31
32 typedef volatile struct {
33 uint32 chipid; /* 0x0 */
34 uint32 capabilities;
35 uint32 corecontrol; /* corerev >= 1 */
36 uint32 bist;
37
38 /* OTP */
39 uint32 otpstatus; /* 0x10, corerev >= 10 */
40 uint32 otpcontrol;
41 uint32 otpprog;
42 uint32 PAD;
43
44 /* Interrupt control */
45 uint32 intstatus; /* 0x20 */
46 uint32 intmask;
47 uint32 chipcontrol; /* 0x28, rev >= 11 */
48 uint32 chipstatus; /* 0x2c, rev >= 11 */
49
50 /* Jtag Master */
51 uint32 jtagcmd; /* 0x30, rev >= 10 */
52 uint32 jtagir;
53 uint32 jtagdr;
54 uint32 jtagctrl;
55
56 /* serial flash interface registers */
57 uint32 flashcontrol; /* 0x40 */
58 uint32 flashaddress;
59 uint32 flashdata;
60 uint32 PAD[1];
61
62 /* Silicon backplane configuration broadcast control */
63 uint32 broadcastaddress; /* 0x50 */
64 uint32 broadcastdata;
65 uint32 PAD[2];
66
67 /* gpio - cleared only by power-on-reset */
68 uint32 gpioin; /* 0x60 */
69 uint32 gpioout;
70 uint32 gpioouten;
71 uint32 gpiocontrol;
72 uint32 gpiointpolarity;
73 uint32 gpiointmask;
74 uint32 PAD[2];
75
76 /* Watchdog timer */
77 uint32 watchdog; /* 0x80 */
78 uint32 PAD[1];
79
80 /* GPIO based LED powersave registers corerev >= 16 */
81 uint32 gpiotimerval; /* 0x88 */
82 uint32 gpiotimeroutmask;
83
84 /* clock control */
85 uint32 clockcontrol_n; /* 0x90 */
86 uint32 clockcontrol_sb; /* aka m0 */
87 uint32 clockcontrol_pci; /* aka m1 */
88 uint32 clockcontrol_m2; /* mii/uart/mipsref */
89 uint32 clockcontrol_m3; /* cpu */
90 uint32 clkdiv; /* corerev >= 3 */
91 uint32 PAD[2];
92
93 /* pll delay registers (corerev >= 4) */
94 uint32 pll_on_delay; /* 0xb0 */
95 uint32 fref_sel_delay;
96 uint32 slow_clk_ctl; /* 5 < corerev < 10 */
97 uint32 PAD[1];
98
99 /* Instaclock registers (corerev >= 10) */
100 uint32 system_clk_ctl; /* 0xc0 */
101 uint32 clkstatestretch;
102 uint32 PAD[14];
103
104 /* ExtBus control registers (corerev >= 3) */
105 uint32 pcmcia_config; /* 0x100 */
106 uint32 pcmcia_memwait;
107 uint32 pcmcia_attrwait;
108 uint32 pcmcia_iowait;
109 uint32 ide_config;
110 uint32 ide_memwait;
111 uint32 ide_attrwait;
112 uint32 ide_iowait;
113 uint32 prog_config;
114 uint32 prog_waitcount;
115 uint32 flash_config;
116 uint32 flash_waitcount;
117 uint32 PAD[44];
118
119 /* Clock control and hardware workarounds */
120 uint32 clk_ctl_st;
121 uint32 hw_war;
122 uint32 PAD[70];
123
124 /* uarts */
125 uint8 uart0data; /* 0x300 */
126 uint8 uart0imr;
127 uint8 uart0fcr;
128 uint8 uart0lcr;
129 uint8 uart0mcr;
130 uint8 uart0lsr;
131 uint8 uart0msr;
132 uint8 uart0scratch;
133 uint8 PAD[248]; /* corerev >= 1 */
134
135 uint8 uart1data; /* 0x400 */
136 uint8 uart1imr;
137 uint8 uart1fcr;
138 uint8 uart1lcr;
139 uint8 uart1mcr;
140 uint8 uart1lsr;
141 uint8 uart1msr;
142 uint8 uart1scratch;
143 } chipcregs_t;
144
145 #endif /* _LANGUAGE_ASSEMBLY */
146
147 #define CC_CHIPID 0
148 #define CC_CAPABILITIES 4
149 #define CC_JTAGCMD 0x30
150 #define CC_JTAGIR 0x34
151 #define CC_JTAGDR 0x38
152 #define CC_JTAGCTRL 0x3c
153 #define CC_WATCHDOG 0x80
154 #define CC_CLKC_N 0x90
155 #define CC_CLKC_M0 0x94
156 #define CC_CLKC_M1 0x98
157 #define CC_CLKC_M2 0x9c
158 #define CC_CLKC_M3 0xa0
159 #define CC_CLKDIV 0xa4
160 #define CC_SYS_CLK_CTL 0xc0
161 #define CC_OTP 0x800
162
163 /* chipid */
164 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
165 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
166 #define CID_REV_SHIFT 16 /* Chip Revision shift */
167 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
168 #define CID_PKG_SHIFT 20 /* Package Option shift */
169 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
170 #define CID_CC_SHIFT 24
171
172 /* capabilities */
173 #define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
174 #define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
175 #define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
176 #define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
177 #define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
178 #define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
179 #define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
180 #define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
181 #define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
182 #define CAP_FLASH_MASK 0x00000700 /* Type of flash */
183 #define CAP_PLL_MASK 0x00038000 /* Type of PLL */
184 #define CAP_PWR_CTL 0x00040000 /* Power control */
185 #define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
186 #define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
187 #define CAP_OTPSIZE_BASE 5 /* OTP Size base */
188 #define CAP_JTAGP 0x00400000 /* JTAG Master Present */
189 #define CAP_ROM 0x00800000 /* Internal boot rom active */
190 #define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
191
192 /* PLL type */
193 #define PLL_NONE 0x00000000
194 #define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
195 #define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
196 #define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
197 #define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
198 #define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
199 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
200 #define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
201
202 /* corecontrol */
203 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
204 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
205
206 /* chipcontrol */
207 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
208 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
209
210 /* Fields in the otpstatus register */
211 #define OTPS_PROGFAIL 0x80000000
212 #define OTPS_PROTECT 0x00000007
213 #define OTPS_HW_PROTECT 0x00000001
214 #define OTPS_SW_PROTECT 0x00000002
215 #define OTPS_CID_PROTECT 0x00000004
216
217 /* Fields in the otpcontrol register */
218 #define OTPC_RECWAIT 0xff000000
219 #define OTPC_PROGWAIT 0x00ffff00
220 #define OTPC_PRW_SHIFT 8
221 #define OTPC_MAXFAIL 0x00000038
222 #define OTPC_VSEL 0x00000006
223 #define OTPC_SELVL 0x00000001
224
225 /* Fields in otpprog */
226 #define OTPP_COL_MASK 0x000000ff
227 #define OTPP_ROW_MASK 0x0000ff00
228 #define OTPP_ROW_SHIFT 8
229 #define OTPP_READERR 0x10000000
230 #define OTPP_VALUE 0x20000000
231 #define OTPP_VALUE_SHIFT 29
232 #define OTPP_READ 0x40000000
233 #define OTPP_START 0x80000000
234 #define OTPP_BUSY 0x80000000
235
236 /* jtagcmd */
237 #define JCMD_START 0x80000000
238 #define JCMD_BUSY 0x80000000
239 #define JCMD_PAUSE 0x40000000
240 #define JCMD0_ACC_MASK 0x0000f000
241 #define JCMD0_ACC_IRDR 0x00000000
242 #define JCMD0_ACC_DR 0x00001000
243 #define JCMD0_ACC_IR 0x00002000
244 #define JCMD0_ACC_RESET 0x00003000
245 #define JCMD0_ACC_IRPDR 0x00004000
246 #define JCMD0_ACC_PDR 0x00005000
247 #define JCMD0_IRW_MASK 0x00000f00
248 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
249 #define JCMD_ACC_IRDR 0x00000000
250 #define JCMD_ACC_DR 0x00010000
251 #define JCMD_ACC_IR 0x00020000
252 #define JCMD_ACC_RESET 0x00030000
253 #define JCMD_ACC_IRPDR 0x00040000
254 #define JCMD_ACC_PDR 0x00050000
255 #define JCMD_IRW_MASK 0x00001f00
256 #define JCMD_IRW_SHIFT 8
257 #define JCMD_DRW_MASK 0x0000003f
258
259 /* jtagctrl */
260 #define JCTRL_FORCE_CLK 4 /* Force clock */
261 #define JCTRL_EXT_EN 2 /* Enable external targets */
262 #define JCTRL_EN 1 /* Enable Jtag master */
263
264 /* Fields in clkdiv */
265 #define CLKD_SFLASH 0x0f000000
266 #define CLKD_SFLASH_SHIFT 24
267 #define CLKD_OTP 0x000f0000
268 #define CLKD_OTP_SHIFT 16
269 #define CLKD_JTAG 0x00000f00
270 #define CLKD_JTAG_SHIFT 8
271 #define CLKD_UART 0x000000ff
272
273 /* intstatus/intmask */
274 #define CI_GPIO 0x00000001 /* gpio intr */
275 #define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
276 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */
277
278 /* slow_clk_ctl */
279 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
280 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
281 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
282 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
283 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
284 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
285 * 0: LPO is enabled
286 */
287 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
288 * 0: power logic control
289 */
290 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
291 * PLL clock disable requests from core
292 */
293 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
294 * disable crystal when appropriate
295 */
296 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
297 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
298 #define SCC_CD_SHIFT 16
299
300 /* system_clk_ctl */
301 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
302 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
303 #define SYCC_FP 0x00000004 /* ForcePLLOn */
304 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
305 #define SYCC_HR 0x00000010 /* Force HT */
306 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
307 #define SYCC_CD_SHIFT 16
308
309 /* gpiotimerval */
310 #define GPIO_ONTIME_SHIFT 16
311
312 /* clockcontrol_n */
313 #define CN_N1_MASK 0x3f /* n1 control */
314 #define CN_N2_MASK 0x3f00 /* n2 control */
315 #define CN_N2_SHIFT 8
316 #define CN_PLLC_MASK 0xf0000 /* pll control */
317 #define CN_PLLC_SHIFT 16
318
319 /* clockcontrol_sb/pci/uart */
320 #define CC_M1_MASK 0x3f /* m1 control */
321 #define CC_M2_MASK 0x3f00 /* m2 control */
322 #define CC_M2_SHIFT 8
323 #define CC_M3_MASK 0x3f0000 /* m3 control */
324 #define CC_M3_SHIFT 16
325 #define CC_MC_MASK 0x1f000000 /* mux control */
326 #define CC_MC_SHIFT 24
327
328 /* N3M Clock control magic field values */
329 #define CC_F6_2 0x02 /* A factor of 2 in */
330 #define CC_F6_3 0x03 /* 6-bit fields like */
331 #define CC_F6_4 0x05 /* N1, M1 or M3 */
332 #define CC_F6_5 0x09
333 #define CC_F6_6 0x11
334 #define CC_F6_7 0x21
335
336 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
337
338 #define CC_MC_BYPASS 0x08
339 #define CC_MC_M1 0x04
340 #define CC_MC_M1M2 0x02
341 #define CC_MC_M1M2M3 0x01
342 #define CC_MC_M1M3 0x11
343
344 /* Type 2 Clock control magic field values */
345 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
346 #define CC_T2M2_BIAS 3 /* m2 bias */
347
348 #define CC_T2MC_M1BYP 1
349 #define CC_T2MC_M2BYP 2
350 #define CC_T2MC_M3BYP 4
351
352 /* Type 6 Clock control magic field values */
353 #define CC_T6_MMASK 1 /* bits of interest in m */
354 #define CC_T6_M0 120000000 /* sb clock for m = 0 */
355 #define CC_T6_M1 100000000 /* sb clock for m = 1 */
356 #define SB2MIPS_T6(sb) (2 * (sb))
357
358 /* Common clock base */
359 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
360 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
361
362 /* Clock control values for 200Mhz in 5350 */
363 #define CLKC_5350_N 0x0311
364 #define CLKC_5350_M 0x04020009
365
366 /* Flash types in the chipcommon capabilities register */
367 #define FLASH_NONE 0x000 /* No flash */
368 #define SFLASH_ST 0x100 /* ST serial flash */
369 #define SFLASH_AT 0x200 /* Atmel serial flash */
370 #define PFLASH 0x700 /* Parallel flash */
371
372 /* Bits in the ExtBus config registers */
373 #define CC_CFG_EN 0x0001 /* Enable */
374 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */
375 #define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
376 #define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
377 #define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
378 #define CC_CFG_EM_IDE 0x0006 /* IDE */
379 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
380 #define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
381 #define CC_CFG_CE 0x0080 /* Sync: Clock enable */
382 #define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
383
384 /* ExtBus address space */
385 #define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
386 #define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
387 #define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
388 #define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
389 #define CC_EB_IDE 0x1a800000 /* IDE memory base */
390 #define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
391 #define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
392 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
393 #define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
394
395
396 /* Start/busy bit in flashcontrol */
397 #define SFLASH_OPCODE 0x000000ff
398 #define SFLASH_ACTION 0x00000700
399 #define SFLASH_START 0x80000000
400 #define SFLASH_BUSY SFLASH_START
401
402 /* flashcontrol action codes */
403 #define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
404 #define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
405 #define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
406 #define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
407 #define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
408 #define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
409 #define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
410
411 /* flashcontrol action+opcodes for ST flashes */
412 #define SFLASH_ST_WREN 0x0006 /* Write Enable */
413 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
414 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
415 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
416 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
417 #define SFLASH_ST_PP 0x0302 /* Page Program */
418 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */
419 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
420 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
421 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
422
423 /* Status register bits for ST flashes */
424 #define SFLASH_ST_WIP 0x01 /* Write In Progress */
425 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
426 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
427 #define SFLASH_ST_BP_SHIFT 2
428 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
429
430 /* flashcontrol action+opcodes for Atmel flashes */
431 #define SFLASH_AT_READ 0x07e8
432 #define SFLASH_AT_PAGE_READ 0x07d2
433 #define SFLASH_AT_BUF1_READ
434 #define SFLASH_AT_BUF2_READ
435 #define SFLASH_AT_STATUS 0x01d7
436 #define SFLASH_AT_BUF1_WRITE 0x0384
437 #define SFLASH_AT_BUF2_WRITE 0x0387
438 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
439 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
440 #define SFLASH_AT_BUF1_PROGRAM 0x0288
441 #define SFLASH_AT_BUF2_PROGRAM 0x0289
442 #define SFLASH_AT_PAGE_ERASE 0x0281
443 #define SFLASH_AT_BLOCK_ERASE 0x0250
444 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
445 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
446 #define SFLASH_AT_BUF1_LOAD 0x0253
447 #define SFLASH_AT_BUF2_LOAD 0x0255
448 #define SFLASH_AT_BUF1_COMPARE 0x0260
449 #define SFLASH_AT_BUF2_COMPARE 0x0261
450 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
451 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
452
453 /* Status register bits for Atmel flashes */
454 #define SFLASH_AT_READY 0x80
455 #define SFLASH_AT_MISMATCH 0x40
456 #define SFLASH_AT_ID_MASK 0x38
457 #define SFLASH_AT_ID_SHIFT 3
458
459 /* OTP regions */
460 #define OTP_HW_REGION OTPS_HW_PROTECT
461 #define OTP_SW_REGION OTPS_SW_PROTECT
462 #define OTP_CID_REGION OTPS_CID_PROTECT
463
464 /* OTP regions (Byte offsets from otp size) */
465 #define OTP_SWLIM_OFF (-8)
466 #define OTP_CIDBASE_OFF 0
467 #define OTP_CIDLIM_OFF 8
468
469 /* Predefined OTP words (Word offset from otp size) */
470 #define OTP_BOUNDARY_OFF (-4)
471 #define OTP_HWSIGN_OFF (-3)
472 #define OTP_SWSIGN_OFF (-2)
473 #define OTP_CIDSIGN_OFF (-1)
474
475 #define OTP_CID_OFF 0
476 #define OTP_PKG_OFF 1
477 #define OTP_FID_OFF 2
478 #define OTP_RSV_OFF 3
479 #define OTP_LIM_OFF 4
480
481 #define OTP_SIGNATURE 0x578a
482 #define OTP_MAGIC 0x4e56
483
484 /*
485 * These are the UART port assignments, expressed as offsets from the base
486 * register. These assignments should hold for any serial port based on
487 * a 8250, 16450, or 16550(A).
488 */
489
490 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */
491 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
492 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
493 #define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
494 #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
495 #define UART_IIR 2 /* In: Interrupt Identity Register */
496 #define UART_FCR 2 /* Out: FIFO Control Register */
497 #define UART_LCR 3 /* Out: Line Control Register */
498 #define UART_MCR 4 /* Out: Modem Control Register */
499 #define UART_LSR 5 /* In: Line Status Register */
500 #define UART_MSR 6 /* In: Modem Status Register */
501 #define UART_SCR 7 /* I/O: Scratch Register */
502 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
503 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
504 #define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
505 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
506 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
507 #define UART_LSR_RXRDY 0x01 /* Receiver ready */
508 #define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
509
510 /* Interrupt Enable Register (IER) bits */
511 #define UART_IER_EDSSI 8 /* enable modem status interrupt */
512 #define UART_IER_ELSI 4 /* enable receiver line status interrupt */
513 #define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
514 #define UART_IER_ERBFI 1 /* enable data available interrupt */
515
516 #endif /* _SBCHIPC_H */
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