target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
   3  *
   4  * Copyright 2006, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
  13  */
  14
  15 #ifndef _SBSDRAM_H
  16 #define _SBSDRAM_H
  17
  18 #ifndef _LANGUAGE_ASSEMBLY
  19
  20 /* Sonics side: SDRAM core registers */
  21 typedef volatile struct sbsdramregs {
  22         uint32  initcontrol;    /* Generates external SDRAM initialization sequence */
  23         uint32  config;         /* Initializes external SDRAM mode register */
  24         uint32  refresh;        /* Controls external SDRAM refresh rate */
  25         uint32  pad1;
  26         uint32  pad2;
  27 } sbsdramregs_t;
  28
  29 /* SDRAM simulation */
  30 #ifdef RAMSZ
  31 #define SDRAMSZ         RAMSZ
  32 #else
  33 #define SDRAMSZ         (4 * 1024 * 1024)
  34 #endif
  35
  36 extern uchar sdrambuf[SDRAMSZ];
  37
  38 #endif /* _LANGUAGE_ASSEMBLY */
  39
  40 /* SDRAM initialization control (initcontrol) register bits */
  41 #define SDRAM_CBR       0x0001  /* Writing 1 generates refresh cycle and toggles bit */
  42 #define SDRAM_PRE       0x0002  /* Writing 1 generates precharge cycle and toggles bit */
  43 #define SDRAM_MRS       0x0004  /* Writing 1 generates mode register select cycle and toggles bit */
  44 #define SDRAM_EN        0x0008  /* When set, enables access to SDRAM */
  45 #define SDRAM_16Mb      0x0000  /* Use 16 Megabit SDRAM */
  46 #define SDRAM_64Mb      0x0010  /* Use 64 Megabit SDRAM */
  47 #define SDRAM_128Mb     0x0020  /* Use 128 Megabit SDRAM */
  48 #define SDRAM_RSVMb     0x0030  /* Use special SDRAM */
  49 #define SDRAM_RST       0x0080  /* Writing 1 causes soft reset of controller */
  50 #define SDRAM_SELFREF   0x0100  /* Writing 1 enables self refresh mode */
  51 #define SDRAM_PWRDOWN   0x0200  /* Writing 1 causes controller to power down */
  52 #define SDRAM_32BIT     0x0400  /* When set, indicates 32 bit SDRAM interface */
  53 #define SDRAM_9BITCOL   0x0800  /* When set, indicates 9 bit column */
  54
  55 /* SDRAM configuration (config) register bits */
  56 #define SDRAM_BURSTFULL 0x0000  /* Use full page bursts */
  57 #define SDRAM_BURST8    0x0001  /* Use burst of 8 */
  58 #define SDRAM_BURST4    0x0002  /* Use burst of 4 */
  59 #define SDRAM_BURST2    0x0003  /* Use burst of 2 */
  60 #define SDRAM_CAS3      0x0000  /* Use CAS latency of 3 */
  61 #define SDRAM_CAS2      0x0004  /* Use CAS latency of 2 */
  62
  63 /* SDRAM refresh control (refresh) register bits */
  64 #define SDRAM_REF(p)    (((p)&0xff) | SDRAM_REF_EN)     /* Refresh period */
  65 #define SDRAM_REF_EN    0x8000          /* Writing 1 enables periodic refresh */
  66
  67 /* SDRAM Core default Init values (OCP ID 0x803) */
  68 #define SDRAM_INIT      MEM4MX16X2
  69 #define SDRAM_CONFIG    SDRAM_BURSTFULL
  70 #define SDRAM_REFRESH   SDRAM_REF(0x40)
  71
  72 #define MEM1MX16        0x009   /* 2 MB */
  73 #define MEM1MX16X2      0x409   /* 4 MB */
  74 #define MEM2MX8X2       0x809   /* 4 MB */
  75 #define MEM2MX8X4       0xc09   /* 8 MB */
  76 #define MEM2MX32        0x439   /* 8 MB */
  77 #define MEM4MX16        0x019   /* 8 MB */
  78 #define MEM4MX16X2      0x419   /* 16 MB */
  79 #define MEM8MX8X2       0x819   /* 16 MB */
  80 #define MEM8MX16        0x829   /* 16 MB */
  81 #define MEM4MX32        0x429   /* 16 MB */
  82 #define MEM8MX8X4       0xc19   /* 32 MB */
  83 #define MEM8MX16X2      0xc29   /* 32 MB */
  84
  85 #endif  /* _SBSDRAM_H */