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[ar71xx] ag71xx driver: fix RX_STATUS_OF bitmask, and add DMA status register bit...
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
98 &ring->descs_dma,
99 GFP_ATOMIC);
100 if (!ring->descs) {
101 err = -ENOMEM;
102 goto err;
103 }
104
105 ring->size = size;
106
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
108 if (!ring->buf) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 return 0;
114
115 err:
116 return err;
117 }
118
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
120 {
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
123
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
126
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
130 }
131
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
134
135 ring->buf[i].skb = NULL;
136
137 ring->dirty++;
138 }
139
140 /* flush descriptors */
141 wmb();
142
143 }
144
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
146 {
147 struct ag71xx_ring *ring = &ag->tx_ring;
148 int i;
149
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
153
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
156 }
157
158 /* flush descriptors */
159 wmb();
160
161 ring->curr = 0;
162 ring->dirty = 0;
163 }
164
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
166 {
167 struct ag71xx_ring *ring = &ag->rx_ring;
168 int i;
169
170 if (!ring->buf)
171 return;
172
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
176
177 }
178
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 unsigned int i;
183 int ret;
184
185 ret = 0;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
189
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
191 struct sk_buff *skb;
192
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
194 if (!skb) {
195 ret = -ENOMEM;
196 break;
197 }
198
199 skb->dev = ag->dev;
200 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
201
202 ring->buf[i].skb = skb;
203 ring->descs[i].data = virt_to_phys(skb->data);
204 ring->descs[i].ctrl = DESC_EMPTY;
205 }
206
207 /* flush descriptors */
208 wmb();
209
210 ring->curr = 0;
211 ring->dirty = 0;
212
213 return ret;
214 }
215
216 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
217 {
218 struct ag71xx_ring *ring = &ag->rx_ring;
219 unsigned int count;
220
221 count = 0;
222 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
223 unsigned int i;
224
225 i = ring->dirty % AG71XX_RX_RING_SIZE;
226
227 if (ring->buf[i].skb == NULL) {
228 struct sk_buff *skb;
229
230 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
231 if (skb == NULL) {
232 printk(KERN_ERR "%s: no memory for skb\n",
233 ag->dev->name);
234 break;
235 }
236
237 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
238 skb->dev = ag->dev;
239 ring->buf[i].skb = skb;
240 ring->descs[i].data = virt_to_phys(skb->data);
241 }
242
243 ring->descs[i].ctrl = DESC_EMPTY;
244 count++;
245 }
246
247 /* flush descriptors */
248 wmb();
249
250 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
251
252 return count;
253 }
254
255 static int ag71xx_rings_init(struct ag71xx *ag)
256 {
257 int ret;
258
259 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
260 if (ret)
261 return ret;
262
263 ag71xx_ring_tx_init(ag);
264
265 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
266 if (ret)
267 return ret;
268
269 ret = ag71xx_ring_rx_init(ag);
270 return ret;
271 }
272
273 static void ag71xx_rings_cleanup(struct ag71xx *ag)
274 {
275 ag71xx_ring_rx_clean(ag);
276 ag71xx_ring_free(&ag->rx_ring);
277
278 ag71xx_ring_tx_clean(ag);
279 ag71xx_ring_free(&ag->tx_ring);
280 }
281
282 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
283 {
284 u32 t;
285
286 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
287 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
288
289 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
290
291 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
292 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
293 }
294
295 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
296 MAC_CFG1_SRX | MAC_CFG1_STX)
297 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
298
299 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
300 MAC_CFG1_SRX | MAC_CFG1_STX | \
301 MAC_CFG1_TFC | MAC_CFG1_RFC)
302 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
303
304 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
305
306 static void ag71xx_dma_reset(struct ag71xx *ag)
307 {
308 int i;
309
310 ag71xx_dump_dma_regs(ag);
311
312 /* stop RX and TX */
313 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
314 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
315
316 /* clear descriptor addresses */
317 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
318 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
319
320 /* clear pending RX/TX interrupts */
321 for (i = 0; i < 256; i++) {
322 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
323 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
324 }
325
326 /* clear pending errors */
327 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
328 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
329
330 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
331 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
332 ag->dev->name);
333
334 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
335 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
336 ag->dev->name);
337
338 ag71xx_dump_dma_regs(ag);
339 }
340
341 static void ag71xx_hw_init(struct ag71xx *ag)
342 {
343 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
344
345 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
346 udelay(20);
347
348 ar71xx_device_stop(pdata->reset_bit);
349 mdelay(100);
350 ar71xx_device_start(pdata->reset_bit);
351 mdelay(100);
352
353 /* setup MAC configuration registers */
354 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
355 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
356 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
357 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
358
359 /* setup max frame length */
360 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
361
362 /* setup MII interface type */
363 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
364
365 /* setup FIFO configuration registers */
366 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
367 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
368 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
369 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
370 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
371 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
372 : AR71XX_FIFO_CFG5_INIT);
373
374 ag71xx_dma_reset(ag);
375 }
376
377 static void ag71xx_hw_start(struct ag71xx *ag)
378 {
379 /* start RX engine */
380 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
381
382 /* enable interrupts */
383 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
384 }
385
386 static void ag71xx_hw_stop(struct ag71xx *ag)
387 {
388 /* disable all interrupts */
389 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
390
391 ag71xx_dma_reset(ag);
392 }
393
394 static int ag71xx_open(struct net_device *dev)
395 {
396 struct ag71xx *ag = netdev_priv(dev);
397 int ret;
398
399 ret = ag71xx_rings_init(ag);
400 if (ret)
401 goto err;
402
403 napi_enable(&ag->napi);
404
405 netif_carrier_off(dev);
406 ag71xx_phy_start(ag);
407
408 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
409 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
410
411 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
412
413 ag71xx_hw_start(ag);
414
415 netif_start_queue(dev);
416
417 return 0;
418
419 err:
420 ag71xx_rings_cleanup(ag);
421 return ret;
422 }
423
424 static int ag71xx_stop(struct net_device *dev)
425 {
426 struct ag71xx *ag = netdev_priv(dev);
427 unsigned long flags;
428
429 spin_lock_irqsave(&ag->lock, flags);
430
431 netif_stop_queue(dev);
432
433 ag71xx_hw_stop(ag);
434
435 netif_carrier_off(dev);
436 ag71xx_phy_stop(ag);
437
438 napi_disable(&ag->napi);
439
440 spin_unlock_irqrestore(&ag->lock, flags);
441
442 ag71xx_rings_cleanup(ag);
443
444 return 0;
445 }
446
447 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
448 {
449 struct ag71xx *ag = netdev_priv(dev);
450 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
451 struct ag71xx_ring *ring = &ag->tx_ring;
452 struct ag71xx_desc *desc;
453 unsigned long flags;
454 int i;
455
456 i = ring->curr % AG71XX_TX_RING_SIZE;
457 desc = &ring->descs[i];
458
459 spin_lock_irqsave(&ag->lock, flags);
460 pdata->ddr_flush();
461 spin_unlock_irqrestore(&ag->lock, flags);
462
463 if (!ag71xx_desc_empty(desc))
464 goto err_drop;
465
466 if (skb->len <= 0) {
467 DBG("%s: packet len is too small\n", ag->dev->name);
468 goto err_drop;
469 }
470
471 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
472
473 ring->buf[i].skb = skb;
474
475 /* setup descriptor fields */
476 desc->data = virt_to_phys(skb->data);
477 desc->ctrl = (skb->len & DESC_PKTLEN_M);
478
479 /* flush descriptor */
480 wmb();
481
482 ring->curr++;
483 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
484 DBG("%s: tx queue full\n", ag->dev->name);
485 netif_stop_queue(dev);
486 }
487
488 DBG("%s: packet injected into TX queue\n", ag->dev->name);
489
490 /* enable TX engine */
491 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
492
493 dev->trans_start = jiffies;
494
495 return 0;
496
497 err_drop:
498 dev->stats.tx_dropped++;
499
500 dev_kfree_skb(skb);
501 return 0;
502 }
503
504 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
505 {
506 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
507 struct ag71xx *ag = netdev_priv(dev);
508 int ret;
509
510 switch (cmd) {
511 case SIOCETHTOOL:
512 if (ag->phy_dev == NULL)
513 break;
514
515 spin_lock_irq(&ag->lock);
516 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
517 spin_unlock_irq(&ag->lock);
518 return ret;
519
520 case SIOCSIFHWADDR:
521 if (copy_from_user
522 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
523 return -EFAULT;
524 return 0;
525
526 case SIOCGIFHWADDR:
527 if (copy_to_user
528 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
529 return -EFAULT;
530 return 0;
531
532 case SIOCGMIIPHY:
533 case SIOCGMIIREG:
534 case SIOCSMIIREG:
535 if (ag->phy_dev == NULL)
536 break;
537
538 return phy_mii_ioctl(ag->phy_dev, data, cmd);
539
540 default:
541 break;
542 }
543
544 return -EOPNOTSUPP;
545 }
546
547 static void ag71xx_tx_packets(struct ag71xx *ag)
548 {
549 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
550 struct ag71xx_ring *ring = &ag->tx_ring;
551 unsigned int sent;
552
553 DBG("%s: processing TX ring\n", ag->dev->name);
554
555 #ifdef AG71XX_NAPI_TX
556 pdata->ddr_flush();
557 #endif
558
559 sent = 0;
560 while (ring->dirty != ring->curr) {
561 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
562 struct ag71xx_desc *desc = &ring->descs[i];
563 struct sk_buff *skb = ring->buf[i].skb;
564
565 if (!ag71xx_desc_empty(desc))
566 break;
567
568 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
569
570 ag->dev->stats.tx_bytes += skb->len;
571 ag->dev->stats.tx_packets++;
572
573 dev_kfree_skb_any(skb);
574 ring->buf[i].skb = NULL;
575
576 ring->dirty++;
577 sent++;
578 }
579
580 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
581
582 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
583 netif_wake_queue(ag->dev);
584
585 }
586
587 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
588 {
589 struct net_device *dev = ag->dev;
590 struct ag71xx_ring *ring = &ag->rx_ring;
591 #ifndef AG71XX_NAPI_TX
592 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
593 unsigned long flags;
594 #endif
595 int done = 0;
596
597 #ifndef AG71XX_NAPI_TX
598 spin_lock_irqsave(&ag->lock, flags);
599 pdata->ddr_flush();
600 spin_unlock_irqrestore(&ag->lock, flags);
601 #endif
602
603 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
604 dev->name, limit, ring->curr, ring->dirty);
605
606 while (done < limit) {
607 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
608 struct ag71xx_desc *desc = &ring->descs[i];
609 struct sk_buff *skb;
610 int pktlen;
611
612 if (ag71xx_desc_empty(desc))
613 break;
614
615 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
616 ag71xx_assert(0);
617 break;
618 }
619
620 skb = ring->buf[i].skb;
621 pktlen = ag71xx_desc_pktlen(desc);
622 pktlen -= ETH_FCS_LEN;
623
624 /* TODO: move it into the refill function */
625 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
626 skb_put(skb, pktlen);
627
628 skb->dev = dev;
629 skb->protocol = eth_type_trans(skb, dev);
630 skb->ip_summed = CHECKSUM_UNNECESSARY;
631
632 netif_receive_skb(skb);
633
634 dev->last_rx = jiffies;
635 dev->stats.rx_packets++;
636 dev->stats.rx_bytes += pktlen;
637
638 ring->buf[i].skb = NULL;
639 done++;
640
641 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
642
643 ring->curr++;
644 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
645 ag71xx_ring_rx_refill(ag);
646 }
647
648 ag71xx_ring_rx_refill(ag);
649
650 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
651 dev->name, ring->curr, ring->dirty, done);
652
653 return done;
654 }
655
656 static int ag71xx_poll(struct napi_struct *napi, int limit)
657 {
658 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
659 #ifdef AG71XX_NAPI_TX
660 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
661 #endif
662 struct net_device *dev = ag->dev;
663 unsigned long flags;
664 u32 status;
665 int done;
666
667 #ifdef AG71XX_NAPI_TX
668 pdata->ddr_flush();
669 ag71xx_tx_packets(ag);
670 #endif
671
672 DBG("%s: processing RX ring\n", dev->name);
673 done = ag71xx_rx_packets(ag, limit);
674
675 /* TODO: add OOM handler */
676
677 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
678 status &= AG71XX_INT_POLL;
679
680 if ((done < limit) && (!status)) {
681 DBG("%s: disable polling mode, done=%d, status=%x\n",
682 dev->name, done, status);
683
684 netif_rx_complete(dev, napi);
685
686 /* enable interrupts */
687 spin_lock_irqsave(&ag->lock, flags);
688 ag71xx_int_enable(ag, AG71XX_INT_POLL);
689 spin_unlock_irqrestore(&ag->lock, flags);
690 return 0;
691 }
692
693 if (status & AG71XX_INT_RX_OF) {
694 if (netif_msg_rx_err(ag))
695 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
696 dev->name);
697
698 /* ack interrupt */
699 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
700 /* restart RX */
701 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
702 }
703
704 DBG("%s: stay in polling mode, done=%d, status=%x\n",
705 dev->name, done, status);
706 return 1;
707 }
708
709 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
710 {
711 struct net_device *dev = dev_id;
712 struct ag71xx *ag = netdev_priv(dev);
713 u32 status;
714
715 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
716 ag71xx_dump_intr(ag, "raw", status);
717 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
718 ag71xx_dump_intr(ag, "masked", status);
719
720 if (unlikely(!status))
721 return IRQ_NONE;
722
723 if (unlikely(status & AG71XX_INT_ERR)) {
724 if (status & AG71XX_INT_TX_BE) {
725 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
726 dev_err(&dev->dev, "TX BUS error\n");
727 }
728 if (status & AG71XX_INT_RX_BE) {
729 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
730 dev_err(&dev->dev, "RX BUS error\n");
731 }
732 }
733
734 #if 0
735 if (unlikely(status & AG71XX_INT_TX_UR)) {
736 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
737 DBG("%s: TX underrun\n", dev->name);
738 }
739 #endif
740
741 #ifndef AG71XX_NAPI_TX
742 if (likely(status & AG71XX_INT_TX_PS))
743 ag71xx_tx_packets(ag);
744 #endif
745
746 if (likely(status & AG71XX_INT_POLL)) {
747 ag71xx_int_disable(ag, AG71XX_INT_POLL);
748 DBG("%s: enable polling mode\n", dev->name);
749 netif_rx_schedule(dev, &ag->napi);
750 }
751
752 return IRQ_HANDLED;
753 }
754
755 static void ag71xx_set_multicast_list(struct net_device *dev)
756 {
757 /* TODO */
758 }
759
760 static int __init ag71xx_probe(struct platform_device *pdev)
761 {
762 struct net_device *dev;
763 struct resource *res;
764 struct ag71xx *ag;
765 struct ag71xx_platform_data *pdata;
766 int err;
767
768 pdata = pdev->dev.platform_data;
769 if (!pdata) {
770 dev_err(&pdev->dev, "no platform data specified\n");
771 err = -ENXIO;
772 goto err_out;
773 }
774
775 dev = alloc_etherdev(sizeof(*ag));
776 if (!dev) {
777 dev_err(&pdev->dev, "alloc_etherdev failed\n");
778 err = -ENOMEM;
779 goto err_out;
780 }
781
782 SET_NETDEV_DEV(dev, &pdev->dev);
783
784 ag = netdev_priv(dev);
785 ag->pdev = pdev;
786 ag->dev = dev;
787 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
788 ag->msg_enable = netif_msg_init(ag71xx_debug,
789 AG71XX_DEFAULT_MSG_ENABLE);
790 spin_lock_init(&ag->lock);
791
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
793 if (!res) {
794 dev_err(&pdev->dev, "no mac_base resource found\n");
795 err = -ENXIO;
796 goto err_out;
797 }
798
799 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
800 if (!ag->mac_base) {
801 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
802 err = -ENOMEM;
803 goto err_free_dev;
804 }
805
806 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
807 if (!res) {
808 dev_err(&pdev->dev, "no mac_base2 resource found\n");
809 err = -ENXIO;
810 goto err_unmap_base1;
811 }
812
813 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
814 if (!ag->mac_base) {
815 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
816 err = -ENOMEM;
817 goto err_unmap_base1;
818 }
819
820 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
821 if (!res) {
822 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
823 err = -ENXIO;
824 goto err_unmap_base2;
825 }
826
827 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
828 if (!ag->mii_ctrl) {
829 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
830 err = -ENOMEM;
831 goto err_unmap_base2;
832 }
833
834 dev->irq = platform_get_irq(pdev, 0);
835 err = request_irq(dev->irq, ag71xx_interrupt,
836 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
837 dev->name, dev);
838 if (err) {
839 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
840 goto err_unmap_mii_ctrl;
841 }
842
843 dev->base_addr = (unsigned long)ag->mac_base;
844 dev->open = ag71xx_open;
845 dev->stop = ag71xx_stop;
846 dev->hard_start_xmit = ag71xx_hard_start_xmit;
847 dev->set_multicast_list = ag71xx_set_multicast_list;
848 dev->do_ioctl = ag71xx_do_ioctl;
849 dev->ethtool_ops = &ag71xx_ethtool_ops;
850
851 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
852
853 if (is_valid_ether_addr(pdata->mac_addr))
854 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
855 else {
856 dev->dev_addr[0] = 0xde;
857 dev->dev_addr[1] = 0xad;
858 get_random_bytes(&dev->dev_addr[2], 3);
859 dev->dev_addr[5] = pdev->id & 0xff;
860 }
861
862 err = register_netdev(dev);
863 if (err) {
864 dev_err(&pdev->dev, "unable to register net device\n");
865 goto err_free_irq;
866 }
867
868 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
869 dev->name, dev->base_addr, dev->irq);
870
871 ag71xx_dump_regs(ag);
872
873 ag71xx_hw_init(ag);
874
875 ag71xx_dump_regs(ag);
876
877 /* Reset the mdio bus explicitly */
878 if (ag->mii_bus) {
879 mutex_lock(&ag->mii_bus->mdio_lock);
880 ag->mii_bus->reset(ag->mii_bus);
881 mutex_unlock(&ag->mii_bus->mdio_lock);
882 }
883
884 err = ag71xx_phy_connect(ag);
885 if (err)
886 goto err_unregister_netdev;
887
888 platform_set_drvdata(pdev, dev);
889
890 return 0;
891
892 err_unregister_netdev:
893 unregister_netdev(dev);
894 err_free_irq:
895 free_irq(dev->irq, dev);
896 err_unmap_mii_ctrl:
897 iounmap(ag->mii_ctrl);
898 err_unmap_base2:
899 iounmap(ag->mac_base2);
900 err_unmap_base1:
901 iounmap(ag->mac_base);
902 err_free_dev:
903 kfree(dev);
904 err_out:
905 platform_set_drvdata(pdev, NULL);
906 return err;
907 }
908
909 static int __exit ag71xx_remove(struct platform_device *pdev)
910 {
911 struct net_device *dev = platform_get_drvdata(pdev);
912
913 if (dev) {
914 struct ag71xx *ag = netdev_priv(dev);
915
916 ag71xx_phy_disconnect(ag);
917 unregister_netdev(dev);
918 free_irq(dev->irq, dev);
919 iounmap(ag->mii_ctrl);
920 iounmap(ag->mac_base2);
921 iounmap(ag->mac_base);
922 kfree(dev);
923 platform_set_drvdata(pdev, NULL);
924 }
925
926 return 0;
927 }
928
929 static struct platform_driver ag71xx_driver = {
930 .probe = ag71xx_probe,
931 .remove = __exit_p(ag71xx_remove),
932 .driver = {
933 .name = AG71XX_DRV_NAME,
934 }
935 };
936
937 static int __init ag71xx_module_init(void)
938 {
939 int ret;
940
941 ret = ag71xx_mdio_driver_init();
942 if (ret)
943 goto err_out;
944
945 ret = platform_driver_register(&ag71xx_driver);
946 if (ret)
947 goto err_mdio_exit;
948
949 return 0;
950
951 err_mdio_exit:
952 ag71xx_mdio_driver_exit();
953 err_out:
954 return ret;
955 }
956
957 static void __exit ag71xx_module_exit(void)
958 {
959 platform_driver_unregister(&ag71xx_driver);
960 ag71xx_mdio_driver_exit();
961 }
962
963 module_init(ag71xx_module_init);
964 module_exit(ag71xx_module_exit);
965
966 MODULE_VERSION(AG71XX_DRV_VERSION);
967 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
968 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
969 MODULE_LICENSE("GPL v2");
970 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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