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ar71xx: disable DDR flush for ethernet on AR934x, it is no longer necessary
[openwrt.git] / target / linux / brcm63xx / patches-3.1 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_UART1] = BCM_6358_UART1_IRQ,
26 [IRQ_DSL] = BCM_6358_DSL_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,98 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
37 + */
38 +
39 +#include <linux/init.h>
40 +#include <linux/kernel.h>
41 +#include <linux/platform_device.h>
42 +
43 +#include <bcm63xx_cpu.h>
44 +#include <bcm63xx_dev_spi.h>
45 +#include <bcm63xx_regs.h>
46 +
47 +#ifdef BCMCPU_RUNTIME_DETECT
48 +/*
49 + * register offsets
50 + */
51 +static const unsigned long bcm96338_regs_spi[] = {
52 + __GEN_SPI_REGS_TABLE(6338)
53 +};
54 +
55 +static const unsigned long bcm96348_regs_spi[] = {
56 + __GEN_SPI_REGS_TABLE(6348)
57 +};
58 +
59 +static const unsigned long bcm96358_regs_spi[] = {
60 + __GEN_SPI_REGS_TABLE(6358)
61 +};
62 +
63 +const unsigned long *bcm63xx_regs_spi;
64 +EXPORT_SYMBOL(bcm63xx_regs_spi);
65 +
66 +static __init void bcm63xx_spi_regs_init(void)
67 +{
68 + if (BCMCPU_IS_6338())
69 + bcm63xx_regs_spi = bcm96338_regs_spi;
70 + if (BCMCPU_IS_6348())
71 + bcm63xx_regs_spi = bcm96348_regs_spi;
72 + if (BCMCPU_IS_6358())
73 + bcm63xx_regs_spi = bcm96358_regs_spi;
74 +}
75 +#else
76 +static __init void bcm63xx_spi_regs_init(void) { }
77 +#endif
78 +
79 +static struct resource spi_resources[] = {
80 + {
81 + .start = -1, /* filled at runtime */
82 + .end = -1, /* filled at runtime */
83 + .flags = IORESOURCE_MEM,
84 + },
85 + {
86 + .start = -1, /* filled at runtime */
87 + .flags = IORESOURCE_IRQ,
88 + },
89 +};
90 +
91 +static struct bcm63xx_spi_pdata spi_pdata = {
92 + .bus_num = 0,
93 + .num_chipselect = 8,
94 + .speed_hz = 50000000, /* Fclk */
95 +};
96 +
97 +static struct platform_device bcm63xx_spi_device = {
98 + .name = "bcm63xx-spi",
99 + .id = 0,
100 + .num_resources = ARRAY_SIZE(spi_resources),
101 + .resource = spi_resources,
102 + .dev = {
103 + .platform_data = &spi_pdata,
104 + },
105 +};
106 +
107 +int __init bcm63xx_spi_register(void)
108 +{
109 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
110 + spi_resources[0].end = spi_resources[0].start;
111 + spi_resources[0].end += RSET_SPI_SIZE - 1;
112 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
113 +
114 + if (BCMCPU_IS_6345())
115 + return -ENODEV;
116 +
117 + /* Fill in platform data */
118 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
119 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
120 +
121 + if (BCMCPU_IS_6358())
122 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
123 +
124 + bcm63xx_spi_regs_init();
125 +
126 + return platform_device_register(&bcm63xx_spi_device);
127 +}
128 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
129 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
130 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
131 #define RSET_WDT_SIZE 12
132 #define RSET_ENET_SIZE 2048
133 #define RSET_ENETDMA_SIZE 2048
134 +#define RSET_SPI_SIZE 256
135 #define RSET_UART_SIZE 24
136 #define RSET_UDC_SIZE 256
137 #define RSET_OHCI_SIZE 256
138 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
139 #define BCM_6358_UART0_BASE (0xfffe0100)
140 #define BCM_6358_UART1_BASE (0xfffe0120)
141 #define BCM_6358_GPIO_BASE (0xfffe0080)
142 -#define BCM_6358_SPI_BASE (0xdeadbeef)
143 +#define BCM_6358_SPI_BASE (0xfffe0800)
144 #define BCM_6358_UDC0_BASE (0xfffe0400)
145 #define BCM_6358_OHCI0_BASE (0xfffe1400)
146 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
147 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
148 */
149 enum bcm63xx_irq {
150 IRQ_TIMER = 0,
151 + IRQ_SPI,
152 IRQ_UART0,
153 IRQ_UART1,
154 IRQ_DSL,
155 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
156 * 6348 irqs
157 */
158 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
159 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
160 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
161 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
162 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
163 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
164 * 6358 irqs
165 */
166 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
167 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
168 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
169 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
170 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
171 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
172 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
173 @@ -804,4 +804,116 @@
174 #define DMIPSPLLCFG_N2_SHIFT 29
175 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
176
177 +/*************************************************************************
178 + * _REG relative to RSET_SPI
179 + *************************************************************************/
180 +
181 +/* BCM 6338 SPI core */
182 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
183 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
184 +#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03
185 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
186 +#define SPI_BCM_6338_SPI_ST 0x05
187 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
188 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
189 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
190 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
191 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
192 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
193 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
194 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
195 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
196 +
197 +/* BCM 6348 SPI core */
198 +#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
199 +#define SPI_BCM_6348_SPI_INT_STATUS 0x02
200 +#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
201 +#define SPI_BCM_6348_SPI_INT_MASK 0x04
202 +#define SPI_BCM_6348_SPI_ST 0x05
203 +#define SPI_BCM_6348_SPI_CLK_CFG 0x06
204 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
205 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
206 +#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
207 +#define SPI_BCM_6348_SPI_MSG_CTL 0x40
208 +#define SPI_BCM_6348_SPI_MSG_DATA 0x41
209 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
210 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
211 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
212 +
213 +/* BCM 6358 SPI core */
214 +#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */
215 +
216 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
217 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
218 +
219 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
220 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
221 +
222 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
223 +
224 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
225 +#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703
226 +
227 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
228 +
229 +#define SPI_BCM_6358_SPI_ST 0x705
230 +
231 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
232 +
233 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
234 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
235 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
236 +
237 +/* Shared SPI definitions */
238 +
239 +/* Message configuration */
240 +#define SPI_FD_RW 0x00
241 +#define SPI_HD_W 0x01
242 +#define SPI_HD_R 0x02
243 +#define SPI_BYTE_CNT_SHIFT 0
244 +#define SPI_MSG_TYPE_SHIFT 14
245 +
246 +/* Command */
247 +#define SPI_CMD_NOOP 0x00
248 +#define SPI_CMD_SOFT_RESET 0x01
249 +#define SPI_CMD_HARD_RESET 0x02
250 +#define SPI_CMD_START_IMMEDIATE 0x03
251 +#define SPI_CMD_COMMAND_SHIFT 0
252 +#define SPI_CMD_COMMAND_MASK 0x000f
253 +#define SPI_CMD_DEVICE_ID_SHIFT 4
254 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
255 +#define SPI_CMD_ONE_BYTE_SHIFT 11
256 +#define SPI_CMD_ONE_WIRE_SHIFT 12
257 +#define SPI_DEV_ID_0 0
258 +#define SPI_DEV_ID_1 1
259 +#define SPI_DEV_ID_2 2
260 +#define SPI_DEV_ID_3 3
261 +
262 +/* Interrupt mask */
263 +#define SPI_INTR_CMD_DONE 0x01
264 +#define SPI_INTR_RX_OVERFLOW 0x02
265 +#define SPI_INTR_TX_UNDERFLOW 0x04
266 +#define SPI_INTR_TX_OVERFLOW 0x08
267 +#define SPI_INTR_RX_UNDERFLOW 0x10
268 +#define SPI_INTR_CLEAR_ALL 0x1f
269 +
270 +/* Status */
271 +#define SPI_RX_EMPTY 0x02
272 +#define SPI_CMD_BUSY 0x04
273 +#define SPI_SERIAL_BUSY 0x08
274 +
275 +/* Clock configuration */
276 +#define SPI_CLK_20MHZ 0x00
277 +#define SPI_CLK_0_391MHZ 0x01
278 +#define SPI_CLK_0_781MHZ 0x02 /* default */
279 +#define SPI_CLK_1_563MHZ 0x03
280 +#define SPI_CLK_3_125MHZ 0x04
281 +#define SPI_CLK_6_250MHZ 0x05
282 +#define SPI_CLK_12_50MHZ 0x06
283 +#define SPI_CLK_25MHZ 0x07
284 +#define SPI_CLK_MASK 0x07
285 +#define SPI_SSOFFTIME_MASK 0x38
286 +#define SPI_SSOFFTIME_SHIFT 3
287 +#define SPI_BYTE_SWAP 0x80
288 +
289 #endif /* BCM63XX_REGS_H_ */
290 --- /dev/null
291 +++ b/drivers/spi/bcm63xx_spi.c
292 @@ -0,0 +1,496 @@
293 +/*
294 + * Broadcom BCM63xx SPI controller support
295 + *
296 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
297 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
298 + *
299 + * This program is free software; you can redistribute it and/or
300 + * modify it under the terms of the GNU General Public License
301 + * as published by the Free Software Foundation; either version 2
302 + * of the License, or (at your option) any later version.
303 + *
304 + * This program is distributed in the hope that it will be useful,
305 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
306 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
307 + * GNU General Public License for more details.
308 + *
309 + * You should have received a copy of the GNU General Public License
310 + * along with this program; if not, write to the
311 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
312 + */
313 +
314 +#include <linux/kernel.h>
315 +#include <linux/init.h>
316 +#include <linux/clk.h>
317 +#include <linux/module.h>
318 +#include <linux/platform_device.h>
319 +#include <linux/delay.h>
320 +#include <linux/interrupt.h>
321 +#include <linux/spi/spi.h>
322 +#include <linux/completion.h>
323 +#include <linux/err.h>
324 +
325 +#include <bcm63xx_dev_spi.h>
326 +
327 +#define PFX KBUILD_MODNAME
328 +#define DRV_VER "0.1.2"
329 +
330 +struct bcm63xx_spi {
331 + spinlock_t lock;
332 + int stopping;
333 + struct completion done;
334 +
335 + void __iomem *regs;
336 + int irq;
337 +
338 + /* Platform data */
339 + u32 speed_hz;
340 + unsigned fifo_size;
341 +
342 + /* Data buffers */
343 + const unsigned char *tx_ptr;
344 + unsigned char *rx_ptr;
345 +
346 + /* data iomem */
347 + u8 __iomem *tx_io;
348 + const u8 __iomem *rx_io;
349 +
350 + int remaining_bytes;
351 +
352 + struct clk *clk;
353 + struct platform_device *pdev;
354 +};
355 +
356 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
357 + unsigned int offset)
358 +{
359 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
360 +}
361 +
362 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
363 + unsigned int offset)
364 +{
365 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
366 +}
367 +
368 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
369 + u8 value, unsigned int offset)
370 +{
371 + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
372 +}
373 +
374 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
375 + u16 value, unsigned int offset)
376 +{
377 + bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
378 +}
379 +
380 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
381 + struct spi_transfer *t)
382 +{
383 + u8 bits_per_word;
384 + u8 clk_cfg;
385 + u32 hz;
386 + unsigned int div;
387 +
388 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
389 +
390 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
391 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
392 + if (bits_per_word != 8) {
393 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
394 + __func__, bits_per_word);
395 + return -EINVAL;
396 + }
397 +
398 + if (spi->chip_select > spi->master->num_chipselect) {
399 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
400 + __func__, spi->chip_select);
401 + return -EINVAL;
402 + }
403 +
404 + /* Check clock setting */
405 + div = (bs->speed_hz / hz);
406 + switch (div) {
407 + case 2:
408 + clk_cfg = SPI_CLK_25MHZ;
409 + break;
410 + case 4:
411 + clk_cfg = SPI_CLK_12_50MHZ;
412 + break;
413 + case 8:
414 + clk_cfg = SPI_CLK_6_250MHZ;
415 + break;
416 + case 16:
417 + clk_cfg = SPI_CLK_3_125MHZ;
418 + break;
419 + case 32:
420 + clk_cfg = SPI_CLK_1_563MHZ;
421 + break;
422 + case 64:
423 + clk_cfg = SPI_CLK_0_781MHZ;
424 + break;
425 + case 128:
426 + default:
427 + /* Set to slowest mode for compatibility */
428 + clk_cfg = SPI_CLK_0_391MHZ;
429 + break;
430 + }
431 +
432 + bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
433 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
434 + div, hz, clk_cfg);
435 +
436 + return 0;
437 +}
438 +
439 +/* the spi->mode bits understood by this driver: */
440 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
441 +
442 +static int bcm63xx_spi_setup(struct spi_device *spi)
443 +{
444 + struct bcm63xx_spi *bs;
445 + int ret;
446 +
447 + bs = spi_master_get_devdata(spi->master);
448 +
449 + if (bs->stopping)
450 + return -ESHUTDOWN;
451 +
452 + if (!spi->bits_per_word)
453 + spi->bits_per_word = 8;
454 +
455 + if (spi->mode & ~MODEBITS) {
456 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
457 + __func__, spi->mode & ~MODEBITS);
458 + return -EINVAL;
459 + }
460 +
461 + ret = bcm63xx_spi_setup_transfer(spi, NULL);
462 + if (ret < 0) {
463 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
464 + spi->mode & ~MODEBITS);
465 + return ret;
466 + }
467 +
468 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
469 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
470 +
471 + return 0;
472 +}
473 +
474 +/* Fill the TX FIFO with as many bytes as possible */
475 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
476 +{
477 + u8 size;
478 +
479 + /* Fill the Tx FIFO with as many bytes as possible */
480 + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
481 + bs->fifo_size;
482 + memcpy_toio(bs->tx_io, bs->tx_ptr, size);
483 + bs->remaining_bytes -= size;
484 +}
485 +
486 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
487 +{
488 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
489 + u16 msg_ctl;
490 + u16 cmd;
491 +
492 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
493 + t->tx_buf, t->rx_buf, t->len);
494 +
495 + /* Transmitter is inhibited */
496 + bs->tx_ptr = t->tx_buf;
497 + bs->rx_ptr = t->rx_buf;
498 + init_completion(&bs->done);
499 +
500 + if (t->tx_buf) {
501 + bs->remaining_bytes = t->len;
502 + bcm63xx_spi_fill_tx_fifo(bs);
503 + }
504 +
505 + /* Enable the command done interrupt which
506 + * we use to determine completion of a command */
507 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
508 +
509 + /* Fill in the Message control register */
510 + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
511 +
512 + if (t->rx_buf && t->tx_buf)
513 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
514 + else if (t->rx_buf)
515 + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
516 + else if (t->tx_buf)
517 + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
518 +
519 + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
520 +
521 + /* Issue the transfer */
522 + cmd = SPI_CMD_START_IMMEDIATE;
523 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
524 + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
525 + bcm_spi_writew(bs, cmd, SPI_CMD);
526 + wait_for_completion(&bs->done);
527 +
528 + /* Disable the CMD_DONE interrupt */
529 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
530 +
531 + return t->len - bs->remaining_bytes;
532 +}
533 +
534 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
535 +{
536 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
537 + struct spi_transfer *t;
538 + int ret = 0;
539 +
540 + if (unlikely(list_empty(&m->transfers)))
541 + return -EINVAL;
542 +
543 + if (bs->stopping)
544 + return -ESHUTDOWN;
545 +
546 + list_for_each_entry(t, &m->transfers, transfer_list) {
547 + ret += bcm63xx_txrx_bufs(spi, t);
548 + }
549 +
550 + m->complete(m->context);
551 +
552 + return ret;
553 +}
554 +
555 +/* This driver supports single master mode only. Hence
556 + * CMD_DONE is the only interrupt we care about
557 + */
558 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
559 +{
560 + struct spi_master *master = (struct spi_master *)dev_id;
561 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
562 + u8 intr;
563 + u16 cmd;
564 +
565 + /* Read interupts and clear them immediately */
566 + intr = bcm_spi_readb(bs, SPI_INT_STATUS);
567 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
568 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
569 +
570 + /* A tansfer completed */
571 + if (intr & SPI_INTR_CMD_DONE) {
572 + u8 rx_tail;
573 +
574 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
575 +
576 + /* Read out all the data */
577 + if (rx_tail)
578 + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
579 +
580 + /* See if there is more data to send */
581 + if (bs->remaining_bytes > 0) {
582 + bcm63xx_spi_fill_tx_fifo(bs);
583 +
584 + /* Start the transfer */
585 + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
586 + SPI_MSG_CTL);
587 + cmd = bcm_spi_readw(bs, SPI_CMD);
588 + cmd |= SPI_CMD_START_IMMEDIATE;
589 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
590 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
591 + bcm_spi_writew(bs, cmd, SPI_CMD);
592 + } else {
593 + complete(&bs->done);
594 + }
595 + }
596 +
597 + return IRQ_HANDLED;
598 +}
599 +
600 +
601 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
602 +{
603 + struct resource *r;
604 + struct device *dev = &pdev->dev;
605 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
606 + int irq;
607 + struct spi_master *master;
608 + struct clk *clk;
609 + struct bcm63xx_spi *bs;
610 + int ret;
611 +
612 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
613 + if (!r) {
614 + dev_err(dev, "no iomem\n");
615 + ret = -ENXIO;
616 + goto out;
617 + }
618 +
619 + irq = platform_get_irq(pdev, 0);
620 + if (irq < 0) {
621 + dev_err(dev, "no irq\n");
622 + ret = -ENXIO;
623 + goto out;
624 + }
625 +
626 + clk = clk_get(dev, "spi");
627 + if (IS_ERR(clk)) {
628 + dev_err(dev, "no clock for device\n");
629 + ret = -ENODEV;
630 + goto out;
631 + }
632 +
633 + master = spi_alloc_master(dev, sizeof(*bs));
634 + if (!master) {
635 + dev_err(dev, "out of memory\n");
636 + ret = -ENOMEM;
637 + goto out_free;
638 + }
639 +
640 + bs = spi_master_get_devdata(master);
641 + init_completion(&bs->done);
642 +
643 + platform_set_drvdata(pdev, master);
644 + bs->pdev = pdev;
645 +
646 + if (!request_mem_region(r->start, r->end - r->start, PFX)) {
647 + dev_err(dev, "iomem request failed\n");
648 + ret = -ENXIO;
649 + goto out_put_master;
650 + }
651 +
652 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
653 + if (!bs->regs) {
654 + dev_err(dev, "unable to ioremap regs\n");
655 + ret = -ENOMEM;
656 + goto out_put_master;
657 + }
658 + bs->irq = irq;
659 + bs->clk = clk;
660 + bs->fifo_size = pdata->fifo_size;
661 +
662 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
663 + if (ret) {
664 + dev_err(dev, "unable to request irq\n");
665 + goto out_unmap;
666 + }
667 +
668 + master->bus_num = pdata->bus_num;
669 + master->num_chipselect = pdata->num_chipselect;
670 + master->setup = bcm63xx_spi_setup;
671 + master->transfer = bcm63xx_transfer;
672 + bs->speed_hz = pdata->speed_hz;
673 + bs->stopping = 0;
674 + bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
675 + bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
676 + spin_lock_init(&bs->lock);
677 +
678 + /* Initialize hardware */
679 + clk_enable(bs->clk);
680 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
681 +
682 + /* register and we are done */
683 + ret = spi_register_master(master);
684 + if (ret) {
685 + dev_err(dev, "spi register failed\n");
686 + goto out_reset_hw;
687 + }
688 +
689 + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
690 + r->start, irq, bs->fifo_size, DRV_VER);
691 +
692 + return 0;
693 +
694 +out_reset_hw:
695 + clk_disable(clk);
696 + free_irq(irq, master);
697 +out_unmap:
698 + iounmap(bs->regs);
699 +out_put_master:
700 + spi_master_put(master);
701 +out_free:
702 + clk_put(clk);
703 +out:
704 + return ret;
705 +}
706 +
707 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
708 +{
709 + struct spi_master *master = platform_get_drvdata(pdev);
710 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
711 + struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 +
713 + /* reset spi block */
714 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
715 + spin_lock(&bs->lock);
716 + bs->stopping = 1;
717 +
718 + /* HW shutdown */
719 + clk_disable(bs->clk);
720 + clk_put(bs->clk);
721 +
722 + spin_unlock(&bs->lock);
723 +
724 + free_irq(bs->irq, master);
725 + iounmap(bs->regs);
726 + release_mem_region(r->start, r->end - r->start);
727 + platform_set_drvdata(pdev, 0);
728 + spi_unregister_master(master);
729 +
730 + return 0;
731 +}
732 +
733 +#ifdef CONFIG_PM
734 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
735 +{
736 + struct spi_master *master = platform_get_drvdata(pdev);
737 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
738 +
739 + clk_disable(bs->clk);
740 +
741 + return 0;
742 +}
743 +
744 +static int bcm63xx_spi_resume(struct platform_device *pdev)
745 +{
746 + struct spi_master *master = platform_get_drvdata(pdev);
747 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
748 +
749 + clk_enable(bs->clk);
750 +
751 + return 0;
752 +}
753 +#else
754 +#define bcm63xx_spi_suspend NULL
755 +#define bcm63xx_spi_resume NULL
756 +#endif
757 +
758 +static struct platform_driver bcm63xx_spi_driver = {
759 + .driver = {
760 + .name = "bcm63xx-spi",
761 + .owner = THIS_MODULE,
762 + },
763 + .probe = bcm63xx_spi_probe,
764 + .remove = __exit_p(bcm63xx_spi_remove),
765 + .suspend = bcm63xx_spi_suspend,
766 + .resume = bcm63xx_spi_resume,
767 +};
768 +
769 +
770 +static int __init bcm63xx_spi_init(void)
771 +{
772 + return platform_driver_register(&bcm63xx_spi_driver);
773 +}
774 +
775 +static void __exit bcm63xx_spi_exit(void)
776 +{
777 + platform_driver_unregister(&bcm63xx_spi_driver);
778 +}
779 +
780 +module_init(bcm63xx_spi_init);
781 +module_exit(bcm63xx_spi_exit);
782 +
783 +MODULE_ALIAS("platform:bcm63xx_spi");
784 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
785 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
786 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
787 +MODULE_LICENSE("GPL");
788 +MODULE_VERSION(DRV_VER);
789 --- a/drivers/spi/Kconfig
790 +++ b/drivers/spi/Kconfig
791 @@ -74,6 +74,12 @@ config SPI_ATMEL
792 This selects a driver for the Atmel SPI Controller, present on
793 many AT32 (AVR32) and AT91 (ARM) chips.
794
795 +config SPI_BCM63XX
796 + tristate "Broadcom BCM63xx SPI controller"
797 + depends on BCM63XX
798 + help
799 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
800 +
801 config SPI_BFIN
802 tristate "SPI controller driver for ADI Blackfin5xx"
803 depends on BLACKFIN
804 --- a/drivers/spi/Makefile
805 +++ b/drivers/spi/Makefile
806 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
807 obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
808 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
809 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
810 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
811 obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
812 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
813 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
814 --- /dev/null
815 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
816 @@ -0,0 +1,85 @@
817 +#ifndef BCM63XX_DEV_SPI_H
818 +#define BCM63XX_DEV_SPI_H
819 +
820 +#include <linux/types.h>
821 +#include <bcm63xx_io.h>
822 +#include <bcm63xx_regs.h>
823 +
824 +int __init bcm63xx_spi_register(void);
825 +
826 +struct bcm63xx_spi_pdata {
827 + unsigned int fifo_size;
828 + int bus_num;
829 + int num_chipselect;
830 + u32 speed_hz;
831 +};
832 +
833 +enum bcm63xx_regs_spi {
834 + SPI_CMD,
835 + SPI_INT_STATUS,
836 + SPI_INT_MASK_ST,
837 + SPI_INT_MASK,
838 + SPI_ST,
839 + SPI_CLK_CFG,
840 + SPI_FILL_BYTE,
841 + SPI_MSG_TAIL,
842 + SPI_RX_TAIL,
843 + SPI_MSG_CTL,
844 + SPI_MSG_DATA,
845 + SPI_RX_DATA,
846 +};
847 +
848 +#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
849 + case SPI_## __rset: \
850 + return SPI_BCM_## __cpu ##_SPI_## __rset;
851 +
852 +#define __GEN_SPI_RSET(__cpu) \
853 + switch (reg) { \
854 + __GEN_SPI_RSET_BASE(__cpu, CMD) \
855 + __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
856 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
857 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
858 + __GEN_SPI_RSET_BASE(__cpu, ST) \
859 + __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
860 + __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
861 + __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
862 + __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
863 + __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
864 + __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
865 + __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
866 + }
867 +
868 +#define __GEN_SPI_REGS_TABLE(__cpu) \
869 + [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \
870 + [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \
871 + [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \
872 + [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \
873 + [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \
874 + [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \
875 + [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \
876 + [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \
877 + [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \
878 + [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \
879 + [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \
880 + [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA,
881 +
882 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
883 +{
884 +#ifdef BCMCPU_RUNTIME_DETECT
885 + extern const unsigned long *bcm63xx_regs_spi;
886 + return bcm63xx_regs_spi[reg];
887 +#else
888 +#ifdef CONFIG_BCM63XX_CPU_6338
889 + __GEN_SPI_RSET(6338)
890 +#endif
891 +#ifdef CONFIG_BCM63XX_CPU_6348
892 + __GEN_SPI_RSET(6348)
893 +#endif
894 +#ifdef CONFIG_BCM63XX_CPU_6358
895 + __GEN_SPI_RSET(6358)
896 +#endif
897 +#endif
898 + return 0;
899 +}
900 +
901 +#endif /* BCM63XX_DEV_SPI_H */
902 --- a/arch/mips/bcm63xx/Makefile
903 +++ b/arch/mips/bcm63xx/Makefile
904 @@ -1,6 +1,6 @@
905 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
906 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
907 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
908 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
909 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
910
911 obj-y += boards/
912 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
913 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
914 @@ -30,6 +30,7 @@
915 #include <bcm63xx_dev_usb_ohci.h>
916 #include <bcm63xx_dev_usb_ehci.h>
917 #include <bcm63xx_dev_usb_udc.h>
918 +#include <bcm63xx_dev_spi.h>
919 #include <board_bcm963xx.h>
920
921 #define PFX "board_bcm963xx: "
922 @@ -933,6 +934,8 @@ int __init board_register_devices(void)
923 if (board.num_spis)
924 spi_register_board_info(board.spis, board.num_spis);
925
926 + bcm63xx_spi_register();
927 +
928 /* read base address of boot chip select (0) */
929 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
930 val &= MPI_CSBASE_BASE_MASK;
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