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[openwrt.git] / target / linux / atheros-2.6 / files / arch / mips / atheros / ar5312.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
10 */
11
12 /*
13 * Platform devices for Atheros SoCs
14 */
15
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/platform_device.h>
23 #include <linux/kernel.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
27 #include <asm/time.h>
28 #include <asm/irq.h>
29 #include <asm/io.h>
30 #include "ar531x.h"
31
32 #define NO_PHY 0x1f
33
34 static int is_5312 = 0;
35 static struct platform_device *ar5312_devs[5];
36
37 static struct resource ar5312_eth0_res[] = {
38 {
39 .name = "eth0_membase",
40 .flags = IORESOURCE_MEM,
41 .start = KSEG1ADDR(AR531X_ENET0),
42 .end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
43 },
44 {
45 .name = "eth0_irq",
46 .flags = IORESOURCE_IRQ,
47 .start = AR5312_IRQ_ENET0_INTRS,
48 .end = AR5312_IRQ_ENET0_INTRS,
49 },
50 };
51 static struct ar531x_eth ar5312_eth0_data = {
52 .phy = NO_PHY,
53 .mac = 0,
54 .reset_base = AR531X_RESET,
55 .reset_mac = AR531X_RESET_ENET0,
56 .reset_phy = AR531X_RESET_EPHY0,
57 .phy_base = KSEG1ADDR(AR531X_ENET0),
58 };
59
60 static struct resource ar5312_eth1_res[] = {
61 {
62 .name = "eth1_membase",
63 .flags = IORESOURCE_MEM,
64 .start = KSEG1ADDR(AR531X_ENET1),
65 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
66 },
67 {
68 .name = "eth1_irq",
69 .flags = IORESOURCE_IRQ,
70 .start = AR5312_IRQ_ENET1_INTRS,
71 .end = AR5312_IRQ_ENET1_INTRS,
72 },
73 };
74 static struct ar531x_eth ar5312_eth1_data = {
75 .phy = NO_PHY,
76 .mac = 1,
77 .reset_base = AR531X_RESET,
78 .reset_mac = AR531X_RESET_ENET1,
79 .reset_phy = AR531X_RESET_EPHY1,
80 .phy_base = KSEG1ADDR(AR531X_ENET1),
81 };
82
83 static struct platform_device ar5312_eth[] = {
84 {
85 .id = 0,
86 .name = "ar531x-eth",
87 .dev.platform_data = &ar5312_eth0_data,
88 .resource = ar5312_eth0_res,
89 .num_resources = ARRAY_SIZE(ar5312_eth0_res)
90 },
91 {
92 .id = 1,
93 .name = "ar531x-eth",
94 .dev.platform_data = &ar5312_eth1_data,
95 .resource = ar5312_eth1_res,
96 .num_resources = ARRAY_SIZE(ar5312_eth1_res)
97 },
98 };
99
100
101 /*
102 * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
103 * of ENET1. Atheros calls it 'twisted' for a reason :)
104 */
105 static struct resource ar231x_eth0_res[] = {
106 {
107 .name = "eth0_membase",
108 .flags = IORESOURCE_MEM,
109 .start = KSEG1ADDR(AR531X_ENET1),
110 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
111 },
112 {
113 .name = "eth0_irq",
114 .flags = IORESOURCE_IRQ,
115 .start = AR5312_IRQ_ENET1_INTRS,
116 .end = AR5312_IRQ_ENET1_INTRS,
117 },
118 };
119 static struct ar531x_eth ar231x_eth0_data = {
120 .phy = 1,
121 .mac = 1,
122 .reset_base = AR531X_RESET,
123 .reset_mac = AR531X_RESET_ENET1,
124 .reset_phy = AR531X_RESET_EPHY1,
125 .phy_base = KSEG1ADDR(AR531X_ENET0),
126 };
127 static struct platform_device ar231x_eth0 = {
128 .id = 0,
129 .name = "ar531x-eth",
130 .dev.platform_data = &ar231x_eth0_data,
131 .resource = ar231x_eth0_res,
132 .num_resources = ARRAY_SIZE(ar231x_eth0_res)
133 };
134
135
136 static struct platform_device ar5312_wmac[] = {
137 {
138 .id = 0,
139 .name = "ar531x-wmac",
140 },
141 {
142 .id = 1,
143 .name = "ar531x-wmac",
144 },
145 };
146
147 static struct physmap_flash_data ar5312_flash_data = {
148 .width = 2,
149 };
150
151 static struct resource ar5312_flash_resource = {
152 .start = AR531X_FLASH,
153 .end = AR531X_FLASH + 0x400000 - 1,
154 .flags = IORESOURCE_MEM,
155 };
156
157 static struct platform_device ar5312_physmap_flash = {
158 .name = "physmap-flash",
159 .id = 0,
160 .dev = {
161 .platform_data = &ar5312_flash_data,
162 },
163 .num_resources = 1,
164 .resource = &ar5312_flash_resource,
165 };
166
167
168 /*
169 * NB: This mapping size is larger than the actual flash size,
170 * but this shouldn't be a problem here, because the flash
171 * will simply be mapped multiple times.
172 */
173 static char __init *ar5312_flash_limit(void)
174 {
175 u32 ctl;
176 /*
177 * Configure flash bank 0.
178 * Assume 8M window size. Flash will be aliased if it's smaller
179 */
180 ctl = FLASHCTL_E |
181 FLASHCTL_AC_8M |
182 FLASHCTL_RBLE |
183 (0x01 << FLASHCTL_IDCY_S) |
184 (0x07 << FLASHCTL_WST1_S) |
185 (0x07 << FLASHCTL_WST2_S) |
186 (sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
187
188 sysRegWrite(AR531X_FLASHCTL0, ctl);
189
190 /* Disable other flash banks */
191 sysRegWrite(AR531X_FLASHCTL1,
192 sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
193
194 sysRegWrite(AR531X_FLASHCTL2,
195 sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
196
197 return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
198 }
199
200 static struct ar531x_config __init *init_wmac(int unit)
201 {
202 struct ar531x_config *config;
203
204 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
205 config->board = board_config;
206 config->radio = radio_config;
207 config->unit = unit;
208 config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
209
210 return config;
211 }
212
213 int __init ar5312_init_devices(void)
214 {
215 struct ar531x_boarddata *bcfg;
216 char *radio, *c;
217 int dev = 0;
218
219 if (!is_5312)
220 return 0;
221
222 /* Locate board/radio config data */
223 ar531x_find_config(ar5312_flash_limit());
224 bcfg = (struct ar531x_boarddata *) board_config;
225
226
227 /*
228 * Chip IDs and hardware detection for some Atheros
229 * models are really broken!
230 *
231 * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
232 * as indication for AR2312, which is otherwise
233 * indistinguishable from the real AR5312.
234 */
235 if (radio_config) {
236 radio = radio_config + AR531X_RADIO_MASK_OFF;
237 if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
238 bcfg->config |= BD_ISCASPER;
239 } else
240 radio = NULL;
241
242 /* AR2313 has CPU minor rev. 10 */
243 if ((current_cpu_data.processor_id & 0xff) == 0x0a)
244 mips_machtype = MACH_ATHEROS_AR2313;
245
246 /* AR2312 shares the same Silicon ID as AR5312 */
247 else if (bcfg->config & BD_ISCASPER)
248 mips_machtype = MACH_ATHEROS_AR2312;
249
250 /* Everything else is probably AR5312 or compatible */
251 else
252 mips_machtype = MACH_ATHEROS_AR5312;
253
254 ar5312_eth0_data.board_config = board_config;
255 ar5312_eth1_data.board_config = board_config;
256 ar5312_devs[dev++] = &ar5312_physmap_flash;
257
258 ar5312_eth0_data.macaddr = bcfg->enet0Mac;
259 ar5312_eth1_data.macaddr = bcfg->enet1Mac;
260 if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
261 /* ENET0 and ENET1 have the same mac.
262 * Increment the one from ENET1 */
263 c = bcfg->enet1Mac + 5;
264 while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
265 c--;
266 }
267
268 switch(mips_machtype) {
269 case MACH_ATHEROS_AR5312:
270 ar5312_devs[dev++] = &ar5312_eth[0];
271 ar5312_devs[dev++] = &ar5312_eth[1];
272 break;
273 case MACH_ATHEROS_AR2312:
274 case MACH_ATHEROS_AR2313:
275 ar5312_devs[dev++] = &ar231x_eth0;
276 ar5312_flash_data.width = 1;
277 break;
278 }
279
280 if (radio) {
281 if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
282 ar5312_wmac[0].dev.platform_data = init_wmac(0);
283 ar5312_devs[dev++] = &ar5312_wmac[0];
284 }
285 if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
286 ar5312_wmac[1].dev.platform_data = init_wmac(1);
287 ar5312_devs[dev++] = &ar5312_wmac[1];
288 }
289 }
290
291 return platform_add_devices(ar5312_devs, dev);
292 }
293
294
295 /*
296 * Called when an interrupt is received, this function
297 * determines exactly which interrupt it was, and it
298 * invokes the appropriate handler.
299 *
300 * Implicitly, we also define interrupt priority by
301 * choosing which to dispatch first.
302 */
303 asmlinkage void ar5312_irq_dispatch(void)
304 {
305 int pending = read_c0_status() & read_c0_cause();
306
307 if (pending & CAUSEF_IP2)
308 do_IRQ(AR5312_IRQ_WLAN0_INTRS);
309 else if (pending & CAUSEF_IP3)
310 do_IRQ(AR5312_IRQ_ENET0_INTRS);
311 else if (pending & CAUSEF_IP4)
312 do_IRQ(AR5312_IRQ_ENET1_INTRS);
313 else if (pending & CAUSEF_IP5)
314 do_IRQ(AR5312_IRQ_WLAN1_INTRS);
315 else if (pending & CAUSEF_IP6) {
316 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
317
318 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
319 do_IRQ(AR531X_MISC_IRQ_TIMER);
320 (void)sysRegRead(AR531X_TIMER);
321 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
322 do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
323 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
324 do_IRQ(AR531X_MISC_IRQ_UART0);
325 else if (ar531x_misc_intrs & AR531X_ISR_WD)
326 do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
327 else
328 do_IRQ(AR531X_MISC_IRQ_NONE);
329 } else if (pending & CAUSEF_IP7) {
330 do_IRQ(AR531X_IRQ_CPU_CLOCK);
331 }
332 else
333 do_IRQ(AR531X_IRQ_NONE);
334 }
335
336 static void ar5312_halt(void)
337 {
338 while (1);
339 }
340
341 static void ar5312_power_off(void)
342 {
343 ar5312_halt();
344 }
345
346
347 static void ar5312_restart(char *command)
348 {
349 /* reset the system */
350 for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
351 }
352
353
354 /*
355 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
356 * to determine the predevisor value.
357 */
358 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
359 1,
360 2,
361 4,
362 5
363 };
364
365
366 static unsigned int __init ar5312_cpu_frequency(void)
367 {
368 unsigned int result;
369 unsigned int predivide_mask, predivide_shift;
370 unsigned int multiplier_mask, multiplier_shift;
371 unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
372 unsigned int doubler_mask;
373 unsigned int wisoc_revision;
374
375 /* Trust the bootrom's idea of cpu frequency. */
376 if ((result = sysRegRead(AR5312_SCRATCH)))
377 return result;
378
379 wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
380 if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
381 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
382 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
383 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
384 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
385 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
386 } else { /* AR5312 and AR2312 */
387 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
388 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
389 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
390 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
391 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
392 }
393
394 /*
395 * Clocking is derived from a fixed 40MHz input clock.
396 *
397 * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
398 * sysFreq = cpuFreq / 4 (used for APB clock, serial,
399 * flash, Timer, Watchdog Timer)
400 *
401 * cntFreq = cpuFreq / 2 (use for CPU count/compare)
402 *
403 * So, for example, with a PLL multiplier of 5, we have
404 *
405 * cpuFreq = 200MHz
406 * sysFreq = 50MHz
407 * cntFreq = 100MHz
408 *
409 * We compute the CPU frequency, based on PLL settings.
410 */
411
412 clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
413 preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
414 preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
415 multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
416
417 if (clockCtl1 & doubler_mask) {
418 multiplier = multiplier << 1;
419 }
420 return (40000000 / preDivisor) * multiplier;
421 }
422
423 static inline int ar5312_sys_frequency(void)
424 {
425 return ar5312_cpu_frequency() / 4;
426 }
427
428 static void __init ar5312_time_init(void)
429 {
430 mips_hpt_frequency = ar5312_cpu_frequency() / 2;
431 }
432
433
434 /* Enable the specified AR531X_MISC_IRQ interrupt */
435 static void
436 ar5312_misc_intr_enable(unsigned int irq)
437 {
438 unsigned int imr;
439
440 imr = sysRegRead(AR531X_IMR);
441 imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
442 sysRegWrite(AR531X_IMR, imr);
443 sysRegRead(AR531X_IMR); /* flush write buffer */
444 }
445
446 /* Disable the specified AR531X_MISC_IRQ interrupt */
447 static void
448 ar5312_misc_intr_disable(unsigned int irq)
449 {
450 unsigned int imr;
451
452 imr = sysRegRead(AR531X_IMR);
453 imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
454 sysRegWrite(AR531X_IMR, imr);
455 sysRegRead(AR531X_IMR); /* flush write buffer */
456 }
457
458 /* Turn on the specified AR531X_MISC_IRQ interrupt */
459 static unsigned int
460 ar5312_misc_intr_startup(unsigned int irq)
461 {
462 ar5312_misc_intr_enable(irq);
463 return 0;
464 }
465
466 /* Turn off the specified AR531X_MISC_IRQ interrupt */
467 static void
468 ar5312_misc_intr_shutdown(unsigned int irq)
469 {
470 ar5312_misc_intr_disable(irq);
471 }
472
473 static void
474 ar5312_misc_intr_ack(unsigned int irq)
475 {
476 ar5312_misc_intr_disable(irq);
477 }
478
479 static void
480 ar5312_misc_intr_end(unsigned int irq)
481 {
482 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
483 ar5312_misc_intr_enable(irq);
484 }
485
486 static struct irq_chip ar5312_misc_intr_controller = {
487 .typename = "AR5312 misc",
488 .startup = ar5312_misc_intr_startup,
489 .shutdown = ar5312_misc_intr_shutdown,
490 .enable = ar5312_misc_intr_enable,
491 .disable = ar5312_misc_intr_disable,
492 .ack = ar5312_misc_intr_ack,
493 .end = ar5312_misc_intr_end,
494 };
495
496 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
497 {
498 u32 proc1 = sysRegRead(AR531X_PROC1);
499 u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
500 u32 dma1 = sysRegRead(AR531X_DMA1);
501 u32 dmaAddr = sysRegRead(AR531X_DMAADDR); /* clears error state */
502
503 printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
504 procAddr, proc1, dmaAddr, dma1);
505
506 machine_restart("AHB error"); /* Catastrophic failure */
507 return IRQ_HANDLED;
508 }
509
510
511 static struct irqaction ar5312_ahb_proc_interrupt = {
512 .handler = ar5312_ahb_proc_handler,
513 .flags = SA_INTERRUPT,
514 .name = "ar5312_ahb_proc_interrupt",
515 };
516
517
518 static struct irqaction cascade = {
519 .handler = no_action,
520 .flags = SA_INTERRUPT,
521 .name = "cascade",
522 };
523
524 void __init ar5312_misc_intr_init(int irq_base)
525 {
526 int i;
527
528 for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
529 irq_desc[i].status = IRQ_DISABLED;
530 irq_desc[i].action = NULL;
531 irq_desc[i].depth = 1;
532 irq_desc[i].chip = &ar5312_misc_intr_controller;
533 }
534 setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
535 setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
536 }
537
538 void __init ar5312_prom_init(void)
539 {
540 u32 memsize, memcfg, bank0AC, bank1AC;
541
542 is_5312 = 1;
543
544 /* Detect memory size */
545 memcfg = sysRegRead(AR531X_MEM_CFG1);
546 bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
547 bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
548 memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
549 + (bank1AC ? (1 << (bank1AC+1)) : 0);
550 memsize <<= 20;
551 add_memory_region(0, memsize, BOOT_MEM_RAM);
552
553 /* Initialize it to AR5312 for now. Real detection will be done
554 * in ar5312_init_devices() */
555 mips_machtype = MACH_ATHEROS_AR5312;
556 }
557
558 void __init ar5312_plat_setup(void)
559 {
560 /* Clear any lingering AHB errors */
561 sysRegRead(AR531X_PROCADDR);
562 sysRegRead(AR531X_DMAADDR);
563 sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
564
565 board_time_init = ar5312_time_init;
566
567 _machine_restart = ar5312_restart;
568 _machine_halt = ar5312_halt;
569 pm_power_off = ar5312_power_off;
570
571 serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
572 }
573
574 arch_initcall(ar5312_init_devices);
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