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[openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8366rb.h>
19
20 #include "rtl8366_smi.h"
21
22 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
23 #define RTL8366RB_DRIVER_VER "0.2.2"
24
25 #define RTL8366RB_PHY_NO_MAX 4
26 #define RTL8366RB_PHY_PAGE_MAX 7
27 #define RTL8366RB_PHY_ADDR_MAX 31
28
29 /* Switch Global Configuration register */
30 #define RTL8366RB_SGCR 0x0000
31 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
32 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
33 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
34 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
37 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
39 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
40
41 /* Port Enable Control register */
42 #define RTL8366RB_PECR 0x0001
43
44 /* Switch Security Control registers */
45 #define RTL8366RB_SSCR0 0x0002
46 #define RTL8366RB_SSCR1 0x0003
47 #define RTL8366RB_SSCR2 0x0004
48 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
49
50 #define RTL8366RB_RESET_CTRL_REG 0x0100
51 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
52 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
53
54 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
55 #define RTL8366RB_CHIP_VERSION_MASK 0xf
56 #define RTL8366RB_CHIP_ID_REG 0x0509
57 #define RTL8366RB_CHIP_ID_8366 0x5937
58
59 /* PHY registers control */
60 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
61 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
62
63 #define RTL8366RB_PHY_CTRL_READ 1
64 #define RTL8366RB_PHY_CTRL_WRITE 0
65
66 #define RTL8366RB_PHY_REG_MASK 0x1f
67 #define RTL8366RB_PHY_PAGE_OFFSET 5
68 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
69 #define RTL8366RB_PHY_NO_OFFSET 9
70 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
71
72 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
73
74 /* LED control registers */
75 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
76 #define RTL8366RB_LED_BLINKRATE_BIT 0
77 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
78
79 #define RTL8366RB_LED_CTRL_REG 0x0431
80 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
81 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
82
83 #define RTL8366RB_MIB_COUNT 33
84 #define RTL8366RB_GLOBAL_MIB_COUNT 1
85 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
86 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
87 #define RTL8366RB_MIB_CTRL_REG 0x13F0
88 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
89 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
90 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
91 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
92 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
93
94 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
95 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
96 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
97 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
98 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
99
100
101 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
102 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
103
104
105 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
106 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
107 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
108
109 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
110
111
112 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
113 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
114 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
115 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
116 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
117 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
118 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
119
120
121 #define RTL8366RB_PORT_NUM_CPU 5
122 #define RTL8366RB_NUM_PORTS 6
123 #define RTL8366RB_NUM_VLANS 16
124 #define RTL8366RB_NUM_LEDGROUPS 4
125 #define RTL8366RB_NUM_VIDS 4096
126 #define RTL8366RB_PRIORITYMAX 7
127 #define RTL8366RB_FIDMAX 7
128
129
130 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
131 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
132 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
133 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
134 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
135
136 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
137
138 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
139 RTL8366RB_PORT_2 | \
140 RTL8366RB_PORT_3 | \
141 RTL8366RB_PORT_4 | \
142 RTL8366RB_PORT_5 | \
143 RTL8366RB_PORT_CPU)
144
145 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
146 RTL8366RB_PORT_2 | \
147 RTL8366RB_PORT_3 | \
148 RTL8366RB_PORT_4 | \
149 RTL8366RB_PORT_5)
150
151 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
152 RTL8366RB_PORT_2 | \
153 RTL8366RB_PORT_3 | \
154 RTL8366RB_PORT_4)
155
156 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
157
158 #define RTL8366RB_VLAN_VID_MASK 0xfff
159 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
160 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
161 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
162 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
163 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
164 #define RTL8366RB_VLAN_FID_MASK 0x7
165
166 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
167 { 0, 0, 4, "IfInOctets" },
168 { 0, 4, 4, "EtherStatsOctets" },
169 { 0, 8, 2, "EtherStatsUnderSizePkts" },
170 { 0, 10, 2, "EtherFragments" },
171 { 0, 12, 2, "EtherStatsPkts64Octets" },
172 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
173 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
174 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
175 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
176 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
177 { 0, 24, 2, "EtherOversizeStats" },
178 { 0, 26, 2, "EtherStatsJabbers" },
179 { 0, 28, 2, "IfInUcastPkts" },
180 { 0, 30, 2, "EtherStatsMulticastPkts" },
181 { 0, 32, 2, "EtherStatsBroadcastPkts" },
182 { 0, 34, 2, "EtherStatsDropEvents" },
183 { 0, 36, 2, "Dot3StatsFCSErrors" },
184 { 0, 38, 2, "Dot3StatsSymbolErrors" },
185 { 0, 40, 2, "Dot3InPauseFrames" },
186 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
187 { 0, 44, 4, "IfOutOctets" },
188 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
189 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
190 { 0, 52, 2, "Dot3sDeferredTransmissions" },
191 { 0, 54, 2, "Dot3StatsLateCollisions" },
192 { 0, 56, 2, "EtherStatsCollisions" },
193 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
194 { 0, 60, 2, "Dot3OutPauseFrames" },
195 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
196 { 0, 64, 2, "Dot1dTpPortInDiscards" },
197 { 0, 66, 2, "IfOutUcastPkts" },
198 { 0, 68, 2, "IfOutMulticastPkts" },
199 { 0, 70, 2, "IfOutBroadcastPkts" },
200 };
201
202 #define REG_WR(_smi, _reg, _val) \
203 do { \
204 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
205 if (err) \
206 return err; \
207 } while (0)
208
209 #define REG_RMW(_smi, _reg, _mask, _val) \
210 do { \
211 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
212 if (err) \
213 return err; \
214 } while (0)
215
216 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
217 {
218 int timeout = 10;
219 u32 data;
220
221 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
222 RTL8366RB_CHIP_CTRL_RESET_HW);
223 do {
224 msleep(1);
225 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
226 return -EIO;
227
228 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
229 break;
230 } while (--timeout);
231
232 if (!timeout) {
233 printk("Timeout waiting for the switch to reset\n");
234 return -EIO;
235 }
236
237 return 0;
238 }
239
240 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
241 {
242 int err;
243
244 /* set maximum packet length to 1536 bytes */
245 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
246 RTL8366RB_SGCR_MAX_LENGTH_1536);
247
248 /* enable all ports */
249 REG_WR(smi, RTL8366RB_PECR, 0);
250
251 /* enable learning for all ports */
252 REG_WR(smi, RTL8366RB_SSCR0, 0);
253
254 /* enable auto ageing for all ports */
255 REG_WR(smi, RTL8366RB_SSCR1, 0);
256
257 /*
258 * discard VLAN tagged packets if the port is not a member of
259 * the VLAN with which the packets is associated.
260 */
261 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
262
263 /* don't drop packets whose DA has not been learned */
264 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
265
266 return 0;
267 }
268
269 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
270 u32 phy_no, u32 page, u32 addr, u32 *data)
271 {
272 u32 reg;
273 int ret;
274
275 if (phy_no > RTL8366RB_PHY_NO_MAX)
276 return -EINVAL;
277
278 if (page > RTL8366RB_PHY_PAGE_MAX)
279 return -EINVAL;
280
281 if (addr > RTL8366RB_PHY_ADDR_MAX)
282 return -EINVAL;
283
284 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
285 RTL8366RB_PHY_CTRL_READ);
286 if (ret)
287 return ret;
288
289 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
290 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
291 (addr & RTL8366RB_PHY_REG_MASK);
292
293 ret = rtl8366_smi_write_reg(smi, reg, 0);
294 if (ret)
295 return ret;
296
297 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
298 if (ret)
299 return ret;
300
301 return 0;
302 }
303
304 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
305 u32 phy_no, u32 page, u32 addr, u32 data)
306 {
307 u32 reg;
308 int ret;
309
310 if (phy_no > RTL8366RB_PHY_NO_MAX)
311 return -EINVAL;
312
313 if (page > RTL8366RB_PHY_PAGE_MAX)
314 return -EINVAL;
315
316 if (addr > RTL8366RB_PHY_ADDR_MAX)
317 return -EINVAL;
318
319 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
320 RTL8366RB_PHY_CTRL_WRITE);
321 if (ret)
322 return ret;
323
324 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
325 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
326 (addr & RTL8366RB_PHY_REG_MASK);
327
328 ret = rtl8366_smi_write_reg(smi, reg, data);
329 if (ret)
330 return ret;
331
332 return 0;
333 }
334
335 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
336 int port, unsigned long long *val)
337 {
338 int i;
339 int err;
340 u32 addr, data;
341 u64 mibvalue;
342
343 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
344 return -EINVAL;
345
346 addr = RTL8366RB_MIB_COUNTER_BASE +
347 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
348 rtl8366rb_mib_counters[counter].offset;
349
350 /*
351 * Writing access counter address first
352 * then ASIC will prepare 64bits counter wait for being retrived
353 */
354 data = 0; /* writing data will be discard by ASIC */
355 err = rtl8366_smi_write_reg(smi, addr, data);
356 if (err)
357 return err;
358
359 /* read MIB control register */
360 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
361 if (err)
362 return err;
363
364 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
365 return -EBUSY;
366
367 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
368 return -EIO;
369
370 mibvalue = 0;
371 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
372 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
373 if (err)
374 return err;
375
376 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
377 }
378
379 *val = mibvalue;
380 return 0;
381 }
382
383 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
384 struct rtl8366_vlan_4k *vlan4k)
385 {
386 u32 data[3];
387 int err;
388 int i;
389
390 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
391
392 if (vid >= RTL8366RB_NUM_VIDS)
393 return -EINVAL;
394
395 /* write VID */
396 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
397 vid & RTL8366RB_VLAN_VID_MASK);
398 if (err)
399 return err;
400
401 /* write table access control word */
402 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
403 RTL8366RB_TABLE_VLAN_READ_CTRL);
404 if (err)
405 return err;
406
407 for (i = 0; i < 3; i++) {
408 err = rtl8366_smi_read_reg(smi,
409 RTL8366RB_VLAN_TABLE_READ_BASE + i,
410 &data[i]);
411 if (err)
412 return err;
413 }
414
415 vlan4k->vid = vid;
416 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
417 RTL8366RB_VLAN_UNTAG_MASK;
418 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
419 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
420
421 return 0;
422 }
423
424 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
425 const struct rtl8366_vlan_4k *vlan4k)
426 {
427 u32 data[3];
428 int err;
429 int i;
430
431 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
432 vlan4k->member > RTL8366RB_PORT_ALL ||
433 vlan4k->untag > RTL8366RB_PORT_ALL ||
434 vlan4k->fid > RTL8366RB_FIDMAX)
435 return -EINVAL;
436
437 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
438 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
439 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
440 RTL8366RB_VLAN_UNTAG_SHIFT);
441 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
442
443 for (i = 0; i < 3; i++) {
444 err = rtl8366_smi_write_reg(smi,
445 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
446 data[i]);
447 if (err)
448 return err;
449 }
450
451 /* write table access control word */
452 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
453 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
454
455 return err;
456 }
457
458 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
459 struct rtl8366_vlan_mc *vlanmc)
460 {
461 u32 data[3];
462 int err;
463 int i;
464
465 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
466
467 if (index >= RTL8366RB_NUM_VLANS)
468 return -EINVAL;
469
470 for (i = 0; i < 3; i++) {
471 err = rtl8366_smi_read_reg(smi,
472 RTL8366RB_VLAN_MC_BASE(index) + i,
473 &data[i]);
474 if (err)
475 return err;
476 }
477
478 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
479 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
480 RTL8366RB_VLAN_PRIORITY_MASK;
481 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
482 RTL8366RB_VLAN_UNTAG_MASK;
483 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
484 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
485
486 return 0;
487 }
488
489 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
490 const struct rtl8366_vlan_mc *vlanmc)
491 {
492 u32 data[3];
493 int err;
494 int i;
495
496 if (index >= RTL8366RB_NUM_VLANS ||
497 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
498 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
499 vlanmc->member > RTL8366RB_PORT_ALL ||
500 vlanmc->untag > RTL8366RB_PORT_ALL ||
501 vlanmc->fid > RTL8366RB_FIDMAX)
502 return -EINVAL;
503
504 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
505 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
506 RTL8366RB_VLAN_PRIORITY_SHIFT);
507 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
508 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
509 RTL8366RB_VLAN_UNTAG_SHIFT);
510 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
511
512 for (i = 0; i < 3; i++) {
513 err = rtl8366_smi_write_reg(smi,
514 RTL8366RB_VLAN_MC_BASE(index) + i,
515 data[i]);
516 if (err)
517 return err;
518 }
519
520 return 0;
521 }
522
523 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
524 {
525 u32 data;
526 int err;
527
528 if (port >= RTL8366RB_NUM_PORTS)
529 return -EINVAL;
530
531 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
532 &data);
533 if (err)
534 return err;
535
536 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
537 RTL8366RB_PORT_VLAN_CTRL_MASK;
538
539 return 0;
540
541 }
542
543 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
544 {
545 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
546 return -EINVAL;
547
548 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
549 RTL8366RB_PORT_VLAN_CTRL_MASK <<
550 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
551 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
552 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
553 }
554
555 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
556 {
557 if (vlan == 0 || vlan >= RTL8366RB_NUM_VLANS)
558 return 0;
559
560 return 1;
561 }
562
563 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
564 {
565 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
566 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
567 }
568
569 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
570 {
571 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
572 RTL8366RB_SGCR_EN_VLAN_4KTB,
573 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
574 }
575
576 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
577 const struct switch_attr *attr,
578 struct switch_val *val)
579 {
580 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
581
582 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
583 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
584 }
585
586 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val)
589 {
590 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
591 u32 data;
592
593 if (attr->ofs == 1) {
594 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
595
596 if (data & RTL8366RB_SGCR_EN_VLAN)
597 val->value.i = 1;
598 else
599 val->value.i = 0;
600 } else if (attr->ofs == 2) {
601 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
602
603 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
604 val->value.i = 1;
605 else
606 val->value.i = 0;
607 }
608
609 return 0;
610 }
611
612 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
613 const struct switch_attr *attr,
614 struct switch_val *val)
615 {
616 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
617 u32 data;
618
619 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
620
621 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
622
623 return 0;
624 }
625
626 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val)
629 {
630 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
631
632 if (val->value.i >= 6)
633 return -EINVAL;
634
635 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
636 RTL8366RB_LED_BLINKRATE_MASK,
637 val->value.i);
638 }
639
640 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
641 const struct switch_attr *attr,
642 struct switch_val *val)
643 {
644 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
645
646 if (attr->ofs == 1)
647 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
648 else
649 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
650 }
651
652 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
653 const struct switch_attr *attr,
654 struct switch_val *val)
655 {
656 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
657 u32 data;
658
659 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
660 val->value.i = !data;
661
662 return 0;
663 }
664
665
666 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
667 const struct switch_attr *attr,
668 struct switch_val *val)
669 {
670 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
671 u32 portmask = 0;
672 int err = 0;
673
674 if (!val->value.i)
675 portmask = RTL8366RB_PORT_ALL;
676
677 /* set learning for all ports */
678 REG_WR(smi, RTL8366RB_SSCR0, portmask);
679
680 /* set auto ageing for all ports */
681 REG_WR(smi, RTL8366RB_SSCR1, portmask);
682
683 return 0;
684 }
685
686
687 static const char *rtl8366rb_speed_str(unsigned speed)
688 {
689 switch (speed) {
690 case 0:
691 return "10baseT";
692 case 1:
693 return "100baseT";
694 case 2:
695 return "1000baseT";
696 }
697
698 return "unknown";
699 }
700
701 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
702 const struct switch_attr *attr,
703 struct switch_val *val)
704 {
705 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
706 u32 len = 0, data = 0;
707
708 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
709 return -EINVAL;
710
711 memset(smi->buf, '\0', sizeof(smi->buf));
712 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
713 (val->port_vlan / 2), &data);
714
715 if (val->port_vlan % 2)
716 data = data >> 8;
717
718 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
719 len = snprintf(smi->buf, sizeof(smi->buf),
720 "port:%d link:up speed:%s %s-duplex %s%s%s",
721 val->port_vlan,
722 rtl8366rb_speed_str(data &
723 RTL8366RB_PORT_STATUS_SPEED_MASK),
724 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
725 "full" : "half",
726 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
727 "tx-pause ": "",
728 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
729 "rx-pause " : "",
730 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
731 "nway ": "");
732 } else {
733 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
734 val->port_vlan);
735 }
736
737 val->value.s = smi->buf;
738 val->len = len;
739
740 return 0;
741 }
742
743 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
744 const struct switch_attr *attr,
745 struct switch_val *val)
746 {
747 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
748 u32 data;
749 u32 mask;
750 u32 reg;
751
752 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
753 return -EINVAL;
754
755 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
756 reg = RTL8366RB_LED_BLINKRATE_REG;
757 mask = 0xF << 4;
758 data = val->value.i << 4;
759 } else {
760 reg = RTL8366RB_LED_CTRL_REG;
761 mask = 0xF << (val->port_vlan * 4),
762 data = val->value.i << (val->port_vlan * 4);
763 }
764
765 return rtl8366_smi_rmwr(smi, reg, mask, data);
766 }
767
768 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
769 const struct switch_attr *attr,
770 struct switch_val *val)
771 {
772 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
773 u32 data = 0;
774
775 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
776 return -EINVAL;
777
778 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
779 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
780
781 return 0;
782 }
783
784 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
785 const struct switch_attr *attr,
786 struct switch_val *val)
787 {
788 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
789
790 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
791 return -EINVAL;
792
793 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
794 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
795 }
796
797 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
798 {
799 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
800 int err;
801
802 err = rtl8366rb_reset_chip(smi);
803 if (err)
804 return err;
805
806 err = rtl8366rb_hw_init(smi);
807 if (err)
808 return err;
809
810 return rtl8366_reset_vlan(smi);
811 }
812
813 static struct switch_attr rtl8366rb_globals[] = {
814 {
815 .type = SWITCH_TYPE_INT,
816 .name = "enable_learning",
817 .description = "Enable learning, enable aging",
818 .set = rtl8366rb_sw_set_learning_enable,
819 .get = rtl8366rb_sw_get_learning_enable,
820 .max = 1
821 }, {
822 .type = SWITCH_TYPE_INT,
823 .name = "enable_vlan",
824 .description = "Enable VLAN mode",
825 .set = rtl8366rb_sw_set_vlan_enable,
826 .get = rtl8366rb_sw_get_vlan_enable,
827 .max = 1,
828 .ofs = 1
829 }, {
830 .type = SWITCH_TYPE_INT,
831 .name = "enable_vlan4k",
832 .description = "Enable VLAN 4K mode",
833 .set = rtl8366rb_sw_set_vlan_enable,
834 .get = rtl8366rb_sw_get_vlan_enable,
835 .max = 1,
836 .ofs = 2
837 }, {
838 .type = SWITCH_TYPE_NOVAL,
839 .name = "reset_mibs",
840 .description = "Reset all MIB counters",
841 .set = rtl8366rb_sw_reset_mibs,
842 }, {
843 .type = SWITCH_TYPE_INT,
844 .name = "blinkrate",
845 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
846 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
847 .set = rtl8366rb_sw_set_blinkrate,
848 .get = rtl8366rb_sw_get_blinkrate,
849 .max = 5
850 },
851 };
852
853 static struct switch_attr rtl8366rb_port[] = {
854 {
855 .type = SWITCH_TYPE_STRING,
856 .name = "link",
857 .description = "Get port link information",
858 .max = 1,
859 .set = NULL,
860 .get = rtl8366rb_sw_get_port_link,
861 }, {
862 .type = SWITCH_TYPE_NOVAL,
863 .name = "reset_mib",
864 .description = "Reset single port MIB counters",
865 .set = rtl8366rb_sw_reset_port_mibs,
866 }, {
867 .type = SWITCH_TYPE_STRING,
868 .name = "mib",
869 .description = "Get MIB counters for port",
870 .max = 33,
871 .set = NULL,
872 .get = rtl8366_sw_get_port_mib,
873 }, {
874 .type = SWITCH_TYPE_INT,
875 .name = "led",
876 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
877 .max = 15,
878 .set = rtl8366rb_sw_set_port_led,
879 .get = rtl8366rb_sw_get_port_led,
880 },
881 };
882
883 static struct switch_attr rtl8366rb_vlan[] = {
884 {
885 .type = SWITCH_TYPE_STRING,
886 .name = "info",
887 .description = "Get vlan information",
888 .max = 1,
889 .set = NULL,
890 .get = rtl8366_sw_get_vlan_info,
891 },
892 };
893
894 static const struct switch_dev_ops rtl8366_ops = {
895 .attr_global = {
896 .attr = rtl8366rb_globals,
897 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
898 },
899 .attr_port = {
900 .attr = rtl8366rb_port,
901 .n_attr = ARRAY_SIZE(rtl8366rb_port),
902 },
903 .attr_vlan = {
904 .attr = rtl8366rb_vlan,
905 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
906 },
907
908 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
909 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
910 .get_port_pvid = rtl8366_sw_get_port_pvid,
911 .set_port_pvid = rtl8366_sw_set_port_pvid,
912 .reset_switch = rtl8366rb_sw_reset_switch,
913 };
914
915 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
916 {
917 struct switch_dev *dev = &smi->sw_dev;
918 int err;
919
920 dev->name = "RTL8366RB";
921 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
922 dev->ports = RTL8366RB_NUM_PORTS;
923 dev->vlans = RTL8366RB_NUM_VLANS;
924 dev->ops = &rtl8366_ops;
925 dev->devname = dev_name(smi->parent);
926
927 err = register_switch(dev, NULL);
928 if (err)
929 dev_err(smi->parent, "switch registration failed\n");
930
931 return err;
932 }
933
934 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
935 {
936 unregister_switch(&smi->sw_dev);
937 }
938
939 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
940 {
941 struct rtl8366_smi *smi = bus->priv;
942 u32 val = 0;
943 int err;
944
945 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
946 if (err)
947 return 0xffff;
948
949 return val;
950 }
951
952 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
953 {
954 struct rtl8366_smi *smi = bus->priv;
955 u32 t;
956 int err;
957
958 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
959 /* flush write */
960 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
961
962 return err;
963 }
964
965 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
966 {
967 return (bus->read == rtl8366rb_mii_read &&
968 bus->write == rtl8366rb_mii_write);
969 }
970
971 static int rtl8366rb_setup(struct rtl8366_smi *smi)
972 {
973 int ret;
974
975 ret = rtl8366rb_reset_chip(smi);
976 if (ret)
977 return ret;
978
979 ret = rtl8366rb_hw_init(smi);
980 return ret;
981 }
982
983 static int rtl8366rb_detect(struct rtl8366_smi *smi)
984 {
985 u32 chip_id = 0;
986 u32 chip_ver = 0;
987 int ret;
988
989 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
990 if (ret) {
991 dev_err(smi->parent, "unable to read chip id\n");
992 return ret;
993 }
994
995 switch (chip_id) {
996 case RTL8366RB_CHIP_ID_8366:
997 break;
998 default:
999 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1000 return -ENODEV;
1001 }
1002
1003 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1004 &chip_ver);
1005 if (ret) {
1006 dev_err(smi->parent, "unable to read chip version\n");
1007 return ret;
1008 }
1009
1010 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1011 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1012
1013 return 0;
1014 }
1015
1016 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1017 .detect = rtl8366rb_detect,
1018 .setup = rtl8366rb_setup,
1019
1020 .mii_read = rtl8366rb_mii_read,
1021 .mii_write = rtl8366rb_mii_write,
1022
1023 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1024 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1025 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1026 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1027 .get_mc_index = rtl8366rb_get_mc_index,
1028 .set_mc_index = rtl8366rb_set_mc_index,
1029 .get_mib_counter = rtl8366rb_get_mib_counter,
1030 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1031 };
1032
1033 static int __init rtl8366rb_probe(struct platform_device *pdev)
1034 {
1035 static int rtl8366_smi_version_printed;
1036 struct rtl8366rb_platform_data *pdata;
1037 struct rtl8366_smi *smi;
1038 int err;
1039
1040 if (!rtl8366_smi_version_printed++)
1041 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1042 " version " RTL8366RB_DRIVER_VER"\n");
1043
1044 pdata = pdev->dev.platform_data;
1045 if (!pdata) {
1046 dev_err(&pdev->dev, "no platform data specified\n");
1047 err = -EINVAL;
1048 goto err_out;
1049 }
1050
1051 smi = rtl8366_smi_alloc(&pdev->dev);
1052 if (!smi) {
1053 err = -ENOMEM;
1054 goto err_out;
1055 }
1056
1057 smi->gpio_sda = pdata->gpio_sda;
1058 smi->gpio_sck = pdata->gpio_sck;
1059 smi->ops = &rtl8366rb_smi_ops;
1060 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1061 smi->num_ports = RTL8366RB_NUM_PORTS;
1062 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1063 smi->mib_counters = rtl8366rb_mib_counters;
1064 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1065
1066 err = rtl8366_smi_init(smi);
1067 if (err)
1068 goto err_free_smi;
1069
1070 platform_set_drvdata(pdev, smi);
1071
1072 err = rtl8366rb_switch_init(smi);
1073 if (err)
1074 goto err_clear_drvdata;
1075
1076 return 0;
1077
1078 err_clear_drvdata:
1079 platform_set_drvdata(pdev, NULL);
1080 rtl8366_smi_cleanup(smi);
1081 err_free_smi:
1082 kfree(smi);
1083 err_out:
1084 return err;
1085 }
1086
1087 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1088 {
1089 if (!rtl8366rb_mii_bus_match(phydev->bus))
1090 return -EINVAL;
1091
1092 return 0;
1093 }
1094
1095 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1096 {
1097 return 0;
1098 }
1099
1100 static struct phy_driver rtl8366rb_phy_driver = {
1101 .phy_id = 0x001cc960,
1102 .name = "Realtek RTL8366RB",
1103 .phy_id_mask = 0x1ffffff0,
1104 .features = PHY_GBIT_FEATURES,
1105 .config_aneg = rtl8366rb_phy_config_aneg,
1106 .config_init = rtl8366rb_phy_config_init,
1107 .read_status = genphy_read_status,
1108 .driver = {
1109 .owner = THIS_MODULE,
1110 },
1111 };
1112
1113 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1114 {
1115 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1116
1117 if (smi) {
1118 rtl8366rb_switch_cleanup(smi);
1119 platform_set_drvdata(pdev, NULL);
1120 rtl8366_smi_cleanup(smi);
1121 kfree(smi);
1122 }
1123
1124 return 0;
1125 }
1126
1127 static struct platform_driver rtl8366rb_driver = {
1128 .driver = {
1129 .name = RTL8366RB_DRIVER_NAME,
1130 .owner = THIS_MODULE,
1131 },
1132 .probe = rtl8366rb_probe,
1133 .remove = __devexit_p(rtl8366rb_remove),
1134 };
1135
1136 static int __init rtl8366rb_module_init(void)
1137 {
1138 int ret;
1139 ret = platform_driver_register(&rtl8366rb_driver);
1140 if (ret)
1141 return ret;
1142
1143 ret = phy_driver_register(&rtl8366rb_phy_driver);
1144 if (ret)
1145 goto err_platform_unregister;
1146
1147 return 0;
1148
1149 err_platform_unregister:
1150 platform_driver_unregister(&rtl8366rb_driver);
1151 return ret;
1152 }
1153 module_init(rtl8366rb_module_init);
1154
1155 static void __exit rtl8366rb_module_exit(void)
1156 {
1157 phy_driver_unregister(&rtl8366rb_phy_driver);
1158 platform_driver_unregister(&rtl8366rb_driver);
1159 }
1160 module_exit(rtl8366rb_module_exit);
1161
1162 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1163 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1164 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1165 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1166 MODULE_LICENSE("GPL v2");
1167 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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