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[openwrt.git] / target / linux / ifxmips / files / drivers / char / ifxmips_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 // ### TO DO: general issues:
22 // - power management
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fs.h>
37 #include <linux/fcntl.h>
38 #include <linux/ptrace.h>
39 #include <linux/mm.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/spinlock.h>
44 #include <linux/slab.h>
45
46 #include <asm/system.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/uaccess.h>
50 #include <asm/bitops.h>
51
52 #include <linux/types.h>
53 #include <linux/kernel.h>
54 #include <linux/version.h>
55
56 #include <asm/ifxmips/ifxmips.h>
57 #include <asm/ifxmips/ifxmips_irq.h>
58 #include <asm/ifxmips/ifx_ssc_defines.h>
59 #include <asm/ifxmips/ifx_ssc.h>
60
61 #ifdef SSC_FRAME_INT_ENABLE
62 #undef SSC_FRAME_INT_ENABLE
63 #endif
64
65 #define not_yet
66
67 #define SPI_VINETIC
68
69
70
71 /* allow the user to set the major device number */
72 static int maj = 0;
73
74 /*
75 * This is the per-channel data structure containing pointers, flags
76 * and variables for the port. This driver supports a maximum of PORT_CNT.
77 * isp is allocated in ifx_ssc_init() based on the chip version.
78 */
79 static struct ifx_ssc_port *isp;
80
81 /* prototypes for fops */
82 static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
83 static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
84 //static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
85 int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
86 unsigned long);
87 int ifx_ssc_open (struct inode *, struct file *);
88 int ifx_ssc_close (struct inode *, struct file *);
89
90 /* other forward declarations */
91 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
92 static void tx_int (struct ifx_ssc_port *);
93
94 extern unsigned int ifxmips_get_fpi_hz (void);
95 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
96
97 static struct file_operations ifx_ssc_fops = {
98 .owner = THIS_MODULE,
99 .read = ifx_ssc_read,
100 .write = ifx_ssc_write,
101 .ioctl = ifx_ssc_ioctl,
102 .open = ifx_ssc_open,
103 .release = ifx_ssc_close,
104 };
105
106 static inline unsigned int
107 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
108 {
109 unsigned int rmc;
110
111 rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
112 if (rmc == 0)
113 {
114 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
115 return 0;
116 }
117 return ifxmips_get_fpi_hz () / rmc;
118 }
119
120 #ifndef not_yet
121 #ifdef IFX_SSC_INT_USE_BH
122 /*
123 * This routine is used by the interrupt handler to schedule
124 * processing in the software interrupt portion of the driver
125 * (also known as the "bottom half"). This can be called any
126 * number of times for any channel without harm.
127 */
128 static inline void
129 ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
130 {
131 info->event |= 1 << event; /* remember what kind of event and who */
132 queue_task (&info->tqueue, &tq_cyclades); /* it belongs to */
133 mark_bh (CYCLADES_BH); /* then trigger event */
134 }
135
136 static void
137 do_softint (void *private_)
138 {
139 struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
140
141 if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event))
142 {
143 wake_up_interruptible (&info->open_wait);
144 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
145 }
146
147 if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event))
148 wake_up_interruptible (&info->open_wait);
149
150 if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event))
151 wake_up_interruptible (&info->delta_msr_wait);
152
153 if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event))
154 wake_up_interruptible (&tty->write_wait);
155 #ifdef Z_WAKE
156 if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event))
157 wake_up_interruptible (&info->shutdown_wait);
158 #endif
159 }
160 #endif
161 #endif
162
163 inline static void
164 rx_int (struct ifx_ssc_port *info)
165 {
166 int fifo_fill_lev, bytes_in_buf, i;
167 unsigned long tmp_val;
168 unsigned long *tmp_ptr;
169 unsigned int rx_valid_cnt;
170 /* number of words waiting in the RX FIFO */
171 fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
172 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
173 // transfer with 32 bits per entry
174 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
175 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
176 *tmp_ptr = readl(IFXMIPS_SSC_RB);
177 info->rxbuf_ptr += 4;
178 info->stats.rxBytes += 4;
179 fifo_fill_lev--;
180 bytes_in_buf -= 4;
181 }
182
183 // now do the rest as mentioned in STATE.RXBV
184 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
185 rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
186 if (rx_valid_cnt == 0)
187 break;
188
189 if (rx_valid_cnt > bytes_in_buf)
190 rx_valid_cnt = bytes_in_buf;
191
192 tmp_val = readl(IFXMIPS_SSC_RB);
193
194 for (i = 0; i < rx_valid_cnt; i++)
195 {
196 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
197 bytes_in_buf--;
198 info->rxbuf_ptr++;
199 }
200 info->stats.rxBytes += rx_valid_cnt;
201 }
202
203 // check if transfer is complete
204 if (info->rxbuf_ptr >= info->rxbuf_end)
205 {
206 disable_irq(info->rxirq);
207 wake_up_interruptible (&info->rwait);
208 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
209 {
210 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
211 writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
212 else
213 writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
214 }
215 }
216
217 inline static void
218 tx_int (struct ifx_ssc_port *info)
219 {
220
221 int fifo_space, fill, i;
222 fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
223 - ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
224
225 if (fifo_space == 0)
226 return;
227
228 fill = info->txbuf_end - info->txbuf_ptr;
229
230 if (fill > fifo_space * 4)
231 fill = fifo_space * 4;
232
233 for (i = 0; i < fill / 4; i++)
234 {
235 // at first 32 bit access
236 writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
237 info->txbuf_ptr += 4;
238 }
239
240 fifo_space -= fill / 4;
241 info->stats.txBytes += fill & ~0x3;
242 fill &= 0x3;
243 if ((fifo_space > 0) & (fill > 1))
244 {
245 // trailing 16 bit access
246 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
247 info->txbuf_ptr += 2;
248 info->stats.txBytes += 2;
249 fifo_space--;
250 fill -= 2;
251 }
252
253 if ((fifo_space > 0) & (fill > 0))
254 {
255 // trailing 8 bit access
256 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
257 info->txbuf_ptr++;
258 info->stats.txBytes++;
259 }
260
261 // check if transmission complete
262 if (info->txbuf_ptr >= info->txbuf_end)
263 {
264 disable_irq(info->txirq);
265 kfree (info->txbuf);
266 info->txbuf = NULL;
267 }
268
269 }
270
271 irqreturn_t
272 ifx_ssc_rx_int (int irq, void *dev_id)
273 {
274 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
275 rx_int (info);
276
277 return IRQ_HANDLED;
278 }
279
280 irqreturn_t
281 ifx_ssc_tx_int (int irq, void *dev_id)
282 {
283 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
284 tx_int (info);
285
286 return IRQ_HANDLED;
287 }
288
289 irqreturn_t
290 ifx_ssc_err_int (int irq, void *dev_id)
291 {
292 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
293 unsigned int state;
294 unsigned int write_back = 0;
295 unsigned long flags;
296
297 local_irq_save (flags);
298 state = readl(IFXMIPS_SSC_STATE);
299
300 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
301 info->stats.rxUnErr++;
302 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
303 }
304
305 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
306 info->stats.rxOvErr++;
307 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
308 }
309
310 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
311 info->stats.txOvErr++;
312 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
313 }
314
315 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
316 info->stats.txUnErr++;
317 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
318 }
319
320 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
321 info->stats.modeErr++;
322 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
323 }
324
325 if (write_back)
326 writel(write_back, IFXMIPS_SSC_WHBSTATE);
327
328 local_irq_restore (flags);
329
330 return IRQ_HANDLED;
331 }
332
333 static void
334 ifx_ssc_abort (struct ifx_ssc_port *info)
335 {
336 unsigned long flags;
337 bool enabled;
338
339 local_irq_save (flags);
340
341 disable_irq(info->rxirq);
342 disable_irq(info->txirq);
343 disable_irq(info->errirq);
344
345 local_irq_restore (flags);
346
347 // disable SSC (also aborts a receive request!)
348 // ### TO DO: Perhaps it's better to abort after the receiption of a
349 // complete word. The disable cuts the transmission immediatly and
350 // releases the chip selects. This could result in unpredictable
351 // behavior of connected external devices!
352 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
353 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
354
355 // flush fifos
356 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
357 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
358
359 // free txbuf
360 if (info->txbuf != NULL)
361 {
362 kfree (info->txbuf);
363 info->txbuf = NULL;
364 }
365
366 // wakeup read process
367 if (info->rxbuf != NULL)
368 wake_up_interruptible (&info->rwait);
369
370 // clear pending int's
371 mask_and_ack_ifxmips_irq(info->rxirq);
372 mask_and_ack_ifxmips_irq(info->txirq);
373 mask_and_ack_ifxmips_irq(info->errirq);
374
375 // clear error flags
376 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
377
378 if (enabled)
379 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
380
381 }
382
383 /*
384 * This routine is called whenever a port is opened. It enforces
385 * exclusive opening of a port and enables interrupts, etc.
386 */
387 int
388 ifx_ssc_open (struct inode *inode, struct file *filp)
389 {
390 struct ifx_ssc_port *info;
391 int line;
392 int from_kernel = 0;
393
394 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
395 from_kernel = 1;
396 line = (int) inode;
397 } else {
398 line = MINOR (filp->f_dentry->d_inode->i_rdev);
399 filp->f_op = &ifx_ssc_fops;
400 }
401
402 /* don't open more minor devices than we can support */
403 if (line < 0 || line >= PORT_CNT)
404 return -ENXIO;
405
406 info = &isp[line];
407
408 /* exclusive open */
409 if (info->port_is_open != 0)
410 return -EBUSY;
411 info->port_is_open++;
412
413 disable_irq(info->rxirq);
414 disable_irq(info->txirq);
415 disable_irq(info->errirq);
416
417 /* Flush and enable TX/RX FIFO */
418 writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
419 writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
420
421 /* logically flush the software FIFOs */
422 info->rxbuf_ptr = 0;
423 info->txbuf_ptr = 0;
424
425 /* clear all error bits */
426 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
427
428 // clear pending interrupts
429 mask_and_ack_ifxmips_irq(info->rxirq);
430 mask_and_ack_ifxmips_irq(info->txirq);
431 mask_and_ack_ifxmips_irq(info->errirq);
432
433 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
434
435 return 0;
436 }
437 EXPORT_SYMBOL(ifx_ssc_open);
438
439 int
440 ifx_ssc_close (struct inode *inode, struct file *filp)
441 {
442 struct ifx_ssc_port *info;
443 int idx;
444
445 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
446 idx = (int) inode;
447 else
448 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
449
450 if (idx < 0 || idx >= PORT_CNT)
451 return -ENXIO;
452
453 info = &isp[idx];
454 if (!info)
455 return -ENXIO;
456
457 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
458
459 ifx_ssc_abort(info);
460
461 info->port_is_open--;
462
463 return 0;
464 }
465 EXPORT_SYMBOL(ifx_ssc_close);
466
467 static ssize_t
468 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
469 {
470 ssize_t ret_val;
471 unsigned long flags;
472
473 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
474 return -EFAULT;
475 local_irq_save (flags);
476 info->rxbuf_ptr = info->rxbuf;
477 info->rxbuf_end = info->rxbuf + len;
478 local_irq_restore (flags);
479 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
480 /* TXRX in poll mode */
481 while (info->rxbuf_ptr < info->rxbuf_end)
482 {
483 if (info->txbuf_ptr < info->txbuf_end)
484 tx_int (info);
485
486 rx_int (info);
487 };
488
489 ret_val = info->rxbuf_ptr - info->rxbuf;
490
491 return ret_val;
492 }
493
494 static ssize_t
495 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
496 {
497 ssize_t ret_val;
498 unsigned long flags;
499 DECLARE_WAITQUEUE (wait, current);
500
501 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
502 return -EFAULT;
503
504 local_irq_save (flags);
505 info->rxbuf_ptr = info->rxbuf;
506 info->rxbuf_end = info->rxbuf + len;
507
508 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
509 {
510 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
511 {
512 local_irq_restore (flags);
513 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
514 return -EFAULT;
515 }
516
517 local_irq_restore(flags);
518 tx_int (info);
519
520 if (info->txbuf_ptr < info->txbuf_end)
521 enable_irq(info->txirq);
522
523 enable_irq(info->rxirq);
524 } else {
525 local_irq_restore(flags);
526 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
527 return -EBUSY;
528 enable_irq(info->rxirq);
529 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
530 WRITE_PERIPHERAL_REGISTER (len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
531 else
532 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
533 }
534
535 __add_wait_queue (&info->rwait, &wait);
536 set_current_state (TASK_INTERRUPTIBLE);
537
538 do {
539 local_irq_save (flags);
540 if (info->rxbuf_ptr >= info->rxbuf_end)
541 break;
542
543 local_irq_restore (flags);
544
545 if (signal_pending (current))
546 {
547 ret_val = -ERESTARTSYS;
548 goto out;
549 }
550 schedule();
551 } while (1);
552
553 ret_val = info->rxbuf_ptr - info->rxbuf;
554 local_irq_restore (flags);
555
556 out:
557 current->state = TASK_RUNNING;
558 __remove_wait_queue (&info->rwait, &wait);
559
560 return (ret_val);
561 }
562
563 static ssize_t
564 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
565 size_t len, int from_kernel)
566 {
567 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
568 return -EFAULT;
569
570 info->txbuf_ptr = info->txbuf;
571 info->txbuf_end = len + info->txbuf;
572 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
573 {
574 tx_int (info);
575 if (info->txbuf_ptr < info->txbuf_end)
576 {
577 enable_irq(info->txirq);
578 }
579 }
580
581 return len;
582 }
583
584 ssize_t
585 ifx_ssc_kread (int port, char *kbuf, size_t len)
586 {
587 struct ifx_ssc_port *info;
588 ssize_t ret_val;
589
590 if (port < 0 || port >= PORT_CNT)
591 return -ENXIO;
592
593 if (len == 0)
594 return 0;
595
596 info = &isp[port];
597
598 if (info->rxbuf != NULL)
599 {
600 printk ("SSC device busy\n");
601 return -EBUSY;
602 }
603
604 info->rxbuf = kbuf;
605 if (info->rxbuf == NULL)
606 {
607 printk ("SSC device error\n");
608 return -EINVAL;
609 }
610
611 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
612 info->rxbuf = NULL;
613
614 disable_irq(info->rxirq);
615
616 return ret_val;
617 }
618 EXPORT_SYMBOL(ifx_ssc_kread);
619
620 ssize_t
621 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
622 {
623 struct ifx_ssc_port *info;
624 ssize_t ret_val;
625
626 if (port < 0 || port >= PORT_CNT)
627 return -ENXIO;
628
629 if (len == 0)
630 return 0;
631
632 info = &isp[port];
633
634 // check if transmission in progress
635 if (info->txbuf != NULL)
636 return -EBUSY;
637
638 info->txbuf = (char *) kbuf;
639
640 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
641
642 if (ret_val < 0)
643 info->txbuf = NULL;
644
645 return ret_val;
646 }
647 EXPORT_SYMBOL(ifx_ssc_kwrite);
648
649 static ssize_t
650 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
651 {
652 ssize_t ret_val;
653 int idx;
654 struct ifx_ssc_port *info;
655
656 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
657 info = &isp[idx];
658
659 if (info->rxbuf != NULL)
660 return -EBUSY;
661
662 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
663 if (info->rxbuf == NULL)
664 return -ENOMEM;
665
666 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
667 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
668 ret_val = -EFAULT;
669
670 disable_irq(info->rxirq);
671
672 kfree (info->rxbuf);
673 info->rxbuf = NULL;
674
675 return (ret_val);
676 }
677
678 static ssize_t
679 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
680 {
681 int idx;
682 struct ifx_ssc_port *info;
683 int ret_val;
684
685 if (len == 0)
686 return (0);
687
688 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
689 info = &isp[idx];
690
691 if (info->txbuf != NULL)
692 return -EBUSY;
693
694 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
695 if (info->txbuf == NULL)
696 return -ENOMEM;
697
698 ret_val = copy_from_user (info->txbuf, ubuf, len);
699 if (ret_val == 0)
700 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
701 else
702 ret_val = -EFAULT;
703
704 if (ret_val < 0)
705 {
706 kfree (info->txbuf);
707 info->txbuf = NULL;
708 }
709
710 return (ret_val);
711 }
712
713 static struct ifx_ssc_frm_status *
714 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
715 {
716 unsigned long tmp;
717
718 tmp = readl(IFXMIPS_SSC_SFSTAT);
719 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
720 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
721 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
722 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
723 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
724 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
725 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
726
727 return &info->frm_status;
728 }
729
730
731 static struct ifx_ssc_frm_opts *
732 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
733 {
734 unsigned long tmp;
735
736 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
737 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
738 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
739 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
740 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
741 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
742 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
743
744 return &info->frm_opts;
745 }
746
747 static int
748 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
749 {
750 unsigned long tmp;
751
752 // check parameters
753 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
754 || (info->frm_opts.DataLength < 1)
755 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
756 || (info->frm_opts.PauseLength < 1)
757 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
758 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
759 return -EINVAL;
760
761 // read interrupt bits (they're not changed here)
762 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
763 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
764
765 // set all values with respect to it's bit position (for data and pause
766 // length set N-1)
767 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
768 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
769 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
770 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
771 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
772 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
773
774 WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
775
776 return 0;
777 }
778
779 static int
780 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
781 {
782 unsigned long tmp;
783
784 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
785 return -EINVAL;
786
787 if ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY)
788 || (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
789 return -EBUSY;
790
791 tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
792 WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
793 info->opts.modeRxTx = val;
794
795 return 0;
796 }
797
798 static int
799 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
800 {
801 unsigned long flags, bits;
802 struct ifx_ssc_hwopts *opts = &info->opts;
803
804 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
805 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
806 return -EINVAL;
807
808 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
809 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
810
811 if (opts->rxOvErrDetect)
812 bits |= IFX_SSC_CON_RX_OFL_CHECK;
813 if (opts->rxUndErrDetect)
814 bits |= IFX_SSC_CON_RX_UFL_CHECK;
815 if (opts->txOvErrDetect)
816 bits |= IFX_SSC_CON_TX_OFL_CHECK;
817 if (opts->txUndErrDetect)
818 bits |= IFX_SSC_CON_TX_UFL_CHECK;
819 if (opts->loopBack)
820 bits |= IFX_SSC_CON_LOOPBACK_MODE;
821 if (opts->echoMode)
822 bits |= IFX_SSC_CON_ECHO_MODE_ON;
823 if (opts->headingControl)
824 bits |= IFX_SSC_CON_MSB_FIRST;
825 if (opts->clockPhase)
826 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
827 if (opts->clockPolarity)
828 bits |= IFX_SSC_CON_CLOCK_FALL;
829
830 switch (opts->modeRxTx)
831 {
832 case IFX_SSC_MODE_TX:
833 bits |= IFX_SSC_CON_RX_OFF;
834 break;
835 case IFX_SSC_MODE_RX:
836 bits |= IFX_SSC_CON_TX_OFF;
837 break;
838 }
839
840 local_irq_save (flags);
841
842 WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
843 WRITE_PERIPHERAL_REGISTER ((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
844 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), info->mapbase + IFX_SSC_GPOCON);
845
846 WRITE_PERIPHERAL_REGISTER (info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, info->mapbase + IFX_SSC_WHBGPOSTAT);
847
848 //master mode
849 if (opts->masterSelect)
850 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
851 else
852 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
853
854 // init serial framing
855 WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
856 /* set up the port pins */
857 //check for general requirements to switch (external) pad/pin characteristics
858 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
859 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
860 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
861 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
862 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
863 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
864 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
865
866 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
867 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
868 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
869 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
870 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
871
872 /*CS3 */
873 /*TODO: CS4 CS5 CS6 */
874 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
875
876 local_irq_restore (flags);
877
878 return 0;
879 }
880
881 static int
882 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
883 {
884 unsigned int ifx_ssc_clock;
885 unsigned int br;
886 unsigned long flags;
887 bool enabled;
888 int retval = 0;
889
890 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
891 if (ifx_ssc_clock == 0)
892 {
893 retval = -EINVAL;
894 goto out;
895 }
896
897 local_irq_save (flags);
898
899 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
900 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
901
902 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
903 wmb();
904
905 if (br > 0xffff || ((br == 0) &&
906 ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
907 local_irq_restore (flags);
908 printk ("%s: invalid baudrate %u\n", __func__, baud);
909 return -EINVAL;
910 }
911
912 WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
913
914 if (enabled)
915 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
916
917 local_irq_restore(flags);
918
919 out:
920 return retval;
921 }
922
923 static int
924 ifx_ssc_hwinit (struct ifx_ssc_port *info)
925 {
926 unsigned long flags;
927 bool enabled;
928
929 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
930 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
931
932 if (ifx_ssc_sethwopts (info) < 0)
933 {
934 printk ("%s: setting the hardware options failed\n", __func__);
935 return -EINVAL;
936 }
937
938 if (ifx_ssc_set_baud (info, info->baud) < 0)
939 {
940 printk ("%s: setting the baud rate failed\n", __func__);
941 return -EINVAL;
942 }
943
944 local_irq_save (flags);
945
946 /* TX FIFO */
947 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
948 info->mapbase + IFX_SSC_TXFCON);
949 /* RX FIFO */
950 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
951 info->mapbase + IFX_SSC_RXFCON);
952
953 local_irq_restore (flags);
954
955 if (enabled)
956 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
957
958 return 0;
959 }
960
961 int
962 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
963 {
964 struct ifx_ssc_port *info;
965 int line, ret_val = 0;
966 unsigned long flags;
967 unsigned long tmp;
968 int from_kernel = 0;
969
970 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
971 {
972 from_kernel = 1;
973 line = (int) inode;
974 } else {
975 line = MINOR (filp->f_dentry->d_inode->i_rdev);
976 }
977
978 if (line < 0 || line >= PORT_CNT)
979 return -ENXIO;
980
981 info = &isp[line];
982
983 switch (cmd)
984 {
985 case IFX_SSC_STATS_READ:
986 /* data must be a pointer to a struct ifx_ssc_statistics */
987 if (from_kernel)
988 memcpy ((void *) data, (void *) &info->stats,
989 sizeof (struct ifx_ssc_statistics));
990 else if (copy_to_user ((void *) data,
991 (void *) &info->stats,
992 sizeof (struct ifx_ssc_statistics)))
993 ret_val = -EFAULT;
994 break;
995 case IFX_SSC_STATS_RESET:
996 /* just resets the statistics counters */
997 memset ((void *) &info->stats, 0,
998 sizeof (struct ifx_ssc_statistics));
999 break;
1000 case IFX_SSC_BAUD_SET:
1001 /* if the buffers are not empty then the port is */
1002 /* busy and we shouldn't change things on-the-fly! */
1003 if (!info->txbuf || !info->rxbuf ||
1004 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1005 & IFX_SSC_STATE_BUSY)) {
1006 ret_val = -EBUSY;
1007 break;
1008 }
1009 /* misuse flags */
1010 if (from_kernel)
1011 flags = *((unsigned long *) data);
1012 else if (copy_from_user ((void *) &flags,
1013 (void *) data, sizeof (flags))) {
1014 ret_val = -EFAULT;
1015 break;
1016 }
1017 if (flags == 0) {
1018 ret_val = -EINVAL;
1019 break;
1020 }
1021 if (ifx_ssc_set_baud (info, flags) < 0) {
1022 ret_val = -EINVAL;
1023 break;
1024 }
1025 info->baud = flags;
1026 break;
1027 case IFX_SSC_BAUD_GET:
1028 if (from_kernel)
1029 *((unsigned int *) data) = info->baud;
1030 else if (copy_to_user ((void *) data,
1031 (void *) &info->baud,
1032 sizeof (unsigned long)))
1033 ret_val = -EFAULT;
1034 break;
1035 case IFX_SSC_RXTX_MODE_SET:
1036 if (from_kernel)
1037 tmp = *((unsigned long *) data);
1038 else if (copy_from_user ((void *) &tmp,
1039 (void *) data, sizeof (tmp))) {
1040 ret_val = -EFAULT;
1041 break;
1042 }
1043 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
1044 break;
1045 case IFX_SSC_RXTX_MODE_GET:
1046 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
1047 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
1048 if (from_kernel)
1049 *((unsigned int *) data) = tmp;
1050 else if (copy_to_user ((void *) data,
1051 (void *) &tmp, sizeof (tmp)))
1052 ret_val = -EFAULT;
1053 break;
1054
1055 case IFX_SSC_ABORT:
1056 ifx_ssc_abort (info);
1057 break;
1058
1059 case IFX_SSC_GPO_OUT_SET:
1060 if (from_kernel)
1061 tmp = *((unsigned long *) data);
1062 else if (copy_from_user ((void *) &tmp,
1063 (void *) data, sizeof (tmp))) {
1064 ret_val = -EFAULT;
1065 break;
1066 }
1067 if (tmp > IFX_SSC_MAX_GPO_OUT)
1068 ret_val = -EINVAL;
1069 else
1070 WRITE_PERIPHERAL_REGISTER
1071 (1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
1072 info->mapbase + IFX_SSC_WHBGPOSTAT);
1073 break;
1074 case IFX_SSC_GPO_OUT_CLR:
1075 if (from_kernel)
1076 tmp = *((unsigned long *) data);
1077 else if (copy_from_user ((void *) &tmp,
1078 (void *) data, sizeof (tmp))) {
1079 ret_val = -EFAULT;
1080 break;
1081 }
1082 if (tmp > IFX_SSC_MAX_GPO_OUT)
1083 ret_val = -EINVAL;
1084 else {
1085 WRITE_PERIPHERAL_REGISTER
1086 (1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1087 info->mapbase + IFX_SSC_WHBGPOSTAT);
1088 }
1089 break;
1090 case IFX_SSC_GPO_OUT_GET:
1091 tmp = READ_PERIPHERAL_REGISTER
1092 (info->mapbase + IFX_SSC_GPOSTAT);
1093 if (from_kernel)
1094 *((unsigned int *) data) = tmp;
1095 else if (copy_to_user ((void *) data,
1096 (void *) &tmp, sizeof (tmp)))
1097 ret_val = -EFAULT;
1098 break;
1099 case IFX_SSC_FRM_STATUS_GET:
1100 ifx_ssc_frm_status_get (info);
1101 if (from_kernel)
1102 memcpy ((void *) data, (void *) &info->frm_status,
1103 sizeof (struct ifx_ssc_frm_status));
1104 else if (copy_to_user ((void *) data,
1105 (void *) &info->frm_status,
1106 sizeof (struct ifx_ssc_frm_status)))
1107 ret_val = -EFAULT;
1108 break;
1109 case IFX_SSC_FRM_CONTROL_GET:
1110 ifx_ssc_frm_control_get (info);
1111 if (from_kernel)
1112 memcpy ((void *) data, (void *) &info->frm_opts,
1113 sizeof (struct ifx_ssc_frm_opts));
1114 else if (copy_to_user ((void *) data,
1115 (void *) &info->frm_opts,
1116 sizeof (struct ifx_ssc_frm_opts)))
1117 ret_val = -EFAULT;
1118 break;
1119 case IFX_SSC_FRM_CONTROL_SET:
1120 if (from_kernel)
1121 memcpy ((void *) &info->frm_opts, (void *) data,
1122 sizeof (struct ifx_ssc_frm_opts));
1123 else if (copy_to_user ((void *) &info->frm_opts,
1124 (void *) data,
1125 sizeof (struct ifx_ssc_frm_opts))) {
1126 ret_val = -EFAULT;
1127 break;
1128 }
1129 ret_val = ifx_ssc_frm_control_set (info);
1130 break;
1131 case IFX_SSC_HWOPTS_SET:
1132 /* data must be a pointer to a struct ifx_ssc_hwopts */
1133 /* if the buffers are not empty then the port is */
1134 /* busy and we shouldn't change things on-the-fly! */
1135 if (!info->txbuf || !info->rxbuf ||
1136 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1137 & IFX_SSC_STATE_BUSY)) {
1138 ret_val = -EBUSY;
1139 break;
1140 }
1141 if (from_kernel)
1142 memcpy ((void *) &info->opts, (void *) data,
1143 sizeof (struct ifx_ssc_hwopts));
1144 else if (copy_from_user ((void *) &info->opts,
1145 (void *) data,
1146 sizeof (struct ifx_ssc_hwopts))) {
1147 ret_val = -EFAULT;
1148 break;
1149 }
1150 if (ifx_ssc_hwinit (info) < 0) {
1151 ret_val = -EIO;
1152 }
1153 break;
1154 case IFX_SSC_HWOPTS_GET:
1155 /* data must be a pointer to a struct ifx_ssc_hwopts */
1156 if (from_kernel)
1157 memcpy ((void *) data, (void *) &info->opts,
1158 sizeof (struct ifx_ssc_hwopts));
1159 else if (copy_to_user ((void *) data,
1160 (void *) &info->opts,
1161 sizeof (struct ifx_ssc_hwopts)))
1162 ret_val = -EFAULT;
1163 break;
1164 default:
1165 ret_val = -ENOIOCTLCMD;
1166 }
1167
1168 return ret_val;
1169 }
1170 EXPORT_SYMBOL(ifx_ssc_ioctl);
1171
1172 int __init
1173 ifx_ssc_init (void)
1174 {
1175 struct ifx_ssc_port *info;
1176 int i, nbytes;
1177 unsigned long flags;
1178 int ret_val;
1179
1180 ret_val = -ENOMEM;
1181 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1182 isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
1183
1184 if (isp == NULL)
1185 {
1186 printk("%s: no memory for isp\n", __func__);
1187 return (ret_val);
1188 }
1189 memset(isp, 0, nbytes);
1190
1191 ret_val = -ENXIO;
1192 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1193 {
1194 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1195 if (maj == 0)
1196 {
1197 goto errout;
1198 } else {
1199 maj = 0;
1200 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1201 {
1202 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1203 goto errout;
1204 }
1205 }
1206 }
1207
1208 if (maj == 0)
1209 maj = i;
1210
1211 /* set default values in ifx_ssc_port */
1212 for (i = 0; i < PORT_CNT; i++) {
1213 info = &isp[i];
1214 info->port_nr = i;
1215 /* default values for the HwOpts */
1216 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1217 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1218 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1219 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1220 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1221 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1222 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1223 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1224 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1225 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1226 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1227 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1228 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1229 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1230 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1231 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1232 info->baud = IFX_SSC_DEF_BAUDRATE;
1233 info->rxbuf = NULL;
1234 info->txbuf = NULL;
1235 /* values specific to SSC1 */
1236 if (i == 0) {
1237 info->mapbase = IFXMIPS_SSC_BASE_ADDR;
1238 info->txirq = IFXMIPS_SSC_TIR;
1239 info->rxirq = IFXMIPS_SSC_RIR;
1240 info->errirq = IFXMIPS_SSC_EIR;
1241 }
1242
1243 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
1244
1245 init_waitqueue_head (&info->rwait);
1246
1247 local_irq_save (flags);
1248
1249 // init serial framing register
1250 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
1251
1252 ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
1253 if (ret_val)
1254 {
1255 printk("%s: unable to get irq %d\n", __func__, info->txirq);
1256 local_irq_restore(flags);
1257 goto errout;
1258 }
1259
1260 ret_val = request_irq(info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
1261 if (ret_val)
1262 {
1263 printk ("%s: unable to get irq %d\n", __func__, info->rxirq);
1264 local_irq_restore (flags);
1265 goto irqerr;
1266 }
1267
1268 ret_val = request_irq(info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
1269 if (ret_val)
1270 {
1271 printk ("%s: unable to get irq %d\n", __func__, info->errirq);
1272 local_irq_restore (flags);
1273 goto irqerr;
1274 }
1275 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
1276
1277 enable_irq(info->txirq);
1278 enable_irq(info->rxirq);
1279 enable_irq(info->errirq);
1280
1281 local_irq_restore (flags);
1282 }
1283
1284 for (i = 0; i < PORT_CNT; i++) {
1285 info = &isp[i];
1286 if (ifx_ssc_hwinit (info) < 0)
1287 {
1288 printk ("%s: hardware init failed for port %d\n", __func__, i);
1289 goto irqerr;
1290 }
1291 }
1292
1293
1294 return 0;
1295
1296 irqerr:
1297 free_irq(isp[0].txirq, &isp[0]);
1298 free_irq(isp[0].rxirq, &isp[0]);
1299 free_irq(isp[0].errirq, &isp[0]);
1300 errout:
1301 kfree (isp);
1302 return (ret_val);
1303 }
1304
1305 void
1306 ifx_ssc_cleanup_module (void)
1307 {
1308 int i;
1309
1310 for (i = 0; i < PORT_CNT; i++) {
1311 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, isp[i].mapbase + IFX_SSC_WHBSTATE);
1312 free_irq(isp[i].txirq, &isp[i]);
1313 free_irq(isp[i].rxirq, &isp[i]);
1314 free_irq(isp[i].errirq, &isp[i]);
1315 }
1316 kfree (isp);
1317 }
1318
1319 module_init(ifx_ssc_init);
1320 module_exit(ifx_ssc_cleanup_module);
1321
1322
1323 inline int
1324 ifx_ssc_cs_low (u32 pin)
1325 {
1326 int ret = 0;
1327 if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
1328 printk ("clear CS %d fails\n", pin);
1329 wmb ();
1330
1331 return ret;
1332 }
1333 EXPORT_SYMBOL(ifx_ssc_cs_low);
1334
1335 inline int
1336 ifx_ssc_cs_high (u32 pin)
1337 {
1338 int ret = 0;
1339 if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
1340 printk ("set CS %d fails\n", pin);
1341 wmb ();
1342
1343 return ret;
1344 }
1345 EXPORT_SYMBOL(ifx_ssc_cs_high);
1346
1347 static int
1348 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1349 {
1350 int ret = 0;
1351
1352 char *ssc_tx_buf = NULL;
1353 char *ssc_rx_buf = NULL;
1354 int eff_size = 0;
1355 u8 mode = 0;
1356
1357 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1358 printk ("invalid parameters\n");
1359 ret = -EINVAL;
1360 goto ssc_session_exit;
1361 }
1362 else if (tx_buf == NULL || tx_len == 0) {
1363 if (rx_buf != NULL && rx_len != 0) {
1364 mode = IFX_SSC_MODE_RX;
1365 }
1366 else {
1367 printk ("invalid parameters\n");
1368 ret = -EINVAL;
1369 goto ssc_session_exit;
1370 }
1371 }
1372 else if (rx_buf == NULL || rx_len == 0) {
1373 if (tx_buf != NULL && tx_len != 0) {
1374 mode = IFX_SSC_MODE_TX;
1375 }
1376 else {
1377 printk ("invalid parameters\n");
1378 ret = -EINVAL;
1379 goto ssc_session_exit;
1380 }
1381 }
1382 else {
1383 mode = IFX_SSC_MODE_RXTX;
1384 }
1385
1386 if (mode == IFX_SSC_MODE_RXTX) {
1387 eff_size = tx_len + rx_len;
1388 }
1389 else if (mode == IFX_SSC_MODE_RX) {
1390 eff_size = rx_len;
1391 }
1392 else {
1393 eff_size = tx_len;
1394 }
1395
1396 //4 bytes alignment, required by driver
1397 /* change by TaiCheng */
1398 //if (in_irq()){
1399 if (1) {
1400 ssc_tx_buf =
1401 (char *) kmalloc (sizeof (char) *
1402 ((eff_size + 3) & (~3)),
1403 GFP_ATOMIC);
1404 ssc_rx_buf =
1405 (char *) kmalloc (sizeof (char) *
1406 ((eff_size + 3) & (~3)),
1407 GFP_ATOMIC);
1408 }
1409 else {
1410 ssc_tx_buf =
1411 (char *) kmalloc (sizeof (char) *
1412 ((eff_size + 3) & (~3)),
1413 GFP_KERNEL);
1414 ssc_rx_buf =
1415 (char *) kmalloc (sizeof (char) *
1416 ((eff_size + 3) & (~3)),
1417 GFP_KERNEL);
1418 }
1419 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1420 printk ("no memory for size of %d\n", eff_size);
1421 ret = -ENOMEM;
1422 goto ssc_session_exit;
1423 }
1424 memset ((void *) ssc_tx_buf, 0, eff_size);
1425 memset ((void *) ssc_rx_buf, 0, eff_size);
1426
1427 if (tx_len > 0) {
1428 memcpy (ssc_tx_buf, tx_buf, tx_len);
1429 }
1430
1431 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
1432
1433 if (ret > 0) {
1434 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
1435 }
1436
1437 if (ret != eff_size) {
1438 printk ("ifx_ssc_write return %d\n", ret);
1439 goto ssc_session_exit;
1440 }
1441 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
1442 if (ret != eff_size) {
1443 printk ("ifx_ssc_read return %d\n", ret);
1444 goto ssc_session_exit;
1445 }
1446
1447 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
1448
1449 if (mode == IFX_SSC_MODE_TX) {
1450 ret = tx_len;
1451 }
1452 else {
1453 ret = rx_len;
1454 }
1455 ssc_session_exit:
1456
1457 if (ssc_tx_buf != NULL)
1458 kfree (ssc_tx_buf);
1459 if (ssc_rx_buf != NULL)
1460 kfree (ssc_rx_buf);
1461
1462 if (ret < 0) {
1463 printk ("ssc session fails\n");
1464 }
1465 return ret;
1466 }
1467
1468 int
1469 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1470 {
1471 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1472 }
1473 EXPORT_SYMBOL(ifx_ssc_txrx);
1474
1475 int
1476 ifx_ssc_tx (char *tx_buf, u32 tx_len)
1477 {
1478 return ssc_session(tx_buf, tx_len, NULL, 0);
1479 }
1480 EXPORT_SYMBOL(ifx_ssc_tx);
1481
1482 int
1483 ifx_ssc_rx (char *rx_buf, u32 rx_len)
1484 {
1485 return ssc_session(NULL, 0, rx_buf, rx_len);
1486 }
1487 EXPORT_SYMBOL(ifx_ssc_rx);
1488
1489 MODULE_LICENSE("GPL");
1490 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1491 MODULE_DESCRIPTION("ifxmips ssc driver");
1492
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