target/linux/xburst/patches-2.6.34/052-rtc.patch

   1 From 9241770134d9bea522051622c52a3195a3d218e0 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:12:37 +0200
   4 Subject: [PATCH] Add jz4740 rtc driver
   5
   6 ---
   7  drivers/rtc/Kconfig      |   11 ++
   8  drivers/rtc/Makefile     |    1 +
   9  drivers/rtc/rtc-jz4740.c |  344 ++++++++++++++++++++++++++++++++++++++++++++++
  10  3 files changed, 356 insertions(+), 0 deletions(-)
  11  create mode 100644 drivers/rtc/rtc-jz4740.c
  12
  13 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
  14 index 6a13037..74699dd 100644
  15 --- a/drivers/rtc/Kconfig
  16 +++ b/drivers/rtc/Kconfig
  17 @@ -488,6 +488,17 @@ config RTC_DRV_EFI
  18           This driver can also be built as a module. If so, the module
  19           will be called rtc-efi.
  20
  21 +config RTC_DRV_JZ4740
  22 +       tristate "Ingenic JZ4720/JZ4740 SoC"
  23 +       depends on RTC_CLASS
  24 +       depends on SOC_JZ4740
  25 +       help
  26 +         If you say yes here you get support for the
  27 +         Ingenic JZ4720/JZ4740 SoC RTC controller.
  28 +
  29 +         This driver can also be buillt as a module. If so, the module
  30 +         will be called rtc-jz4740.
  31 +
  32  config RTC_DRV_STK17TA8
  33         tristate "Simtek STK17TA8"
  34         depends on RTC_CLASS
  35 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
  36 index 44ef194..7002033 100644
  37 --- a/drivers/rtc/Makefile
  38 +++ b/drivers/rtc/Makefile
  39 @@ -45,6 +45,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX)  += rtc-ep93xx.o
  40  obj-$(CONFIG_RTC_DRV_FM3130)   += rtc-fm3130.o
  41  obj-$(CONFIG_RTC_DRV_GENERIC)  += rtc-generic.o
  42  obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
  43 +obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
  44  obj-$(CONFIG_RTC_DRV_M41T80)   += rtc-m41t80.o
  45  obj-$(CONFIG_RTC_DRV_M41T94)   += rtc-m41t94.o
  46  obj-$(CONFIG_RTC_DRV_M48T35)   += rtc-m48t35.o
  47 diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
  48 new file mode 100644
  49 index 0000000..aac905a
  50 --- /dev/null
  51 +++ b/drivers/rtc/rtc-jz4740.c
  52 @@ -0,0 +1,344 @@
  53 +/*
  54 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  55 + *             JZ4720/JZ4740 SoC RTC driver
  56 + *
  57 + *  This program is free software; you can redistribute         it and/or modify it
  58 + *  under  the terms of         the GNU General  Public License as published by the
  59 + *  Free Software Foundation;  either version 2 of the License, or (at your
  60 + *  option) any later version.
  61 + *
  62 + *  You should have received a copy of the  GNU General Public License along
  63 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  64 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  65 + *
  66 + */
  67 +
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +#include <linux/platform_device.h>
  71 +#include <linux/rtc.h>
  72 +#include <linux/slab.h>
  73 +#include <linux/spinlock.h>
  74 +
  75 +#define JZ_REG_RTC_CTRL                0x00
  76 +#define JZ_REG_RTC_SEC         0x04
  77 +#define JZ_REG_RTC_SEC_ALARM   0x08
  78 +#define JZ_REG_RTC_REGULATOR   0x0C
  79 +#define JZ_REG_RTC_HIBERNATE   0x20
  80 +#define JZ_REG_RTC_SCRATCHPAD  0x34
  81 +
  82 +#define JZ_RTC_CTRL_WRDY       BIT(7)
  83 +#define JZ_RTC_CTRL_1HZ                BIT(6)
  84 +#define JZ_RTC_CTRL_1HZ_IRQ    BIT(5)
  85 +#define JZ_RTC_CTRL_AF         BIT(4)
  86 +#define JZ_RTC_CTRL_AF_IRQ     BIT(3)
  87 +#define JZ_RTC_CTRL_AE         BIT(2)
  88 +#define JZ_RTC_CTRL_ENABLE     BIT(0)
  89 +
  90 +struct jz4740_rtc {
  91 +       struct resource *mem;
  92 +       void __iomem *base;
  93 +
  94 +       struct rtc_device *rtc;
  95 +
  96 +       unsigned int irq;
  97 +
  98 +       spinlock_t lock;
  99 +};
 100 +
 101 +static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
 102 +{
 103 +       return readl(rtc->base + reg);
 104 +}
 105 +
 106 +static inline void jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
 107 +{
 108 +       uint32_t ctrl;
 109 +       do {
 110 +               ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 111 +       } while (!(ctrl & JZ_RTC_CTRL_WRDY));
 112 +}
 113 +
 114 +
 115 +static inline void jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 116 +                                       uint32_t val)
 117 +{
 118 +       jz4740_rtc_wait_write_ready(rtc);
 119 +       writel(val, rtc->base + reg);
 120 +}
 121 +
 122 +static void jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 123 +                                       uint32_t val)
 124 +{
 125 +       unsigned long flags;
 126 +       uint32_t ctrl;
 127 +
 128 +       spin_lock_irqsave(&rtc->lock, flags);
 129 +
 130 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 131 +
 132 +       /* Don't clear interrupt flags by accident */
 133 +       ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 134 +
 135 +       ctrl &= ~mask;
 136 +       ctrl |= val;
 137 +
 138 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 139 +
 140 +       spin_unlock_irqrestore(&rtc->lock, flags);
 141 +}
 142 +
 143 +static inline struct jz4740_rtc *dev_to_rtc(struct device *dev)
 144 +{
 145 +       return dev_get_drvdata(dev);
 146 +}
 147 +
 148 +static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 149 +{
 150 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 151 +       uint32_t secs, secs2;
 152 +
 153 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 154 +       secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 155 +
 156 +       while (secs != secs2) {
 157 +               secs = secs2;
 158 +               secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 159 +       }
 160 +
 161 +       rtc_time_to_tm(secs, time);
 162 +
 163 +       return rtc_valid_tm(time);
 164 +}
 165 +
 166 +static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
 167 +{
 168 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 169 +
 170 +       if ((uint32_t)secs != secs)
 171 +               return -EINVAL;
 172 +
 173 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
 174 +
 175 +       return 0;
 176 +}
 177 +
 178 +static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 179 +{
 180 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 181 +       uint32_t secs, secs2;
 182 +       uint32_t ctrl;
 183 +
 184 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 185 +       secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 186 +
 187 +       while (secs != secs2) {
 188 +               secs = secs2;
 189 +               secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 190 +       }
 191 +
 192 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 193 +
 194 +       alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 195 +       alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 196 +
 197 +       rtc_time_to_tm(secs, &alrm->time);
 198 +
 199 +       return rtc_valid_tm(&alrm->time);
 200 +}
 201 +
 202 +static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 203 +{
 204 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 205 +       unsigned long secs;
 206 +
 207 +       rtc_tm_to_time(&alrm->time, &secs);
 208 +
 209 +       if ((uint32_t)secs != secs)
 210 +               return -EINVAL;
 211 +
 212 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, (uint32_t)secs);
 213 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE,
 214 +                                       alrm->enabled ? JZ_RTC_CTRL_AE : 0);
 215 +
 216 +       return 0;
 217 +}
 218 +
 219 +static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
 220 +{
 221 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 222 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ,
 223 +                                       enable ? JZ_RTC_CTRL_1HZ_IRQ : 0);
 224 +       return 0;
 225 +}
 226 +
 227 +
 228 +static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 229 +{
 230 +       struct jz4740_rtc *rtc = dev_to_rtc(dev);
 231 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ,
 232 +                                       enable ? JZ_RTC_CTRL_AF_IRQ : 0);
 233 +       return 0;
 234 +}
 235 +
 236 +static struct rtc_class_ops jz4740_rtc_ops = {
 237 +       .read_time      = jz4740_rtc_read_time,
 238 +       .set_mmss       = jz4740_rtc_set_mmss,
 239 +       .read_alarm     = jz4740_rtc_read_alarm,
 240 +       .set_alarm      = jz4740_rtc_set_alarm,
 241 +       .update_irq_enable = jz4740_rtc_update_irq_enable,
 242 +       .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 243 +};
 244 +
 245 +static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 246 +{
 247 +       struct jz4740_rtc *rtc = data;
 248 +       uint32_t ctrl;
 249 +       unsigned long events = 0;
 250 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 251 +
 252 +       if (ctrl & JZ_RTC_CTRL_1HZ)
 253 +               events |= (RTC_UF | RTC_IRQF);
 254 +
 255 +       if (ctrl & JZ_RTC_CTRL_AF)
 256 +               events |= (RTC_AF | RTC_IRQF);
 257 +
 258 +       rtc_update_irq(rtc->rtc, 1, events);
 259 +
 260 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, 0);
 261 +
 262 +       return IRQ_HANDLED;
 263 +}
 264 +
 265 +void jz4740_rtc_poweroff(struct device *dev)
 266 +{
 267 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 268 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 269 +}
 270 +EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
 271 +
 272 +static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
 273 +{
 274 +       int ret;
 275 +       struct jz4740_rtc *rtc;
 276 +       uint32_t scratchpad;
 277 +
 278 +       rtc = kmalloc(sizeof(*rtc), GFP_KERNEL);
 279 +
 280 +       rtc->irq = platform_get_irq(pdev, 0);
 281 +
 282 +       if (rtc->irq < 0) {
 283 +               ret = -ENOENT;
 284 +               dev_err(&pdev->dev, "Failed to get platform irq\n");
 285 +               goto err_free;
 286 +       }
 287 +
 288 +       rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 289 +       if (!rtc->mem) {
 290 +               ret = -ENOENT;
 291 +               dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
 292 +               goto err_free;
 293 +       }
 294 +
 295 +       rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
 296 +                                       pdev->name);
 297 +
 298 +       if (!rtc->mem) {
 299 +               ret = -EBUSY;
 300 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 301 +               goto err_free;
 302 +       }
 303 +
 304 +       rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
 305 +
 306 +       if (!rtc->base) {
 307 +               ret = -EBUSY;
 308 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 309 +               goto err_release_mem_region;
 310 +       }
 311 +
 312 +       spin_lock_init(&rtc->lock);
 313 +
 314 +       platform_set_drvdata(pdev, rtc);
 315 +
 316 +       rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
 317 +                                       THIS_MODULE);
 318 +
 319 +       if (IS_ERR(rtc->rtc)) {
 320 +               ret = PTR_ERR(rtc->rtc);
 321 +               dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
 322 +               goto err_iounmap;
 323 +       }
 324 +
 325 +       ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
 326 +                               pdev->name, rtc);
 327 +
 328 +       if (ret) {
 329 +               dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 330 +               goto err_unregister_rtc;
 331 +       }
 332 +
 333 +       scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
 334 +       if (scratchpad != 0x12345678) {
 335 +               jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 336 +               jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
 337 +       }
 338 +
 339 +       return 0;
 340 +
 341 +err_unregister_rtc:
 342 +       rtc_device_unregister(rtc->rtc);
 343 +err_iounmap:
 344 +       platform_set_drvdata(pdev, NULL);
 345 +       iounmap(rtc->base);
 346 +err_release_mem_region:
 347 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 348 +err_free:
 349 +       kfree(rtc);
 350 +
 351 +       return ret;
 352 +}
 353 +
 354 +static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
 355 +{
 356 +       struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
 357 +
 358 +       free_irq(rtc->irq, rtc);
 359 +
 360 +       rtc_device_unregister(rtc->rtc);
 361 +
 362 +       iounmap(rtc->base);
 363 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 364 +
 365 +       kfree(rtc);
 366 +
 367 +       platform_set_drvdata(pdev, NULL);
 368 +
 369 +       return 0;
 370 +}
 371 +
 372 +struct platform_driver jz4740_rtc_driver = {
 373 +       .probe = jz4740_rtc_probe,
 374 +       .remove = __devexit_p(jz4740_rtc_remove),
 375 +       .driver = {
 376 +               .name = "jz4740-rtc",
 377 +               .owner = THIS_MODULE,
 378 +       },
 379 +};
 380 +
 381 +static int __init jz4740_rtc_init(void)
 382 +{
 383 +       return platform_driver_register(&jz4740_rtc_driver);
 384 +}
 385 +module_init(jz4740_rtc_init);
 386 +
 387 +static void __exit jz4740_rtc_exit(void)
 388 +{
 389 +       platform_driver_unregister(&jz4740_rtc_driver);
 390 +}
 391 +module_exit(jz4740_rtc_exit);
 392 +
 393 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 394 +MODULE_LICENSE("GPL");
 395 +MODULE_DESCRIPTION("RTC driver for the JZ4720/JZ4740 SoC\n");
 396 +MODULE_ALIAS("platform:jz4740-rtc");
 397 --
 398 1.5.6.5
 399