target/linux/xburst/patches-2.6.34/061-asoc.patch

   1 From 6548719b6a1ce4e202d58625fbfb94e6c894ced9 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:35:07 +0200
   4 Subject: [PATCH] Add jz4740 SoC sound drivers
   5
   6 ---
   7  sound/soc/Kconfig             |    1 +
   8  sound/soc/Makefile            |    1 +
   9  sound/soc/jz4740/Kconfig      |   13 +
  10  sound/soc/jz4740/Makefile     |    9 +
  11  sound/soc/jz4740/jz4740-i2s.c |  572 +++++++++++++++++++++++++++++++++++++++++
  12  sound/soc/jz4740/jz4740-i2s.h |   18 ++
  13  sound/soc/jz4740/jz4740-pcm.c |  350 +++++++++++++++++++++++++
  14  sound/soc/jz4740/jz4740-pcm.h |   22 ++
  15  8 files changed, 986 insertions(+), 0 deletions(-)
  16  create mode 100644 sound/soc/jz4740/Kconfig
  17  create mode 100644 sound/soc/jz4740/Makefile
  18  create mode 100644 sound/soc/jz4740/jz4740-i2s.c
  19  create mode 100644 sound/soc/jz4740/jz4740-i2s.h
  20  create mode 100644 sound/soc/jz4740/jz4740-pcm.c
  21  create mode 100644 sound/soc/jz4740/jz4740-pcm.h
  22
  23 diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
  24 index b1749bc..5a7a724 100644
  25 --- a/sound/soc/Kconfig
  26 +++ b/sound/soc/Kconfig
  27 @@ -36,6 +36,7 @@ source "sound/soc/s3c24xx/Kconfig"
  28  source "sound/soc/s6000/Kconfig"
  29  source "sound/soc/sh/Kconfig"
  30  source "sound/soc/txx9/Kconfig"
  31 +source "sound/soc/jz4740/Kconfig"
  32
  33  # Supported codecs
  34  source "sound/soc/codecs/Kconfig"
  35 diff --git a/sound/soc/Makefile b/sound/soc/Makefile
  36 index 1470141..fdbe74d 100644
  37 --- a/sound/soc/Makefile
  38 +++ b/sound/soc/Makefile
  39 @@ -14,3 +14,4 @@ obj-$(CONFIG_SND_SOC) += s3c24xx/
  40  obj-$(CONFIG_SND_SOC)  += s6000/
  41  obj-$(CONFIG_SND_SOC)  += sh/
  42  obj-$(CONFIG_SND_SOC)  += txx9/
  43 +obj-$(CONFIG_SND_SOC)  += jz4740/
  44 diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig
  45 new file mode 100644
  46 index 0000000..39df949
  47 --- /dev/null
  48 +++ b/sound/soc/jz4740/Kconfig
  49 @@ -0,0 +1,13 @@
  50 +config SND_JZ4740_SOC
  51 +       tristate "SoC Audio for Ingenic JZ4740 SoC"
  52 +       depends on SOC_JZ4740 && SND_SOC
  53 +       help
  54 +         Say Y or M if you want to add support for codecs attached to
  55 +         the Jz4740 AC97, I2S or SSP interface. You will also need
  56 +         to select the audio interfaces to support below.
  57 +
  58 +config SND_JZ4740_SOC_I2S
  59 +       depends on SND_JZ4740_SOC
  60 +       tristate "SoC Audio (I2S protocol) for Ingenic jz4740 chip"
  61 +       help
  62 +         Say Y if you want to use I2S protocol and I2S codec on Ingenic Jz4740 QI_LB60 board.
  63 diff --git a/sound/soc/jz4740/Makefile b/sound/soc/jz4740/Makefile
  64 new file mode 100644
  65 index 0000000..1be8d19
  66 --- /dev/null
  67 +++ b/sound/soc/jz4740/Makefile
  68 @@ -0,0 +1,9 @@
  69 +#
  70 +# Jz4740 Platform Support
  71 +#
  72 +snd-soc-jz4740-objs := jz4740-pcm.o
  73 +snd-soc-jz4740-i2s-objs := jz4740-i2s.o
  74 +
  75 +obj-$(CONFIG_SND_JZ4740_SOC) += snd-soc-jz4740.o
  76 +obj-$(CONFIG_SND_JZ4740_SOC_I2S) += snd-soc-jz4740-i2s.o
  77 +
  78 diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
  79 new file mode 100644
  80 index 0000000..d3daa27
  81 --- /dev/null
  82 +++ b/sound/soc/jz4740/jz4740-i2s.c
  83 @@ -0,0 +1,572 @@
  84 +/*
  85 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  86 + *
  87 + *  This program is free software; you can redistribute         it and/or modify it
  88 + *  under  the terms of         the GNU General  Public License as published by the
  89 + *  Free Software Foundation;  either version 2 of the License, or (at your
  90 + *  option) any later version.
  91 + *
  92 + *  You should have received a copy of the  GNU General Public License along
  93 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  94 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  95 + *
  96 + */
  97 +
  98 +#include <linux/init.h>
  99 +#include <linux/io.h>
 100 +#include <linux/kernel.h>
 101 +#include <linux/module.h>
 102 +#include <linux/platform_device.h>
 103 +#include <linux/slab.h>
 104 +
 105 +#include <linux/clk.h>
 106 +#include <linux/delay.h>
 107 +
 108 +#include <linux/dma-mapping.h>
 109 +
 110 +#include <sound/core.h>
 111 +#include <sound/pcm.h>
 112 +#include <sound/pcm_params.h>
 113 +#include <sound/soc.h>
 114 +#include <sound/soc-dapm.h>
 115 +#include <sound/initval.h>
 116 +
 117 +#include "jz4740-i2s.h"
 118 +#include "jz4740-pcm.h"
 119 +
 120 +#define JZ_REG_AIC_CONF                0x00
 121 +#define JZ_REG_AIC_CTRL                0x04
 122 +#define JZ_REG_AIC_I2S_FMT     0x10
 123 +#define JZ_REG_AIC_FIFO_STATUS 0x14
 124 +#define JZ_REG_AIC_I2S_STATUS  0x1c
 125 +#define JZ_REG_AIC_CLK_DIV     0x30
 126 +#define JZ_REG_AIC_FIFO                0x34
 127 +
 128 +#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
 129 +#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
 130 +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
 131 +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
 132 +#define JZ_AIC_CONF_I2S BIT(4)
 133 +#define JZ_AIC_CONF_RESET BIT(3)
 134 +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
 135 +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
 136 +#define JZ_AIC_CONF_ENABLE BIT(0)
 137 +
 138 +#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
 139 +#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
 140 +
 141 +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
 142 +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
 143 +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
 144 +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
 145 +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
 146 +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
 147 +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
 148 +#define JZ_AIC_CTRL_FLUSH              BIT(8)
 149 +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
 150 +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
 151 +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
 152 +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
 153 +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
 154 +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
 155 +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
 156 +
 157 +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
 158 +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16
 159 +
 160 +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
 161 +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
 162 +#define JZ_AIC_I2S_FMT_MSB BIT(0)
 163 +
 164 +#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
 165 +
 166 +#define JZ_AIC_CLK_DIV_MASK 0xf
 167 +
 168 +struct jz4740_i2s {
 169 +       struct resource *mem;
 170 +       void __iomem *base;
 171 +       dma_addr_t phys_base;
 172 +
 173 +       struct clk *clk_aic;
 174 +       struct clk *clk_i2s;
 175 +
 176 +       struct jz4740_pcm_config capture_pcm_config;
 177 +       struct jz4740_pcm_config playback_pcm_config;
 178 +};
 179 +
 180 +static struct jz4740_dma_config jz4740_i2s_dma_playback_config = {
 181 +       .src_width = JZ4740_DMA_WIDTH_16BIT,
 182 +       .dst_width = JZ4740_DMA_WIDTH_32BIT,
 183 +       .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
 184 +       .request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
 185 +       .flags = JZ4740_DMA_SRC_AUTOINC,
 186 +       .mode = JZ4740_DMA_MODE_SINGLE,
 187 +};
 188 +
 189 +static struct jz4740_dma_config jz4740_i2s_dma_capture_config = {
 190 +       .src_width = JZ4740_DMA_WIDTH_32BIT,
 191 +       .dst_width = JZ4740_DMA_WIDTH_16BIT,
 192 +       .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
 193 +       .request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
 194 +       .flags = JZ4740_DMA_DST_AUTOINC,
 195 +       .mode = JZ4740_DMA_MODE_SINGLE,
 196 +};
 197 +
 198 +
 199 +static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
 200 +               unsigned int reg)
 201 +{
 202 +       return readl(i2s->base + reg);
 203 +}
 204 +
 205 +static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
 206 +               unsigned int reg, uint32_t value)
 207 +{
 208 +       writel(value, i2s->base + reg);
 209 +}
 210 +
 211 +static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
 212 +{
 213 +       return dai->private_data;
 214 +}
 215 +
 216 +static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
 217 +               struct snd_soc_dai *dai)
 218 +{
 219 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 220 +       uint32_t conf, ctrl;
 221 +
 222 +       if (dai->active)
 223 +               return 0;
 224 +
 225 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 226 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 227 +
 228 +       conf |= JZ_AIC_CONF_ENABLE;
 229 +       ctrl |= JZ_AIC_CTRL_FLUSH;
 230 +
 231 +
 232 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 233 +       clk_enable(i2s->clk_i2s);
 234 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 235 +
 236 +       return 0;
 237 +}
 238 +
 239 +static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct
 240 +                              snd_soc_dai *dai)
 241 +{
 242 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 243 +       uint32_t conf;
 244 +
 245 +       if (!dai->active)
 246 +               return;
 247 +
 248 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 249 +       conf &= ~JZ_AIC_CONF_ENABLE;
 250 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 251 +
 252 +       clk_disable(i2s->clk_i2s);
 253 +}
 254 +
 255 +
 256 +static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 257 +                              struct snd_soc_dai *dai)
 258 +{
 259 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 260 +       bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 261 +
 262 +       uint32_t ctrl;
 263 +       uint32_t mask;
 264 +
 265 +       if (playback) {
 266 +           mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
 267 +       } else {
 268 +           mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
 269 +       }
 270 +
 271 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 272 +
 273 +       switch (cmd) {
 274 +       case SNDRV_PCM_TRIGGER_START:
 275 +       case SNDRV_PCM_TRIGGER_RESUME:
 276 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 277 +           ctrl |= mask;
 278 +           break;
 279 +       case SNDRV_PCM_TRIGGER_STOP:
 280 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 281 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 282 +           ctrl &= ~mask;
 283 +           break;
 284 +       default:
 285 +           return -EINVAL;
 286 +       }
 287 +
 288 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 289 +
 290 +       return 0;
 291 +}
 292 +
 293 +
 294 +static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai,
 295 +                              unsigned int fmt)
 296 +{
 297 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 298 +
 299 +       uint32_t format = 0;
 300 +       uint32_t conf;
 301 +
 302 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 303 +
 304 +       conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
 305 +
 306 +       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 307 +       case SND_SOC_DAIFMT_CBS_CFS:
 308 +           conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
 309 +           format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
 310 +           break;
 311 +       case SND_SOC_DAIFMT_CBM_CFS:
 312 +           conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
 313 +           break;
 314 +       case SND_SOC_DAIFMT_CBS_CFM:
 315 +           conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
 316 +           break;
 317 +       case SND_SOC_DAIFMT_CBM_CFM:
 318 +           break;
 319 +       default:
 320 +           return -EINVAL;
 321 +       }
 322 +
 323 +       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 324 +       case SND_SOC_DAIFMT_MSB:
 325 +           format |= JZ_AIC_I2S_FMT_MSB;
 326 +           break;
 327 +       case SND_SOC_DAIFMT_I2S:
 328 +           break;
 329 +       default:
 330 +           return -EINVAL;
 331 +       }
 332 +
 333 +       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 334 +       case SND_SOC_DAIFMT_NB_NF:
 335 +           break;
 336 +       default:
 337 +           return -EINVAL;
 338 +       }
 339 +
 340 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 341 +       jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
 342 +
 343 +       return 0;
 344 +}
 345 +
 346 +static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
 347 +                                struct snd_pcm_hw_params *params,
 348 +                                struct snd_soc_dai *dai)
 349 +{
 350 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 351 +       bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 352 +       enum jz4740_dma_width dma_width;
 353 +       struct jz4740_pcm_config *pcm_config;
 354 +       unsigned int sample_size;
 355 +       uint32_t ctrl;
 356 +
 357 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 358 +
 359 +       switch (params_format(params)) {
 360 +       case SNDRV_PCM_FORMAT_S8:
 361 +           sample_size = 0;
 362 +               dma_width = JZ4740_DMA_WIDTH_8BIT;
 363 +           break;
 364 +       case SNDRV_PCM_FORMAT_S16:
 365 +           sample_size = 1;
 366 +               dma_width = JZ4740_DMA_WIDTH_16BIT;
 367 +               break;
 368 +       default:
 369 +               return -EINVAL;
 370 +       }
 371 +
 372 +       if (playback) {
 373 +               ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
 374 +               ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
 375 +       } else {
 376 +               ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
 377 +               ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
 378 +       }
 379 +
 380 +       switch (params_channels(params)) {
 381 +       case 2:
 382 +           break;
 383 +       case 1:
 384 +               if (playback) {
 385 +                       ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
 386 +                       break;
 387 +               }
 388 +       default: /* Falltrough */
 389 +               return -EINVAL;
 390 +       }
 391 +
 392 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 393 +
 394 +       if (playback) {
 395 +               jz4740_i2s_dma_playback_config.src_width = dma_width;
 396 +               pcm_config = &i2s->playback_pcm_config;
 397 +               pcm_config->dma_config = &jz4740_i2s_dma_playback_config;
 398 +       } else {
 399 +               jz4740_i2s_dma_capture_config.dst_width = dma_width;
 400 +               pcm_config = &i2s->capture_pcm_config;
 401 +               pcm_config->dma_config = &jz4740_i2s_dma_capture_config;
 402 +       }
 403 +       pcm_config->fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
 404 +
 405 +       snd_soc_dai_set_dma_data(dai, substream, pcm_config);
 406 +
 407 +       return 0;
 408 +}
 409 +
 410 +static int jz4740_i2s_set_clkdiv(struct snd_soc_dai *dai,
 411 +                                 int div_id, int div)
 412 +{
 413 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 414 +
 415 +       switch (div_id) {
 416 +       case JZ4740_I2S_BIT_CLK:
 417 +               if (div & 1 || div > 16)
 418 +                       return -EINVAL;
 419 +               jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div - 1);
 420 +               break;
 421 +       default:
 422 +               return -EINVAL;
 423 +       }
 424 +
 425 +       return 0;
 426 +}
 427 +
 428 +static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 429 +                                 unsigned int freq, int dir)
 430 +{
 431 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 432 +       int ret = 0;
 433 +       struct clk *parent;
 434 +
 435 +       switch (clk_id) {
 436 +       case JZ4740_I2S_CLKSRC_EXT:
 437 +               parent = clk_get(NULL, "ext");
 438 +               clk_set_parent(i2s->clk_i2s, parent);
 439 +               break;
 440 +       case JZ4740_I2S_CLKSRC_PLL:
 441 +               parent = clk_get(NULL, "pll half");
 442 +               clk_set_parent(i2s->clk_i2s, parent);
 443 +               ret = clk_set_rate(i2s->clk_i2s, freq);
 444 +               break;
 445 +       default:
 446 +               return -EINVAL;
 447 +       }
 448 +       clk_put(parent);
 449 +
 450 +       return ret;
 451 +}
 452 +
 453 +static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
 454 +{
 455 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 456 +       uint32_t conf;
 457 +
 458 +       if (dai->active) {
 459 +               conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 460 +               conf &= ~JZ_AIC_CONF_ENABLE;
 461 +               jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 462 +
 463 +               clk_disable(i2s->clk_i2s);
 464 +       }
 465 +
 466 +       clk_disable(i2s->clk_aic);
 467 +
 468 +       return 0;
 469 +}
 470 +
 471 +static int jz4740_i2s_resume(struct snd_soc_dai *dai)
 472 +{
 473 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 474 +       uint32_t conf;
 475 +
 476 +       clk_enable(i2s->clk_aic);
 477 +
 478 +       if (dai->active) {
 479 +               clk_enable(i2s->clk_i2s);
 480 +
 481 +               conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 482 +               conf |= JZ_AIC_CONF_ENABLE;
 483 +               jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 484 +
 485 +       }
 486 +
 487 +       return 0;
 488 +}
 489 +
 490 +static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
 491 +{
 492 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 493 +       uint32_t conf;
 494 +
 495 +       conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
 496 +               (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
 497 +               JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
 498 +               JZ_AIC_CONF_I2S |
 499 +               JZ_AIC_CONF_INTERNAL_CODEC;
 500 +
 501 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
 502 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 503 +
 504 +       return 0;
 505 +}
 506 +
 507 +
 508 +static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
 509 +       .startup = jz4740_i2s_startup,
 510 +       .shutdown = jz4740_i2s_shutdown,
 511 +       .trigger = jz4740_i2s_trigger,
 512 +       .hw_params = jz4740_i2s_hw_params,
 513 +       .set_fmt = jz4740_i2s_set_fmt,
 514 +       .set_clkdiv = jz4740_i2s_set_clkdiv,
 515 +       .set_sysclk = jz4740_i2s_set_sysclk,
 516 +};
 517 +
 518 +#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 519 +               SNDRV_PCM_FMTBIT_S16_LE)
 520 +
 521 +struct snd_soc_dai jz4740_i2s_dai = {
 522 +       .name = "jz4740-i2s",
 523 +       .probe = jz4740_i2s_probe,
 524 +       .playback = {
 525 +               .channels_min = 1,
 526 +               .channels_max = 2,
 527 +               .rates = SNDRV_PCM_RATE_8000_44100,
 528 +               .formats = JZ4740_I2S_FMTS,
 529 +       },
 530 +       .capture = {
 531 +               .channels_min = 2,
 532 +               .channels_max = 2,
 533 +               .rates = SNDRV_PCM_RATE_8000_44100,
 534 +               .formats = JZ4740_I2S_FMTS,
 535 +       },
 536 +       .symmetric_rates = 1,
 537 +       .ops = &jz4740_i2s_dai_ops,
 538 +       .suspend = jz4740_i2s_suspend,
 539 +       .resume = jz4740_i2s_resume,
 540 +};
 541 +EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
 542 +
 543 +static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
 544 +{
 545 +       struct jz4740_i2s *i2s;
 546 +       int ret;
 547 +
 548 +       i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
 549 +
 550 +       if (!i2s)
 551 +               return -ENOMEM;
 552 +
 553 +       i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 554 +
 555 +       if (!i2s->mem) {
 556 +               ret = -ENOENT;
 557 +               goto err_free;
 558 +       }
 559 +
 560 +       i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
 561 +                               pdev->name);
 562 +
 563 +       if (!i2s->mem) {
 564 +               ret = -EBUSY;
 565 +               goto err_free;
 566 +       }
 567 +
 568 +       i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
 569 +
 570 +       if (!i2s->base) {
 571 +               ret = -EBUSY;
 572 +               goto err_release_mem_region;
 573 +       }
 574 +
 575 +       i2s->phys_base = i2s->mem->start;
 576 +
 577 +       jz4740_i2s_dai.private_data = i2s;
 578 +
 579 +       ret = snd_soc_register_dai(&jz4740_i2s_dai);
 580 +
 581 +       i2s->clk_aic = clk_get(&pdev->dev, "aic");
 582 +
 583 +       if (IS_ERR(i2s->clk_aic)) {
 584 +               ret = PTR_ERR(i2s->clk_aic);
 585 +               goto err_iounmap;
 586 +       }
 587 +
 588 +
 589 +       i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
 590 +
 591 +       if (IS_ERR(i2s->clk_i2s)) {
 592 +               ret = PTR_ERR(i2s->clk_i2s);
 593 +               goto err_iounmap;
 594 +       }
 595 +
 596 +       clk_enable(i2s->clk_aic);
 597 +
 598 +       platform_set_drvdata(pdev, i2s);
 599 +
 600 +       return 0;
 601 +
 602 +err_iounmap:
 603 +       iounmap(i2s->base);
 604 +err_release_mem_region:
 605 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 606 +err_free:
 607 +       kfree(i2s);
 608 +
 609 +       return ret;
 610 +}
 611 +
 612 +static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
 613 +{
 614 +       struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
 615 +
 616 +       snd_soc_unregister_dai(&jz4740_i2s_dai);
 617 +
 618 +       clk_disable(i2s->clk_aic);
 619 +       clk_put(i2s->clk_i2s);
 620 +       clk_put(i2s->clk_aic);
 621 +
 622 +       iounmap(i2s->base);
 623 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 624 +
 625 +       platform_set_drvdata(pdev, NULL);
 626 +       kfree(i2s);
 627 +
 628 +       return 0;
 629 +}
 630 +
 631 +static struct platform_driver jz4740_i2s_driver = {
 632 +       .probe = jz4740_i2s_dev_probe,
 633 +       .remove = __devexit_p(jz4740_i2s_dev_remove),
 634 +       .driver = {
 635 +               .name = "jz4740-i2s",
 636 +               .owner = THIS_MODULE,
 637 +       },
 638 +};
 639 +
 640 +static int __init jz4740_i2s_init(void)
 641 +{
 642 +       return platform_driver_register(&jz4740_i2s_driver);
 643 +}
 644 +module_init(jz4740_i2s_init);
 645 +
 646 +static void __exit jz4740_i2s_exit(void)
 647 +{
 648 +       platform_driver_unregister(&jz4740_i2s_driver);
 649 +}
 650 +module_exit(jz4740_i2s_exit);
 651 +
 652 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 653 +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 654 +MODULE_LICENSE("GPL");
 655 +MODULE_ALIAS("platform:jz4740-i2s");
 656 diff --git a/sound/soc/jz4740/jz4740-i2s.h b/sound/soc/jz4740/jz4740-i2s.h
 657 new file mode 100644
 658 index 0000000..da22ed8
 659 --- /dev/null
 660 +++ b/sound/soc/jz4740/jz4740-i2s.h
 661 @@ -0,0 +1,18 @@
 662 +/*
 663 + * This program is free software; you can redistribute it and/or modify
 664 + * it under the terms of the GNU General Public License version 2 as
 665 + * published by the Free Software Foundation.
 666 + */
 667 +
 668 +#ifndef _JZ4740_I2S_H
 669 +#define _JZ4740_I2S_H
 670 +
 671 +/* I2S clock source */
 672 +#define JZ4740_I2S_CLKSRC_EXT 0
 673 +#define JZ4740_I2S_CLKSRC_PLL 1
 674 +
 675 +#define JZ4740_I2S_BIT_CLK             0
 676 +
 677 +extern struct snd_soc_dai jz4740_i2s_dai;
 678 +
 679 +#endif
 680 diff --git a/sound/soc/jz4740/jz4740-pcm.c b/sound/soc/jz4740/jz4740-pcm.c
 681 new file mode 100644
 682 index 0000000..e55ffbf
 683 --- /dev/null
 684 +++ b/sound/soc/jz4740/jz4740-pcm.c
 685 @@ -0,0 +1,350 @@
 686 +/*
 687 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 688 + *
 689 + *  This program is free software; you can redistribute         it and/or modify it
 690 + *  under  the terms of         the GNU General  Public License as published by the
 691 + *  Free Software Foundation;  either version 2 of the License, or (at your
 692 + *  option) any later version.
 693 + *
 694 + *  You should have received a copy of the  GNU General Public License along
 695 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 696 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 697 + *
 698 + */
 699 +
 700 +#include <linux/init.h>
 701 +#include <linux/interrupt.h>
 702 +#include <linux/kernel.h>
 703 +#include <linux/module.h>
 704 +#include <linux/slab.h>
 705 +
 706 +#include <linux/dma-mapping.h>
 707 +
 708 +#include <sound/core.h>
 709 +#include <sound/pcm.h>
 710 +#include <sound/pcm_params.h>
 711 +#include <sound/soc.h>
 712 +
 713 +#include <asm/mach-jz4740/dma.h>
 714 +#include "jz4740-pcm.h"
 715 +
 716 +struct jz4740_runtime_data {
 717 +       unsigned int dma_period;
 718 +       dma_addr_t dma_start;
 719 +       dma_addr_t dma_pos;
 720 +       dma_addr_t dma_end;
 721 +
 722 +       struct jz4740_dma_chan *dma;
 723 +
 724 +       dma_addr_t fifo_addr;
 725 +};
 726 +
 727 +/* identify hardware playback capabilities */
 728 +static const struct snd_pcm_hardware jz4740_pcm_hardware = {
 729 +       .info = SNDRV_PCM_INFO_MMAP |
 730 +               SNDRV_PCM_INFO_MMAP_VALID |
 731 +               SNDRV_PCM_INFO_INTERLEAVED |
 732 +               SNDRV_PCM_INFO_BLOCK_TRANSFER,
 733 +       .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
 734 +
 735 +       .rates                  = SNDRV_PCM_RATE_8000_48000,
 736 +       .channels_min           = 1,
 737 +       .channels_max           = 2,
 738 +       .period_bytes_min       = 32,
 739 +       .period_bytes_max       = 2 * PAGE_SIZE,
 740 +       .periods_min            = 2,
 741 +       .periods_max            = 128,
 742 +       .buffer_bytes_max       = 128 * 2 * PAGE_SIZE,
 743 +       .fifo_size              = 32,
 744 +};
 745 +
 746 +static void jz4740_pcm_start_transfer(struct jz4740_runtime_data *prtd, int stream)
 747 +{
 748 +       unsigned int count;
 749 +
 750 +       if (prtd->dma_pos + prtd->dma_period > prtd->dma_end)
 751 +               count = prtd->dma_end - prtd->dma_pos;
 752 +       else
 753 +               count = prtd->dma_period;
 754 +
 755 +       jz4740_dma_disable(prtd->dma);
 756 +
 757 +       if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 758 +               jz4740_dma_set_src_addr(prtd->dma, prtd->dma_pos);
 759 +               jz4740_dma_set_dst_addr(prtd->dma, prtd->fifo_addr);
 760 +       } else {
 761 +               jz4740_dma_set_src_addr(prtd->dma, prtd->fifo_addr);
 762 +               jz4740_dma_set_dst_addr(prtd->dma, prtd->dma_pos);
 763 +       }
 764 +
 765 +       jz4740_dma_set_transfer_count(prtd->dma, count);
 766 +
 767 +       jz4740_dma_enable(prtd->dma);
 768 +
 769 +       prtd->dma_pos += prtd->dma_period;
 770 +       if (prtd->dma_pos >= prtd->dma_end)
 771 +               prtd->dma_pos = prtd->dma_start;
 772 +}
 773 +
 774 +static void jz4740_pcm_dma_transfer_done(struct jz4740_dma_chan *dma, int err,
 775 +       void *dev_id)
 776 +{
 777 +       struct snd_pcm_substream *substream = dev_id;
 778 +       struct snd_pcm_runtime *runtime = substream->runtime;
 779 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 780 +
 781 +       snd_pcm_period_elapsed(substream);
 782 +
 783 +       jz4740_pcm_start_transfer(prtd, substream->stream);
 784 +}
 785 +
 786 +static int jz4740_pcm_hw_params(struct snd_pcm_substream *substream,
 787 +       struct snd_pcm_hw_params *params)
 788 +{
 789 +       struct snd_pcm_runtime *runtime = substream->runtime;
 790 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 791 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 792 +       struct jz4740_pcm_config *config;
 793 +
 794 +       config = snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
 795 +       if (!prtd->dma) {
 796 +               const char *dma_channel_name;
 797 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 798 +                       dma_channel_name = "PCM Playback";
 799 +               else
 800 +                       dma_channel_name = "PCM Capture";
 801 +
 802 +               prtd->dma = jz4740_dma_request(substream, dma_channel_name);
 803 +       }
 804 +
 805 +       if (!prtd->dma)
 806 +               return -EBUSY;
 807 +
 808 +       jz4740_dma_configure(prtd->dma, config->dma_config);
 809 +       prtd->fifo_addr = config->fifo_addr;
 810 +
 811 +       jz4740_dma_set_complete_cb(prtd->dma, jz4740_pcm_dma_transfer_done);
 812 +
 813 +       snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
 814 +       runtime->dma_bytes = params_buffer_bytes(params);
 815 +
 816 +       prtd->dma_period = params_period_bytes(params);
 817 +       prtd->dma_start = runtime->dma_addr;
 818 +       prtd->dma_pos = prtd->dma_start;
 819 +       prtd->dma_end = prtd->dma_start + runtime->dma_bytes;
 820 +
 821 +       return 0;
 822 +}
 823 +
 824 +static int jz4740_pcm_hw_free(struct snd_pcm_substream *substream)
 825 +{
 826 +       struct jz4740_runtime_data *prtd = substream->runtime->private_data;
 827 +
 828 +       snd_pcm_set_runtime_buffer(substream, NULL);
 829 +       if (prtd->dma) {
 830 +               jz4740_dma_free(prtd->dma);
 831 +               prtd->dma = NULL;
 832 +       }
 833 +
 834 +       return 0;
 835 +}
 836 +
 837 +static int jz4740_pcm_prepare(struct snd_pcm_substream *substream)
 838 +{
 839 +       struct jz4740_runtime_data *prtd = substream->runtime->private_data;
 840 +       int ret = 0;
 841 +
 842 +       if (!prtd->dma)
 843 +                       return 0;
 844 +
 845 +       prtd->dma_pos = prtd->dma_start;
 846 +
 847 +       return ret;
 848 +}
 849 +
 850 +static int jz4740_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 851 +{
 852 +       struct snd_pcm_runtime *runtime = substream->runtime;
 853 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 854 +
 855 +       int ret = 0;
 856 +
 857 +       switch (cmd) {
 858 +       case SNDRV_PCM_TRIGGER_START:
 859 +       case SNDRV_PCM_TRIGGER_RESUME:
 860 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 861 +               jz4740_pcm_start_transfer(prtd, substream->stream);
 862 +               break;
 863 +       case SNDRV_PCM_TRIGGER_STOP:
 864 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 865 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 866 +               jz4740_dma_disable(prtd->dma);
 867 +               break;
 868 +       default:
 869 +               ret = -EINVAL;
 870 +       }
 871 +
 872 +       return ret;
 873 +}
 874 +
 875 +static snd_pcm_uframes_t jz4740_pcm_pointer(struct snd_pcm_substream *substream)
 876 +{
 877 +       struct snd_pcm_runtime *runtime = substream->runtime;
 878 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 879 +       unsigned long count, pos;
 880 +       snd_pcm_uframes_t offset;
 881 +       struct jz4740_dma_chan *dma = prtd->dma;
 882 +
 883 +       count = jz4740_dma_get_residue(dma);
 884 +       if (prtd->dma_pos == prtd->dma_start)
 885 +               pos = prtd->dma_end - prtd->dma_start - count;
 886 +       else
 887 +               pos = prtd->dma_pos - prtd->dma_start - count;
 888 +
 889 +       offset = bytes_to_frames(runtime, pos);
 890 +       if (offset >= runtime->buffer_size)
 891 +               offset = 0;
 892 +
 893 +       return offset;
 894 +}
 895 +
 896 +static int jz4740_pcm_open(struct snd_pcm_substream *substream)
 897 +{
 898 +       struct snd_pcm_runtime *runtime = substream->runtime;
 899 +       struct jz4740_runtime_data *prtd;
 900 +
 901 +       snd_soc_set_runtime_hwparams(substream, &jz4740_pcm_hardware);
 902 +       prtd = kzalloc(sizeof(struct jz4740_runtime_data), GFP_KERNEL);
 903 +
 904 +       if (prtd == NULL)
 905 +               return -ENOMEM;
 906 +
 907 +       runtime->private_data = prtd;
 908 +       return 0;
 909 +}
 910 +
 911 +static int jz4740_pcm_close(struct snd_pcm_substream *substream)
 912 +{
 913 +       struct snd_pcm_runtime *runtime = substream->runtime;
 914 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 915 +
 916 +       kfree(prtd);
 917 +
 918 +       return 0;
 919 +}
 920 +
 921 +static int jz4740_pcm_mmap(struct snd_pcm_substream *substream,
 922 +       struct vm_area_struct *vma)
 923 +{
 924 +       return remap_pfn_range(vma, vma->vm_start,
 925 +                       substream->dma_buffer.addr >> PAGE_SHIFT,
 926 +                       vma->vm_end - vma->vm_start, vma->vm_page_prot);
 927 +}
 928 +
 929 +static struct snd_pcm_ops jz4740_pcm_ops = {
 930 +       .open           = jz4740_pcm_open,
 931 +       .close          = jz4740_pcm_close,
 932 +       .ioctl          = snd_pcm_lib_ioctl,
 933 +       .hw_params      = jz4740_pcm_hw_params,
 934 +       .hw_free        = jz4740_pcm_hw_free,
 935 +       .prepare        = jz4740_pcm_prepare,
 936 +       .trigger        = jz4740_pcm_trigger,
 937 +       .pointer        = jz4740_pcm_pointer,
 938 +       .mmap           = jz4740_pcm_mmap,
 939 +};
 940 +
 941 +static int jz4740_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
 942 +{
 943 +       struct snd_pcm_substream *substream = pcm->streams[stream].substream;
 944 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
 945 +       size_t size = jz4740_pcm_hardware.buffer_bytes_max;
 946 +
 947 +       buf->dev.type = SNDRV_DMA_TYPE_DEV;
 948 +       buf->dev.dev = pcm->card->dev;
 949 +       buf->private_data = NULL;
 950 +
 951 +       buf->area = dma_alloc_noncoherent(pcm->card->dev, size,
 952 +                                         &buf->addr, GFP_KERNEL);
 953 +       if (!buf->area)
 954 +               return -ENOMEM;
 955 +
 956 +       buf->bytes = size;
 957 +
 958 +       return 0;
 959 +}
 960 +
 961 +static void jz4740_pcm_free(struct snd_pcm *pcm)
 962 +{
 963 +       struct snd_pcm_substream *substream;
 964 +       struct snd_dma_buffer *buf;
 965 +       int stream;
 966 +
 967 +       for (stream = 0; stream < 2; stream++) {
 968 +               substream = pcm->streams[stream].substream;
 969 +               if (!substream)
 970 +                       continue;
 971 +
 972 +               buf = &substream->dma_buffer;
 973 +               if (!buf->area)
 974 +                       continue;
 975 +
 976 +               dma_free_noncoherent(pcm->card->dev, buf->bytes,
 977 +                 buf->area, buf->addr);
 978 +               buf->area = NULL;
 979 +       }
 980 +}
 981 +
 982 +static u64 jz4740_pcm_dmamask = DMA_BIT_MASK(32);
 983 +
 984 +int jz4740_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
 985 +       struct snd_pcm *pcm)
 986 +{
 987 +       int ret = 0;
 988 +
 989 +       if (!card->dev->dma_mask)
 990 +               card->dev->dma_mask = &jz4740_pcm_dmamask;
 991 +
 992 +       if (!card->dev->coherent_dma_mask)
 993 +               card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
 994 +
 995 +       if (dai->playback.channels_min) {
 996 +               ret = jz4740_pcm_preallocate_dma_buffer(pcm,
 997 +                       SNDRV_PCM_STREAM_PLAYBACK);
 998 +               if (ret)
 999 +                       goto err;
1000 +       }
1001 +
1002 +       if (dai->capture.channels_min) {
1003 +               ret = jz4740_pcm_preallocate_dma_buffer(pcm,
1004 +                       SNDRV_PCM_STREAM_CAPTURE);
1005 +               if (ret)
1006 +                       goto err;
1007 +       }
1008 +
1009 +err:
1010 +       return ret;
1011 +}
1012 +
1013 +struct snd_soc_platform jz4740_soc_platform = {
1014 +               .name           = "jz4740-pcm",
1015 +               .pcm_ops        = &jz4740_pcm_ops,
1016 +               .pcm_new        = jz4740_pcm_new,
1017 +               .pcm_free       = jz4740_pcm_free,
1018 +};
1019 +EXPORT_SYMBOL_GPL(jz4740_soc_platform);
1020 +
1021 +static int __init jz4740_soc_platform_init(void)
1022 +{
1023 +       return snd_soc_register_platform(&jz4740_soc_platform);
1024 +}
1025 +module_init(jz4740_soc_platform_init);
1026 +
1027 +static void __exit jz4740_soc_platform_exit(void)
1028 +{
1029 +       snd_soc_unregister_platform(&jz4740_soc_platform);
1030 +}
1031 +module_exit(jz4740_soc_platform_exit);
1032 +
1033 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1034 +MODULE_DESCRIPTION("Ingenic SoC JZ4740 PCM driver");
1035 +MODULE_LICENSE("GPL");
1036 diff --git a/sound/soc/jz4740/jz4740-pcm.h b/sound/soc/jz4740/jz4740-pcm.h
1037 new file mode 100644
1038 index 0000000..2a11800
1039 --- /dev/null
1040 +++ b/sound/soc/jz4740/jz4740-pcm.h
1041 @@ -0,0 +1,22 @@
1042 +/*
1043 + *
1044 + * This program is free software; you can redistribute it and/or modify
1045 + * it under the terms of the GNU General Public License version 2 as
1046 + * published by the Free Software Foundation.
1047 + */
1048 +
1049 +#ifndef _JZ4740_PCM_H
1050 +#define _JZ4740_PCM_H
1051 +
1052 +#include <linux/dma-mapping.h>
1053 +#include <asm/mach-jz4740/dma.h>
1054 +
1055 +/* platform data */
1056 +extern struct snd_soc_platform jz4740_soc_platform;
1057 +
1058 +struct jz4740_pcm_config {
1059 +       struct jz4740_dma_config *dma_config;
1060 +       phys_addr_t fifo_addr;
1061 +};
1062 +
1063 +#endif
1064 --
1065 1.5.6.5
1066