target/linux/ar7/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
   3  * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19
  20 #ifndef __AR7_H__
  21 #define __AR7_H__
  22
  23 #include <linux/delay.h>
  24 #include <asm/addrspace.h>
  25 #include <linux/io.h>
  26
  27 #define AR7_REGS_BASE   0x08610000
  28
  29 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  30 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  31 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
  32 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
  33 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  34 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
  35 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  36 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  37 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
  38 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
  39 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
  40 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  41 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  42
  43 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
  44 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  45 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  46
  47 #define AR7_RESET_PEREPHERIAL   0x0
  48 #define AR7_RESET_SOFTWARE      0x4
  49 #define AR7_RESET_STATUS        0x8
  50
  51 #define AR7_RESET_BIT_CPMAC_LO  17
  52 #define AR7_RESET_BIT_CPMAC_HI  21
  53 #define AR7_RESET_BIT_MDIO      22
  54 #define AR7_RESET_BIT_EPHY      26
  55
  56 /* GPIO control registers */
  57 #define AR7_GPIO_INPUT  0x0
  58 #define AR7_GPIO_OUTPUT 0x4
  59 #define AR7_GPIO_DIR    0x8
  60 #define AR7_GPIO_ENABLE 0xc
  61
  62 #define AR7_CHIP_7100   0x18
  63 #define AR7_CHIP_7200   0x2b
  64 #define AR7_CHIP_7300   0x05
  65
  66 /* Interrupts */
  67 #define AR7_IRQ_UART0   15
  68 #define AR7_IRQ_UART1   16
  69
  70 /* Clocks */
  71 #define AR7_AFE_CLOCK   35328000
  72 #define AR7_REF_CLOCK   25000000
  73 #define AR7_XTAL_CLOCK  24000000
  74
  75 struct plat_cpmac_data {
  76         int reset_bit;
  77         int power_bit;
  78         u32 phy_mask;
  79         char dev_addr[6];
  80 };
  81
  82 struct plat_dsl_data {
  83         int reset_bit_dsl;
  84         int reset_bit_sar;
  85 };
  86
  87 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
  88
  89 static inline u16 ar7_chip_id(void)
  90 {
  91         return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
  92 }
  93
  94 static inline u8 ar7_chip_rev(void)
  95 {
  96         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
  97 }
  98
  99 static inline int ar7_cpu_freq(void)
 100 {
 101         return ar7_cpu_clock;
 102 }
 103
 104 static inline int ar7_bus_freq(void)
 105 {
 106         return ar7_bus_clock;
 107 }
 108
 109 static inline int ar7_vbus_freq(void)
 110 {
 111         return ar7_bus_clock / 2;
 112 }
 113 #define ar7_cpmac_freq ar7_vbus_freq
 114
 115 static inline int ar7_dsp_freq(void)
 116 {
 117         return ar7_dsp_clock;
 118 }
 119
 120 static inline int ar7_has_high_cpmac(void)
 121 {
 122         u16 chip_id = ar7_chip_id();
 123         switch (chip_id) {
 124         case AR7_CHIP_7100:
 125         case AR7_CHIP_7200:
 126                 return 0;
 127         default:
 128                 return 1;
 129         }
 130 }
 131 #define ar7_has_high_vlynq ar7_has_high_cpmac
 132 #define ar7_has_second_uart ar7_has_high_cpmac
 133
 134 static inline void ar7_device_enable(u32 bit)
 135 {
 136         void *reset_reg =
 137                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 138         writel(readl(reset_reg) | (1 << bit), reset_reg);
 139         mdelay(20);
 140 }
 141
 142 static inline void ar7_device_disable(u32 bit)
 143 {
 144         void *reset_reg =
 145                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 146         writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 147         mdelay(20);
 148 }
 149
 150 static inline void ar7_device_reset(u32 bit)
 151 {
 152         ar7_device_disable(bit);
 153         ar7_device_enable(bit);
 154 }
 155
 156 static inline void ar7_device_on(u32 bit)
 157 {
 158         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 159         writel(readl(power_reg) | (1 << bit), power_reg);
 160         mdelay(20);
 161 }
 162
 163 static inline void ar7_device_off(u32 bit)
 164 {
 165         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 166         writel(readl(power_reg) & ~(1 << bit), power_reg);
 167         mdelay(20);
 168 }
 169
 170 #endif /* __AR7_H__ */