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add Avila/Cambria latch LED support, thanks Chris
[openwrt.git] / target / linux / ixp4xx / patches-2.6.24 / 200-npe_driver.patch
1 Index: linux-2.6.24.7/drivers/net/arm/Kconfig
2 ===================================================================
3 --- linux-2.6.24.7.orig/drivers/net/arm/Kconfig
4 +++ linux-2.6.24.7/drivers/net/arm/Kconfig
5 @@ -47,3 +47,13 @@ config EP93XX_ETH
6 help
7 This is a driver for the ethernet hardware included in EP93xx CPUs.
8 Say Y if you are building a kernel for EP93xx based devices.
9 +
10 +config IXP4XX_ETH
11 + tristate "IXP4xx Ethernet support"
12 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
13 + select IXP4XX_NPE
14 + select IXP4XX_QMGR
15 + select MII
16 + help
17 + Say Y here if you want to use built-in Ethernet ports
18 + on IXP4xx processor.
19 Index: linux-2.6.24.7/drivers/net/arm/Makefile
20 ===================================================================
21 --- linux-2.6.24.7.orig/drivers/net/arm/Makefile
22 +++ linux-2.6.24.7/drivers/net/arm/Makefile
23 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
24 obj-$(CONFIG_ARM_ETHER1) += ether1.o
25 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
26 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
27 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
28 Index: linux-2.6.24.7/drivers/net/arm/ixp4xx_eth.c
29 ===================================================================
30 --- /dev/null
31 +++ linux-2.6.24.7/drivers/net/arm/ixp4xx_eth.c
32 @@ -0,0 +1,1261 @@
33 +/*
34 + * Intel IXP4xx Ethernet driver for Linux
35 + *
36 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
37 + *
38 + * This program is free software; you can redistribute it and/or modify it
39 + * under the terms of version 2 of the GNU General Public License
40 + * as published by the Free Software Foundation.
41 + *
42 + * Ethernet port config (0x00 is not present on IXP42X):
43 + *
44 + * logical port 0x00 0x10 0x20
45 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
46 + * physical PortId 2 0 1
47 + * TX queue 23 24 25
48 + * RX-free queue 26 27 28
49 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
50 + *
51 + *
52 + * Queue entries:
53 + * bits 0 -> 1 - NPE ID (RX and TX-done)
54 + * bits 0 -> 2 - priority (TX, per 802.1D)
55 + * bits 3 -> 4 - port ID (user-set?)
56 + * bits 5 -> 31 - physical descriptor address
57 + */
58 +
59 +#include <linux/delay.h>
60 +#include <linux/dma-mapping.h>
61 +#include <linux/dmapool.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/io.h>
64 +#include <linux/kernel.h>
65 +#include <linux/mii.h>
66 +#include <linux/platform_device.h>
67 +#include <asm/arch/npe.h>
68 +#include <asm/arch/qmgr.h>
69 +
70 +#define DEBUG_QUEUES 0
71 +#define DEBUG_DESC 0
72 +#define DEBUG_RX 0
73 +#define DEBUG_TX 0
74 +#define DEBUG_PKT_BYTES 0
75 +#define DEBUG_MDIO 0
76 +#define DEBUG_CLOSE 0
77 +
78 +#define DRV_NAME "ixp4xx_eth"
79 +
80 +#define MAX_NPES 3
81 +
82 +#define RX_DESCS 64 /* also length of all RX queues */
83 +#define TX_DESCS 16 /* also length of all TX queues */
84 +#define TXDONE_QUEUE_LEN 64 /* dwords */
85 +
86 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
87 +#define REGS_SIZE 0x1000
88 +#define MAX_MRU 1536 /* 0x600 */
89 +
90 +#define MDIO_INTERVAL (3 * HZ)
91 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
92 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
93 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
94 +
95 +#define NPE_ID(port_id) ((port_id) >> 4)
96 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
97 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
98 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
99 +#define TXDONE_QUEUE 31
100 +
101 +#define ETH_NAPI_WEIGHT 16
102 +
103 +/* TX Control Registers */
104 +#define TX_CNTRL0_TX_EN 0x01
105 +#define TX_CNTRL0_HALFDUPLEX 0x02
106 +#define TX_CNTRL0_RETRY 0x04
107 +#define TX_CNTRL0_PAD_EN 0x08
108 +#define TX_CNTRL0_APPEND_FCS 0x10
109 +#define TX_CNTRL0_2DEFER 0x20
110 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
111 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
112 +
113 +/* RX Control Registers */
114 +#define RX_CNTRL0_RX_EN 0x01
115 +#define RX_CNTRL0_PADSTRIP_EN 0x02
116 +#define RX_CNTRL0_SEND_FCS 0x04
117 +#define RX_CNTRL0_PAUSE_EN 0x08
118 +#define RX_CNTRL0_LOOP_EN 0x10
119 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
120 +#define RX_CNTRL0_RX_RUNT_EN 0x40
121 +#define RX_CNTRL0_BCAST_DIS 0x80
122 +#define RX_CNTRL1_DEFER_EN 0x01
123 +
124 +/* Core Control Register */
125 +#define CORE_RESET 0x01
126 +#define CORE_RX_FIFO_FLUSH 0x02
127 +#define CORE_TX_FIFO_FLUSH 0x04
128 +#define CORE_SEND_JAM 0x08
129 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
130 +
131 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
132 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
133 + TX_CNTRL0_2DEFER)
134 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
135 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
136 +
137 +
138 +/* NPE message codes */
139 +#define NPE_GETSTATUS 0x00
140 +#define NPE_EDB_SETPORTADDRESS 0x01
141 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
142 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
143 +#define NPE_GETSTATS 0x04
144 +#define NPE_RESETSTATS 0x05
145 +#define NPE_SETMAXFRAMELENGTHS 0x06
146 +#define NPE_VLAN_SETRXTAGMODE 0x07
147 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
148 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
149 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
150 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
151 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
152 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
153 +#define NPE_FW_SETFIREWALLMODE 0x0E
154 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
155 +#define NPE_PC_SETAPMACTABLE 0x11
156 +#define NPE_SETLOOPBACK_MODE 0x12
157 +#define NPE_PC_SETBSSIDTABLE 0x13
158 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
159 +#define NPE_APPENDFCSCONFIG 0x15
160 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
161 +#define NPE_MAC_RECOVERY_START 0x17
162 +
163 +
164 +#ifdef __ARMEB__
165 +typedef struct sk_buff buffer_t;
166 +#define free_buffer dev_kfree_skb
167 +#define free_buffer_irq dev_kfree_skb_irq
168 +#else
169 +typedef void buffer_t;
170 +#define free_buffer kfree
171 +#define free_buffer_irq kfree
172 +#endif
173 +
174 +struct eth_regs {
175 + u32 tx_control[2], __res1[2]; /* 000 */
176 + u32 rx_control[2], __res2[2]; /* 010 */
177 + u32 random_seed, __res3[3]; /* 020 */
178 + u32 partial_empty_threshold, __res4; /* 030 */
179 + u32 partial_full_threshold, __res5; /* 038 */
180 + u32 tx_start_bytes, __res6[3]; /* 040 */
181 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
182 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
183 + u32 slot_time, __res9[3]; /* 070 */
184 + u32 mdio_command[4]; /* 080 */
185 + u32 mdio_status[4]; /* 090 */
186 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
187 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
188 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
189 + u32 hw_addr[6], __res13[61]; /* 0F0 */
190 + u32 core_control; /* 1FC */
191 +};
192 +
193 +struct port {
194 + struct resource *mem_res;
195 + struct eth_regs __iomem *regs;
196 + struct npe *npe;
197 + struct net_device *netdev;
198 + struct napi_struct napi;
199 + struct net_device_stats stat;
200 + struct mii_if_info mii;
201 + struct delayed_work mdio_thread;
202 + struct eth_plat_info *plat;
203 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
204 + struct desc *desc_tab; /* coherent */
205 + u32 desc_tab_phys;
206 + int id; /* logical port ID */
207 + u16 mii_bmcr;
208 +};
209 +
210 +/* NPE message structure */
211 +struct msg {
212 +#ifdef __ARMEB__
213 + u8 cmd, eth_id, byte2, byte3;
214 + u8 byte4, byte5, byte6, byte7;
215 +#else
216 + u8 byte3, byte2, eth_id, cmd;
217 + u8 byte7, byte6, byte5, byte4;
218 +#endif
219 +};
220 +
221 +/* Ethernet packet descriptor */
222 +struct desc {
223 + u32 next; /* pointer to next buffer, unused */
224 +
225 +#ifdef __ARMEB__
226 + u16 buf_len; /* buffer length */
227 + u16 pkt_len; /* packet length */
228 + u32 data; /* pointer to data buffer in RAM */
229 + u8 dest_id;
230 + u8 src_id;
231 + u16 flags;
232 + u8 qos;
233 + u8 padlen;
234 + u16 vlan_tci;
235 +#else
236 + u16 pkt_len; /* packet length */
237 + u16 buf_len; /* buffer length */
238 + u32 data; /* pointer to data buffer in RAM */
239 + u16 flags;
240 + u8 src_id;
241 + u8 dest_id;
242 + u16 vlan_tci;
243 + u8 padlen;
244 + u8 qos;
245 +#endif
246 +
247 +#ifdef __ARMEB__
248 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
249 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
250 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
251 +#else
252 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
253 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
254 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
255 +#endif
256 +};
257 +
258 +
259 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
260 + (n) * sizeof(struct desc))
261 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
262 +
263 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
264 + ((n) + RX_DESCS) * sizeof(struct desc))
265 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
266 +
267 +#ifndef __ARMEB__
268 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
269 +{
270 + int i;
271 + for (i = 0; i < cnt; i++)
272 + dest[i] = swab32(src[i]);
273 +}
274 +#endif
275 +
276 +static spinlock_t mdio_lock;
277 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
278 +static int ports_open;
279 +static struct port *npe_port_tab[MAX_NPES];
280 +static struct dma_pool *dma_pool;
281 +
282 +
283 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
284 + int write, u16 cmd)
285 +{
286 + int cycles = 0;
287 +
288 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
289 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
290 + return 0;
291 + }
292 +
293 + if (write) {
294 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
295 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
296 + }
297 + __raw_writel(((phy_id << 5) | location) & 0xFF,
298 + &mdio_regs->mdio_command[2]);
299 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
300 + &mdio_regs->mdio_command[3]);
301 +
302 + while ((cycles < MAX_MDIO_RETRIES) &&
303 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
304 + udelay(1);
305 + cycles++;
306 + }
307 +
308 + if (cycles == MAX_MDIO_RETRIES) {
309 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
310 + return 0;
311 + }
312 +
313 +#if DEBUG_MDIO
314 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
315 + cycles);
316 +#endif
317 +
318 + if (write)
319 + return 0;
320 +
321 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
322 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
323 + return 0;
324 + }
325 +
326 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
327 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
328 +}
329 +
330 +static int mdio_read(struct net_device *dev, int phy_id, int location)
331 +{
332 + unsigned long flags;
333 + u16 val;
334 +
335 + spin_lock_irqsave(&mdio_lock, flags);
336 + val = mdio_cmd(dev, phy_id, location, 0, 0);
337 + spin_unlock_irqrestore(&mdio_lock, flags);
338 + return val;
339 +}
340 +
341 +static void mdio_write(struct net_device *dev, int phy_id, int location,
342 + int val)
343 +{
344 + unsigned long flags;
345 +
346 + spin_lock_irqsave(&mdio_lock, flags);
347 + mdio_cmd(dev, phy_id, location, 1, val);
348 + spin_unlock_irqrestore(&mdio_lock, flags);
349 +}
350 +
351 +static void phy_reset(struct net_device *dev, int phy_id)
352 +{
353 + struct port *port = netdev_priv(dev);
354 + int cycles = 0;
355 +
356 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
357 +
358 + while (cycles < MAX_MII_RESET_RETRIES) {
359 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
360 +#if DEBUG_MDIO
361 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
362 + dev->name, cycles);
363 +#endif
364 + return;
365 + }
366 + udelay(1);
367 + cycles++;
368 + }
369 +
370 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
371 +}
372 +
373 +static void eth_set_duplex(struct port *port)
374 +{
375 + if (port->mii.full_duplex)
376 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
377 + &port->regs->tx_control[0]);
378 + else
379 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
380 + &port->regs->tx_control[0]);
381 +}
382 +
383 +
384 +static void phy_check_media(struct port *port, int init)
385 +{
386 + if (mii_check_media(&port->mii, 1, init))
387 + eth_set_duplex(port);
388 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
389 + struct net_device *dev = port->netdev;
390 + int cur_link = mii_link_ok(&port->mii);
391 + int prev_link = netif_carrier_ok(dev);
392 +
393 + if (!prev_link && cur_link) {
394 + printk(KERN_INFO "%s: link up\n", dev->name);
395 + netif_carrier_on(dev);
396 + } else if (prev_link && !cur_link) {
397 + printk(KERN_INFO "%s: link down\n", dev->name);
398 + netif_carrier_off(dev);
399 + }
400 + }
401 +}
402 +
403 +
404 +static void mdio_thread(struct work_struct *work)
405 +{
406 + struct port *port = container_of(work, struct port, mdio_thread.work);
407 +
408 + phy_check_media(port, 0);
409 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
410 +}
411 +
412 +
413 +static inline void debug_pkt(struct net_device *dev, const char *func,
414 + u8 *data, int len)
415 +{
416 +#if DEBUG_PKT_BYTES
417 + int i;
418 +
419 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
420 + for (i = 0; i < len; i++) {
421 + if (i >= DEBUG_PKT_BYTES)
422 + break;
423 + printk("%s%02X",
424 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
425 + data[i]);
426 + }
427 + printk("\n");
428 +#endif
429 +}
430 +
431 +
432 +static inline void debug_desc(u32 phys, struct desc *desc)
433 +{
434 +#if DEBUG_DESC
435 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
436 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
437 + phys, desc->next, desc->buf_len, desc->pkt_len,
438 + desc->data, desc->dest_id, desc->src_id, desc->flags,
439 + desc->qos, desc->padlen, desc->vlan_tci,
440 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
441 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
442 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
443 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
444 +#endif
445 +}
446 +
447 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
448 +{
449 +#if DEBUG_QUEUES
450 + static struct {
451 + int queue;
452 + char *name;
453 + } names[] = {
454 + { TX_QUEUE(0x10), "TX#0 " },
455 + { TX_QUEUE(0x20), "TX#1 " },
456 + { TX_QUEUE(0x00), "TX#2 " },
457 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
458 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
459 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
460 + { TXDONE_QUEUE, "TX-done " },
461 + };
462 + int i;
463 +
464 + for (i = 0; i < ARRAY_SIZE(names); i++)
465 + if (names[i].queue == queue)
466 + break;
467 +
468 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
469 + i < ARRAY_SIZE(names) ? names[i].name : "",
470 + is_get ? "->" : "<-", phys);
471 +#endif
472 +}
473 +
474 +static inline u32 queue_get_entry(unsigned int queue)
475 +{
476 + u32 phys = qmgr_get_entry(queue);
477 + debug_queue(queue, 1, phys);
478 + return phys;
479 +}
480 +
481 +static inline int queue_get_desc(unsigned int queue, struct port *port,
482 + int is_tx)
483 +{
484 + u32 phys, tab_phys, n_desc;
485 + struct desc *tab;
486 +
487 + if (!(phys = queue_get_entry(queue)))
488 + return -1;
489 +
490 + phys &= ~0x1F; /* mask out non-address bits */
491 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
492 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
493 + n_desc = (phys - tab_phys) / sizeof(struct desc);
494 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
495 + debug_desc(phys, &tab[n_desc]);
496 + BUG_ON(tab[n_desc].next);
497 + return n_desc;
498 +}
499 +
500 +static inline void queue_put_desc(unsigned int queue, u32 phys,
501 + struct desc *desc)
502 +{
503 + debug_queue(queue, 0, phys);
504 + debug_desc(phys, desc);
505 + BUG_ON(phys & 0x1F);
506 + qmgr_put_entry(queue, phys);
507 + BUG_ON(qmgr_stat_overflow(queue));
508 +}
509 +
510 +
511 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
512 +{
513 +#ifdef __ARMEB__
514 + dma_unmap_single(&port->netdev->dev, desc->data,
515 + desc->buf_len, DMA_TO_DEVICE);
516 +#else
517 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
518 + ALIGN((desc->data & 3) + desc->buf_len, 4),
519 + DMA_TO_DEVICE);
520 +#endif
521 +}
522 +
523 +
524 +static void eth_rx_irq(void *pdev)
525 +{
526 + struct net_device *dev = pdev;
527 + struct port *port = netdev_priv(dev);
528 +
529 +#if DEBUG_RX
530 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
531 +#endif
532 + qmgr_disable_irq(port->plat->rxq);
533 + netif_rx_schedule(dev, &port->napi);
534 +}
535 +
536 +static int eth_poll(struct napi_struct *napi, int budget)
537 +{
538 + struct port *port = container_of(napi, struct port, napi);
539 + struct net_device *dev = port->netdev;
540 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
541 + int received = 0;
542 +
543 +#if DEBUG_RX
544 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
545 +#endif
546 +
547 + while (received < budget) {
548 + struct sk_buff *skb;
549 + struct desc *desc;
550 + int n;
551 +#ifdef __ARMEB__
552 + struct sk_buff *temp;
553 + u32 phys;
554 +#endif
555 +
556 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
557 + received = 0; /* No packet received */
558 +#if DEBUG_RX
559 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
560 + dev->name);
561 +#endif
562 + netif_rx_complete(dev, &port->napi);
563 + qmgr_enable_irq(rxq);
564 + if (!qmgr_stat_empty(rxq) &&
565 + netif_rx_reschedule(dev, &port->napi)) {
566 +#if DEBUG_RX
567 + printk(KERN_DEBUG "%s: eth_poll"
568 + " netif_rx_reschedule successed\n",
569 + dev->name);
570 +#endif
571 + qmgr_disable_irq(rxq);
572 + continue;
573 + }
574 +#if DEBUG_RX
575 + printk(KERN_DEBUG "%s: eth_poll all done\n",
576 + dev->name);
577 +#endif
578 + return 0; /* all work done */
579 + }
580 +
581 + desc = rx_desc_ptr(port, n);
582 +
583 +#ifdef __ARMEB__
584 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
585 + phys = dma_map_single(&dev->dev, skb->data,
586 + MAX_MRU, DMA_FROM_DEVICE);
587 + if (dma_mapping_error(phys)) {
588 + dev_kfree_skb(skb);
589 + skb = NULL;
590 + }
591 + }
592 +#else
593 + skb = netdev_alloc_skb(dev, desc->pkt_len);
594 +#endif
595 +
596 + if (!skb) {
597 + port->stat.rx_dropped++;
598 + /* put the desc back on RX-ready queue */
599 + desc->buf_len = MAX_MRU;
600 + desc->pkt_len = 0;
601 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
602 + continue;
603 + }
604 +
605 + /* process received frame */
606 +#ifdef __ARMEB__
607 + temp = skb;
608 + skb = port->rx_buff_tab[n];
609 + dma_unmap_single(&dev->dev, desc->data,
610 + MAX_MRU, DMA_FROM_DEVICE);
611 +#else
612 + dma_sync_single(&dev->dev, desc->data,
613 + MAX_MRU, DMA_FROM_DEVICE);
614 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
615 + ALIGN(desc->pkt_len, 4) / 4);
616 +#endif
617 + skb_put(skb, desc->pkt_len);
618 +
619 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
620 +
621 + skb->protocol = eth_type_trans(skb, dev);
622 + dev->last_rx = jiffies;
623 + port->stat.rx_packets++;
624 + port->stat.rx_bytes += skb->len;
625 + netif_receive_skb(skb);
626 +
627 + /* put the new buffer on RX-free queue */
628 +#ifdef __ARMEB__
629 + port->rx_buff_tab[n] = temp;
630 + desc->data = phys;
631 +#endif
632 + desc->buf_len = MAX_MRU;
633 + desc->pkt_len = 0;
634 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
635 + received++;
636 + }
637 +
638 +#if DEBUG_RX
639 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
640 +#endif
641 + return received; /* not all work done */
642 +}
643 +
644 +
645 +static void eth_txdone_irq(void *unused)
646 +{
647 + u32 phys;
648 +
649 +#if DEBUG_TX
650 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
651 +#endif
652 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
653 + u32 npe_id, n_desc;
654 + struct port *port;
655 + struct desc *desc;
656 + int start;
657 +
658 + npe_id = phys & 3;
659 + BUG_ON(npe_id >= MAX_NPES);
660 + port = npe_port_tab[npe_id];
661 + BUG_ON(!port);
662 + phys &= ~0x1F; /* mask out non-address bits */
663 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
664 + BUG_ON(n_desc >= TX_DESCS);
665 + desc = tx_desc_ptr(port, n_desc);
666 + debug_desc(phys, desc);
667 +
668 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
669 + port->stat.tx_packets++;
670 + port->stat.tx_bytes += desc->pkt_len;
671 +
672 + dma_unmap_tx(port, desc);
673 +#if DEBUG_TX
674 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
675 + port->netdev->name, port->tx_buff_tab[n_desc]);
676 +#endif
677 + free_buffer_irq(port->tx_buff_tab[n_desc]);
678 + port->tx_buff_tab[n_desc] = NULL;
679 + }
680 +
681 + start = qmgr_stat_empty(port->plat->txreadyq);
682 + queue_put_desc(port->plat->txreadyq, phys, desc);
683 + if (start) {
684 +#if DEBUG_TX
685 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
686 + port->netdev->name);
687 +#endif
688 + netif_wake_queue(port->netdev);
689 + }
690 + }
691 +}
692 +
693 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
694 +{
695 + struct port *port = netdev_priv(dev);
696 + unsigned int txreadyq = port->plat->txreadyq;
697 + int len, offset, bytes, n;
698 + void *mem;
699 + u32 phys;
700 + struct desc *desc;
701 +
702 +#if DEBUG_TX
703 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
704 +#endif
705 +
706 + if (unlikely(skb->len > MAX_MRU)) {
707 + dev_kfree_skb(skb);
708 + port->stat.tx_errors++;
709 + return NETDEV_TX_OK;
710 + }
711 +
712 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
713 +
714 + len = skb->len;
715 +#ifdef __ARMEB__
716 + offset = 0; /* no need to keep alignment */
717 + bytes = len;
718 + mem = skb->data;
719 +#else
720 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
721 + bytes = ALIGN(offset + len, 4);
722 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
723 + dev_kfree_skb(skb);
724 + port->stat.tx_dropped++;
725 + return NETDEV_TX_OK;
726 + }
727 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
728 + dev_kfree_skb(skb);
729 +#endif
730 +
731 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
732 + if (dma_mapping_error(phys)) {
733 +#ifdef __ARMEB__
734 + dev_kfree_skb(skb);
735 +#else
736 + kfree(mem);
737 +#endif
738 + port->stat.tx_dropped++;
739 + return NETDEV_TX_OK;
740 + }
741 +
742 + n = queue_get_desc(txreadyq, port, 1);
743 + BUG_ON(n < 0);
744 + desc = tx_desc_ptr(port, n);
745 +
746 +#ifdef __ARMEB__
747 + port->tx_buff_tab[n] = skb;
748 +#else
749 + port->tx_buff_tab[n] = mem;
750 +#endif
751 + desc->data = phys + offset;
752 + desc->buf_len = desc->pkt_len = len;
753 +
754 + /* NPE firmware pads short frames with zeros internally */
755 + wmb();
756 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
757 + dev->trans_start = jiffies;
758 +
759 + if (qmgr_stat_empty(txreadyq)) {
760 +#if DEBUG_TX
761 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
762 +#endif
763 + netif_stop_queue(dev);
764 + /* we could miss TX ready interrupt */
765 + if (!qmgr_stat_empty(txreadyq)) {
766 +#if DEBUG_TX
767 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
768 + dev->name);
769 +#endif
770 + netif_wake_queue(dev);
771 + }
772 + }
773 +
774 +#if DEBUG_TX
775 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
776 +#endif
777 + return NETDEV_TX_OK;
778 +}
779 +
780 +
781 +static struct net_device_stats *eth_stats(struct net_device *dev)
782 +{
783 + struct port *port = netdev_priv(dev);
784 + return &port->stat;
785 +}
786 +
787 +static void eth_set_mcast_list(struct net_device *dev)
788 +{
789 + struct port *port = netdev_priv(dev);
790 + struct dev_mc_list *mclist = dev->mc_list;
791 + u8 diffs[ETH_ALEN], *addr;
792 + int cnt = dev->mc_count, i;
793 +
794 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
795 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
796 + &port->regs->rx_control[0]);
797 + return;
798 + }
799 +
800 + memset(diffs, 0, ETH_ALEN);
801 + addr = mclist->dmi_addr; /* first MAC address */
802 +
803 + while (--cnt && (mclist = mclist->next))
804 + for (i = 0; i < ETH_ALEN; i++)
805 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
806 +
807 + for (i = 0; i < ETH_ALEN; i++) {
808 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
809 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
810 + }
811 +
812 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
813 + &port->regs->rx_control[0]);
814 +}
815 +
816 +
817 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
818 +{
819 + struct port *port = netdev_priv(dev);
820 + unsigned int duplex_chg;
821 + int err;
822 +
823 + if (!netif_running(dev))
824 + return -EINVAL;
825 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
826 + if (duplex_chg)
827 + eth_set_duplex(port);
828 + return err;
829 +}
830 +
831 +
832 +static int request_queues(struct port *port)
833 +{
834 + int err;
835 +
836 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
837 + if (err)
838 + return err;
839 +
840 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
841 + if (err)
842 + goto rel_rxfree;
843 +
844 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
845 + if (err)
846 + goto rel_rx;
847 +
848 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
849 + if (err)
850 + goto rel_tx;
851 +
852 + /* TX-done queue handles skbs sent out by the NPEs */
853 + if (!ports_open) {
854 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
855 + if (err)
856 + goto rel_txready;
857 + }
858 + return 0;
859 +
860 +rel_txready:
861 + qmgr_release_queue(port->plat->txreadyq);
862 +rel_tx:
863 + qmgr_release_queue(TX_QUEUE(port->id));
864 +rel_rx:
865 + qmgr_release_queue(port->plat->rxq);
866 +rel_rxfree:
867 + qmgr_release_queue(RXFREE_QUEUE(port->id));
868 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
869 + port->netdev->name);
870 + return err;
871 +}
872 +
873 +static void release_queues(struct port *port)
874 +{
875 + qmgr_release_queue(RXFREE_QUEUE(port->id));
876 + qmgr_release_queue(port->plat->rxq);
877 + qmgr_release_queue(TX_QUEUE(port->id));
878 + qmgr_release_queue(port->plat->txreadyq);
879 +
880 + if (!ports_open)
881 + qmgr_release_queue(TXDONE_QUEUE);
882 +}
883 +
884 +static int init_queues(struct port *port)
885 +{
886 + int i;
887 +
888 + if (!ports_open)
889 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
890 + POOL_ALLOC_SIZE, 32, 0)))
891 + return -ENOMEM;
892 +
893 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
894 + &port->desc_tab_phys)))
895 + return -ENOMEM;
896 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
897 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
898 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
899 +
900 + /* Setup RX buffers */
901 + for (i = 0; i < RX_DESCS; i++) {
902 + struct desc *desc = rx_desc_ptr(port, i);
903 + buffer_t *buff;
904 + void *data;
905 +#ifdef __ARMEB__
906 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
907 + return -ENOMEM;
908 + data = buff->data;
909 +#else
910 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
911 + return -ENOMEM;
912 + data = buff;
913 +#endif
914 + desc->buf_len = MAX_MRU;
915 + desc->data = dma_map_single(&port->netdev->dev, data,
916 + MAX_MRU, DMA_FROM_DEVICE);
917 + if (dma_mapping_error(desc->data)) {
918 + free_buffer(buff);
919 + return -EIO;
920 + }
921 + port->rx_buff_tab[i] = buff;
922 + }
923 +
924 + return 0;
925 +}
926 +
927 +static void destroy_queues(struct port *port)
928 +{
929 + int i;
930 +
931 + if (port->desc_tab) {
932 + for (i = 0; i < RX_DESCS; i++) {
933 + struct desc *desc = rx_desc_ptr(port, i);
934 + buffer_t *buff = port->rx_buff_tab[i];
935 + if (buff) {
936 + dma_unmap_single(&port->netdev->dev,
937 + desc->data, MAX_MRU,
938 + DMA_FROM_DEVICE);
939 + free_buffer(buff);
940 + }
941 + }
942 + for (i = 0; i < TX_DESCS; i++) {
943 + struct desc *desc = tx_desc_ptr(port, i);
944 + buffer_t *buff = port->tx_buff_tab[i];
945 + if (buff) {
946 + dma_unmap_tx(port, desc);
947 + free_buffer(buff);
948 + }
949 + }
950 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
951 + port->desc_tab = NULL;
952 + }
953 +
954 + if (!ports_open && dma_pool) {
955 + dma_pool_destroy(dma_pool);
956 + dma_pool = NULL;
957 + }
958 +}
959 +
960 +static int eth_open(struct net_device *dev)
961 +{
962 + struct port *port = netdev_priv(dev);
963 + struct npe *npe = port->npe;
964 + struct msg msg;
965 + int i, err;
966 +
967 + if (!npe_running(npe)) {
968 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
969 + if (err)
970 + return err;
971 +
972 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
973 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
974 + npe_name(npe));
975 + return -EIO;
976 + }
977 + }
978 +
979 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
980 +
981 + memset(&msg, 0, sizeof(msg));
982 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
983 + msg.eth_id = port->id;
984 + msg.byte5 = port->plat->rxq | 0x80;
985 + msg.byte7 = port->plat->rxq << 4;
986 + for (i = 0; i < 8; i++) {
987 + msg.byte3 = i;
988 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
989 + return -EIO;
990 + }
991 +
992 + msg.cmd = NPE_EDB_SETPORTADDRESS;
993 + msg.eth_id = PHYSICAL_ID(port->id);
994 + msg.byte2 = dev->dev_addr[0];
995 + msg.byte3 = dev->dev_addr[1];
996 + msg.byte4 = dev->dev_addr[2];
997 + msg.byte5 = dev->dev_addr[3];
998 + msg.byte6 = dev->dev_addr[4];
999 + msg.byte7 = dev->dev_addr[5];
1000 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1001 + return -EIO;
1002 +
1003 + memset(&msg, 0, sizeof(msg));
1004 + msg.cmd = NPE_FW_SETFIREWALLMODE;
1005 + msg.eth_id = port->id;
1006 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1007 + return -EIO;
1008 +
1009 + if ((err = request_queues(port)) != 0)
1010 + return err;
1011 +
1012 + if ((err = init_queues(port)) != 0) {
1013 + destroy_queues(port);
1014 + release_queues(port);
1015 + return err;
1016 + }
1017 +
1018 + for (i = 0; i < ETH_ALEN; i++)
1019 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1020 + __raw_writel(0x08, &port->regs->random_seed);
1021 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
1022 + __raw_writel(0x30, &port->regs->partial_full_threshold);
1023 + __raw_writel(0x08, &port->regs->tx_start_bytes);
1024 + __raw_writel(0x15, &port->regs->tx_deferral);
1025 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1026 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1027 + __raw_writel(0x80, &port->regs->slot_time);
1028 + __raw_writel(0x01, &port->regs->int_clock_threshold);
1029 +
1030 + /* Populate queues with buffers, no failure after this point */
1031 + for (i = 0; i < TX_DESCS; i++)
1032 + queue_put_desc(port->plat->txreadyq,
1033 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
1034 +
1035 + for (i = 0; i < RX_DESCS; i++)
1036 + queue_put_desc(RXFREE_QUEUE(port->id),
1037 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
1038 +
1039 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1040 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1041 + __raw_writel(0, &port->regs->rx_control[1]);
1042 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1043 +
1044 + napi_enable(&port->napi); /* check location of this call */
1045 +
1046 + phy_check_media(port, 1);
1047 + eth_set_mcast_list(dev);
1048 + netif_start_queue(dev);
1049 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1050 +
1051 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1052 + eth_rx_irq, dev);
1053 + if (!ports_open) {
1054 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1055 + eth_txdone_irq, NULL);
1056 + qmgr_enable_irq(TXDONE_QUEUE);
1057 + }
1058 + ports_open++;
1059 + netif_rx_schedule(dev, &port->napi); /* we may already have RX data, enables IRQ */
1060 + return 0;
1061 +}
1062 +
1063 +static int eth_close(struct net_device *dev)
1064 +{
1065 + struct port *port = netdev_priv(dev);
1066 + struct msg msg;
1067 + int buffs = RX_DESCS; /* allocated RX buffers */
1068 + int i;
1069 +
1070 + ports_open--;
1071 + qmgr_disable_irq(port->plat->rxq);
1072 + netif_stop_queue(dev);
1073 +
1074 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1075 + buffs--;
1076 +
1077 + memset(&msg, 0, sizeof(msg));
1078 + msg.cmd = NPE_SETLOOPBACK_MODE;
1079 + msg.eth_id = port->id;
1080 + msg.byte3 = 1;
1081 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1082 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1083 +
1084 + i = 0;
1085 + do { /* drain RX buffers */
1086 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1087 + buffs--;
1088 + if (!buffs)
1089 + break;
1090 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1091 + /* we have to inject some packet */
1092 + struct desc *desc;
1093 + u32 phys;
1094 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
1095 + BUG_ON(n < 0);
1096 + desc = tx_desc_ptr(port, n);
1097 + phys = tx_desc_phys(port, n);
1098 + desc->buf_len = desc->pkt_len = 1;
1099 + wmb();
1100 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
1101 + }
1102 + udelay(1);
1103 + } while (++i < MAX_CLOSE_WAIT);
1104 +
1105 + if (buffs)
1106 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1107 + " left in NPE\n", dev->name, buffs);
1108 +#if DEBUG_CLOSE
1109 + if (!buffs)
1110 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1111 +#endif
1112 +
1113 + buffs = TX_DESCS;
1114 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1115 + buffs--; /* cancel TX */
1116 +
1117 + i = 0;
1118 + do {
1119 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1120 + buffs--;
1121 + if (!buffs)
1122 + break;
1123 + } while (++i < MAX_CLOSE_WAIT);
1124 +
1125 + if (buffs)
1126 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1127 + "left in NPE\n", dev->name, buffs);
1128 +#if DEBUG_CLOSE
1129 + if (!buffs)
1130 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1131 +#endif
1132 +
1133 + msg.byte3 = 0;
1134 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1135 + printk(KERN_CRIT "%s: unable to disable loopback\n",
1136 + dev->name);
1137 +
1138 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
1139 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1140 + mdio_write(dev, port->plat->phy, MII_BMCR,
1141 + port->mii_bmcr | BMCR_PDOWN);
1142 +
1143 + if (!ports_open)
1144 + qmgr_disable_irq(TXDONE_QUEUE);
1145 + cancel_rearming_delayed_work(&port->mdio_thread);
1146 + napi_disable(&port->napi);
1147 + destroy_queues(port);
1148 + release_queues(port);
1149 + return 0;
1150 +}
1151 +
1152 +static int __devinit eth_init_one(struct platform_device *pdev)
1153 +{
1154 + struct port *port;
1155 + struct net_device *dev;
1156 + struct eth_plat_info *plat = pdev->dev.platform_data;
1157 + u32 regs_phys;
1158 + int err;
1159 +
1160 + if (!(dev = alloc_etherdev(sizeof(struct port))))
1161 + return -ENOMEM;
1162 +
1163 + SET_NETDEV_DEV(dev, &pdev->dev);
1164 + port = netdev_priv(dev);
1165 + port->netdev = dev;
1166 + port->id = pdev->id;
1167 +
1168 + switch (port->id) {
1169 + case IXP4XX_ETH_NPEA:
1170 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1171 + regs_phys = IXP4XX_EthA_BASE_PHYS;
1172 + break;
1173 + case IXP4XX_ETH_NPEB:
1174 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1175 + regs_phys = IXP4XX_EthB_BASE_PHYS;
1176 + break;
1177 + case IXP4XX_ETH_NPEC:
1178 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1179 + regs_phys = IXP4XX_EthC_BASE_PHYS;
1180 + break;
1181 + default:
1182 + err = -ENOSYS;
1183 + goto err_free;
1184 + }
1185 +
1186 + dev->open = eth_open;
1187 + dev->hard_start_xmit = eth_xmit;
1188 + dev->stop = eth_close;
1189 + dev->get_stats = eth_stats;
1190 + dev->do_ioctl = eth_ioctl;
1191 + dev->set_multicast_list = eth_set_mcast_list;
1192 + dev->tx_queue_len = 100;
1193 +
1194 + netif_napi_add(dev, &port->napi, eth_poll, ETH_NAPI_WEIGHT);
1195 +
1196 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1197 + err = -EIO;
1198 + goto err_free;
1199 + }
1200 +
1201 + if (register_netdev(dev)) {
1202 + err = -EIO;
1203 + goto err_npe_rel;
1204 + }
1205 +
1206 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1207 + if (!port->mem_res) {
1208 + err = -EBUSY;
1209 + goto err_unreg;
1210 + }
1211 +
1212 + port->plat = plat;
1213 + npe_port_tab[NPE_ID(port->id)] = port;
1214 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1215 +
1216 + platform_set_drvdata(pdev, dev);
1217 +
1218 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1219 + &port->regs->core_control);
1220 + udelay(50);
1221 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1222 + udelay(50);
1223 +
1224 + port->mii.dev = dev;
1225 + port->mii.mdio_read = mdio_read;
1226 + port->mii.mdio_write = mdio_write;
1227 + port->mii.phy_id = plat->phy;
1228 + port->mii.phy_id_mask = 0x1F;
1229 + port->mii.reg_num_mask = 0x1F;
1230 +
1231 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1232 + npe_name(port->npe));
1233 +
1234 + phy_reset(dev, plat->phy);
1235 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1236 + ~(BMCR_RESET | BMCR_PDOWN);
1237 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1238 +
1239 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1240 + return 0;
1241 +
1242 +err_unreg:
1243 + unregister_netdev(dev);
1244 +err_npe_rel:
1245 + npe_release(port->npe);
1246 +err_free:
1247 + free_netdev(dev);
1248 + return err;
1249 +}
1250 +
1251 +static int __devexit eth_remove_one(struct platform_device *pdev)
1252 +{
1253 + struct net_device *dev = platform_get_drvdata(pdev);
1254 + struct port *port = netdev_priv(dev);
1255 +
1256 + unregister_netdev(dev);
1257 + npe_port_tab[NPE_ID(port->id)] = NULL;
1258 + platform_set_drvdata(pdev, NULL);
1259 + npe_release(port->npe);
1260 + release_resource(port->mem_res);
1261 + free_netdev(dev);
1262 + return 0;
1263 +}
1264 +
1265 +static struct platform_driver drv = {
1266 + .driver.name = DRV_NAME,
1267 + .probe = eth_init_one,
1268 + .remove = eth_remove_one,
1269 +};
1270 +
1271 +static int __init eth_init_module(void)
1272 +{
1273 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1274 + return -ENOSYS;
1275 +
1276 + /* All MII PHY accesses use NPE-B Ethernet registers */
1277 + spin_lock_init(&mdio_lock);
1278 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1279 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1280 +
1281 + return platform_driver_register(&drv);
1282 +}
1283 +
1284 +static void __exit eth_cleanup_module(void)
1285 +{
1286 + platform_driver_unregister(&drv);
1287 +}
1288 +
1289 +MODULE_AUTHOR("Krzysztof Halasa");
1290 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1291 +MODULE_LICENSE("GPL v2");
1292 +module_init(eth_init_module);
1293 +module_exit(eth_cleanup_module);
1294 Index: linux-2.6.24.7/drivers/net/wan/Kconfig
1295 ===================================================================
1296 --- linux-2.6.24.7.orig/drivers/net/wan/Kconfig
1297 +++ linux-2.6.24.7/drivers/net/wan/Kconfig
1298 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
1299
1300 Say Y if your card supports this feature.
1301
1302 +config IXP4XX_HSS
1303 + tristate "IXP4xx HSS (synchronous serial port) support"
1304 + depends on HDLC && ARM && ARCH_IXP4XX
1305 + select IXP4XX_NPE
1306 + select IXP4XX_QMGR
1307 + help
1308 + Say Y here if you want to use built-in HSS ports
1309 + on IXP4xx processor.
1310 +
1311 config DLCI
1312 tristate "Frame Relay DLCI support"
1313 ---help---
1314 Index: linux-2.6.24.7/drivers/net/wan/Makefile
1315 ===================================================================
1316 --- linux-2.6.24.7.orig/drivers/net/wan/Makefile
1317 +++ linux-2.6.24.7/drivers/net/wan/Makefile
1318 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
1319 obj-$(CONFIG_WANXL) += wanxl.o
1320 obj-$(CONFIG_PCI200SYN) += pci200syn.o
1321 obj-$(CONFIG_PC300TOO) += pc300too.o
1322 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
1323
1324 clean-files := wanxlfw.inc
1325 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
1326 Index: linux-2.6.24.7/drivers/net/wan/ixp4xx_hss.c
1327 ===================================================================
1328 --- /dev/null
1329 +++ linux-2.6.24.7/drivers/net/wan/ixp4xx_hss.c
1330 @@ -0,0 +1,1270 @@
1331 +/*
1332 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
1333 + *
1334 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1335 + *
1336 + * This program is free software; you can redistribute it and/or modify it
1337 + * under the terms of version 2 of the GNU General Public License
1338 + * as published by the Free Software Foundation.
1339 + */
1340 +
1341 +#include <linux/dma-mapping.h>
1342 +#include <linux/dmapool.h>
1343 +#include <linux/io.h>
1344 +#include <linux/kernel.h>
1345 +#include <linux/hdlc.h>
1346 +#include <linux/platform_device.h>
1347 +#include <asm/arch/npe.h>
1348 +#include <asm/arch/qmgr.h>
1349 +
1350 +#define DEBUG_QUEUES 0
1351 +#define DEBUG_DESC 0
1352 +#define DEBUG_RX 0
1353 +#define DEBUG_TX 0
1354 +#define DEBUG_PKT_BYTES 0
1355 +#define DEBUG_CLOSE 0
1356 +
1357 +#define DRV_NAME "ixp4xx_hss"
1358 +
1359 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
1360 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
1361 +#define FRAME_SYNC_SIZE 1024
1362 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
1363 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
1364 +
1365 +#define RX_DESCS 16 /* also length of all RX queues */
1366 +#define TX_DESCS 16 /* also length of all TX queues */
1367 +
1368 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1369 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
1370 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
1371 +
1372 +/* Queue IDs */
1373 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
1374 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
1375 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
1376 +#define HSS0_PKT_TX1_QUEUE 15
1377 +#define HSS0_PKT_TX2_QUEUE 16
1378 +#define HSS0_PKT_TX3_QUEUE 17
1379 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
1380 +#define HSS0_PKT_RXFREE1_QUEUE 19
1381 +#define HSS0_PKT_RXFREE2_QUEUE 20
1382 +#define HSS0_PKT_RXFREE3_QUEUE 21
1383 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
1384 +
1385 +#define HSS1_CHL_RXTRIG_QUEUE 10
1386 +#define HSS1_PKT_RX_QUEUE 0
1387 +#define HSS1_PKT_TX0_QUEUE 5
1388 +#define HSS1_PKT_TX1_QUEUE 6
1389 +#define HSS1_PKT_TX2_QUEUE 7
1390 +#define HSS1_PKT_TX3_QUEUE 8
1391 +#define HSS1_PKT_RXFREE0_QUEUE 1
1392 +#define HSS1_PKT_RXFREE1_QUEUE 2
1393 +#define HSS1_PKT_RXFREE2_QUEUE 3
1394 +#define HSS1_PKT_RXFREE3_QUEUE 4
1395 +#define HSS1_PKT_TXDONE_QUEUE 9
1396 +
1397 +#define NPE_PKT_MODE_HDLC 0
1398 +#define NPE_PKT_MODE_RAW 1
1399 +#define NPE_PKT_MODE_56KMODE 2
1400 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
1401 +
1402 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
1403 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
1404 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
1405 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
1406 +
1407 +
1408 +/* hss_config, PCRs */
1409 +/* Frame sync sampling, default = active low */
1410 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
1411 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
1412 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
1413 +
1414 +/* Frame sync pin: input (default) or output generated off a given clk edge */
1415 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
1416 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
1417 +
1418 +/* Frame and data clock sampling on edge, default = falling */
1419 +#define PCR_FCLK_EDGE_RISING 0x08000000
1420 +#define PCR_DCLK_EDGE_RISING 0x04000000
1421 +
1422 +/* Clock direction, default = input */
1423 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
1424 +
1425 +/* Generate/Receive frame pulses, default = enabled */
1426 +#define PCR_FRM_PULSE_DISABLED 0x01000000
1427 +
1428 + /* Data rate is full (default) or half the configured clk speed */
1429 +#define PCR_HALF_CLK_RATE 0x00200000
1430 +
1431 +/* Invert data between NPE and HSS FIFOs? (default = no) */
1432 +#define PCR_DATA_POLARITY_INVERT 0x00100000
1433 +
1434 +/* TX/RX endianness, default = LSB */
1435 +#define PCR_MSB_ENDIAN 0x00080000
1436 +
1437 +/* Normal (default) / open drain mode (TX only) */
1438 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
1439 +
1440 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
1441 +#define PCR_SOF_NO_FBIT 0x00020000
1442 +
1443 +/* Drive data pins? */
1444 +#define PCR_TX_DATA_ENABLE 0x00010000
1445 +
1446 +/* Voice 56k type: drive the data pins low (default), high, high Z */
1447 +#define PCR_TX_V56K_HIGH 0x00002000
1448 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
1449 +
1450 +/* Unassigned type: drive the data pins low (default), high, high Z */
1451 +#define PCR_TX_UNASS_HIGH 0x00000800
1452 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
1453 +
1454 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
1455 +#define PCR_TX_FB_HIGH_IMP 0x00000400
1456 +
1457 +/* 56k data endiannes - which bit unused: high (default) or low */
1458 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
1459 +
1460 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
1461 +#define PCR_TX_56KS_56K_DATA 0x00000100
1462 +
1463 +/* hss_config, cCR */
1464 +/* Number of packetized clients, default = 1 */
1465 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
1466 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
1467 +
1468 +/* default = no loopback */
1469 +#define CCR_LOOPBACK 0x02000000
1470 +
1471 +/* HSS number, default = 0 (first) */
1472 +#define CCR_SECOND_HSS 0x01000000
1473 +
1474 +
1475 +/* hss_config, clkCR: main:10, num:10, denom:12 */
1476 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
1477 +
1478 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
1479 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
1480 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
1481 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
1482 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
1483 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
1484 +
1485 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
1486 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
1487 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
1488 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
1489 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
1490 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
1491 +
1492 +
1493 +/* hss_config, LUT entries */
1494 +#define TDMMAP_UNASSIGNED 0
1495 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
1496 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
1497 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
1498 +
1499 +#define TIMESLOTS 128
1500 +#define LUT_BITS 2
1501 +
1502 +/* offsets into HSS config */
1503 +#define HSS_CONFIG_TX_PCR 0x00
1504 +#define HSS_CONFIG_RX_PCR 0x04
1505 +#define HSS_CONFIG_CORE_CR 0x08
1506 +#define HSS_CONFIG_CLOCK_CR 0x0C
1507 +#define HSS_CONFIG_TX_FCR 0x10
1508 +#define HSS_CONFIG_RX_FCR 0x14
1509 +#define HSS_CONFIG_TX_LUT 0x18
1510 +#define HSS_CONFIG_RX_LUT 0x38
1511 +
1512 +
1513 +/* NPE command codes */
1514 +/* writes the ConfigWord value to the location specified by offset */
1515 +#define PORT_CONFIG_WRITE 0x40
1516 +
1517 +/* triggers the NPE to load the contents of the configuration table */
1518 +#define PORT_CONFIG_LOAD 0x41
1519 +
1520 +/* triggers the NPE to return an HssErrorReadResponse message */
1521 +#define PORT_ERROR_READ 0x42
1522 +
1523 +/* reset NPE internal status and enable the HssChannelized operation */
1524 +#define CHAN_FLOW_ENABLE 0x43
1525 +#define CHAN_FLOW_DISABLE 0x44
1526 +#define CHAN_IDLE_PATTERN_WRITE 0x45
1527 +#define CHAN_NUM_CHANS_WRITE 0x46
1528 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
1529 +#define CHAN_RX_BUF_CFG_WRITE 0x48
1530 +#define CHAN_TX_BLK_CFG_WRITE 0x49
1531 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
1532 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
1533 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
1534 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
1535 +
1536 +/* downloads the gainWord value for a timeslot switching channel associated
1537 + with bypassNum */
1538 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
1539 +
1540 +/* triggers the NPE to reset internal status and enable the HssPacketized
1541 + operation for the flow specified by pPipe */
1542 +#define PKT_PIPE_FLOW_ENABLE 0x50
1543 +#define PKT_PIPE_FLOW_DISABLE 0x51
1544 +#define PKT_NUM_PIPES_WRITE 0x52
1545 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
1546 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
1547 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
1548 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
1549 +#define PKT_PIPE_MODE_WRITE 0x57
1550 +
1551 +/* HDLC packet status values - desc->status */
1552 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
1553 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
1554 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
1555 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
1556 + this packet (if buf_len < pkt_len) */
1557 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
1558 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
1559 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
1560 +
1561 +
1562 +#ifdef __ARMEB__
1563 +typedef struct sk_buff buffer_t;
1564 +#define free_buffer dev_kfree_skb
1565 +#define free_buffer_irq dev_kfree_skb_irq
1566 +#else
1567 +typedef void buffer_t;
1568 +#define free_buffer kfree
1569 +#define free_buffer_irq kfree
1570 +#endif
1571 +
1572 +struct port {
1573 + struct npe *npe;
1574 + struct net_device *netdev;
1575 + struct hss_plat_info *plat;
1576 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1577 + struct desc *desc_tab; /* coherent */
1578 + u32 desc_tab_phys;
1579 + int id;
1580 + unsigned int clock_type, clock_rate, loopback;
1581 + u8 hdlc_cfg;
1582 +};
1583 +
1584 +/* NPE message structure */
1585 +struct msg {
1586 +#ifdef __ARMEB__
1587 + u8 cmd, unused, hss_port, index;
1588 + union {
1589 + struct { u8 data8a, data8b, data8c, data8d; };
1590 + struct { u16 data16a, data16b; };
1591 + struct { u32 data32; };
1592 + };
1593 +#else
1594 + u8 index, hss_port, unused, cmd;
1595 + union {
1596 + struct { u8 data8d, data8c, data8b, data8a; };
1597 + struct { u16 data16b, data16a; };
1598 + struct { u32 data32; };
1599 + };
1600 +#endif
1601 +};
1602 +
1603 +/* HDLC packet descriptor */
1604 +struct desc {
1605 + u32 next; /* pointer to next buffer, unused */
1606 +
1607 +#ifdef __ARMEB__
1608 + u16 buf_len; /* buffer length */
1609 + u16 pkt_len; /* packet length */
1610 + u32 data; /* pointer to data buffer in RAM */
1611 + u8 status;
1612 + u8 error_count;
1613 + u16 __reserved;
1614 +#else
1615 + u16 pkt_len; /* packet length */
1616 + u16 buf_len; /* buffer length */
1617 + u32 data; /* pointer to data buffer in RAM */
1618 + u16 __reserved;
1619 + u8 error_count;
1620 + u8 status;
1621 +#endif
1622 + u32 __reserved1[4];
1623 +};
1624 +
1625 +
1626 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1627 + (n) * sizeof(struct desc))
1628 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1629 +
1630 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1631 + ((n) + RX_DESCS) * sizeof(struct desc))
1632 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1633 +
1634 +/*****************************************************************************
1635 + * global variables
1636 + ****************************************************************************/
1637 +
1638 +static int ports_open;
1639 +static struct dma_pool *dma_pool;
1640 +
1641 +static const struct {
1642 + int tx, txdone, rx, rxfree;
1643 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
1644 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
1645 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
1646 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
1647 +};
1648 +
1649 +/*****************************************************************************
1650 + * utility functions
1651 + ****************************************************************************/
1652 +
1653 +static inline struct port* dev_to_port(struct net_device *dev)
1654 +{
1655 + return dev_to_hdlc(dev)->priv;
1656 +}
1657 +
1658 +#ifndef __ARMEB__
1659 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1660 +{
1661 + int i;
1662 + for (i = 0; i < cnt; i++)
1663 + dest[i] = swab32(src[i]);
1664 +}
1665 +#endif
1666 +
1667 +static inline void debug_pkt(struct net_device *dev, const char *func,
1668 + u8 *data, int len)
1669 +{
1670 +#if DEBUG_PKT_BYTES
1671 + int i;
1672 +
1673 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1674 + for (i = 0; i < len; i++) {
1675 + if (i >= DEBUG_PKT_BYTES)
1676 + break;
1677 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
1678 + }
1679 + printk("\n");
1680 +#endif
1681 +}
1682 +
1683 +
1684 +static inline void debug_desc(u32 phys, struct desc *desc)
1685 +{
1686 +#if DEBUG_DESC
1687 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
1688 + phys, desc->next, desc->buf_len, desc->pkt_len,
1689 + desc->data, desc->status, desc->error_count);
1690 +#endif
1691 +}
1692 +
1693 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1694 +{
1695 +#if DEBUG_QUEUES
1696 + static struct {
1697 + int queue;
1698 + char *name;
1699 + } names[] = {
1700 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
1701 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
1702 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
1703 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
1704 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
1705 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
1706 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
1707 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
1708 + };
1709 + int i;
1710 +
1711 + for (i = 0; i < ARRAY_SIZE(names); i++)
1712 + if (names[i].queue == queue)
1713 + break;
1714 +
1715 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1716 + i < ARRAY_SIZE(names) ? names[i].name : "",
1717 + is_get ? "->" : "<-", phys);
1718 +#endif
1719 +}
1720 +
1721 +static inline u32 queue_get_entry(unsigned int queue)
1722 +{
1723 + u32 phys = qmgr_get_entry(queue);
1724 + debug_queue(queue, 1, phys);
1725 + return phys;
1726 +}
1727 +
1728 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1729 + int is_tx)
1730 +{
1731 + u32 phys, tab_phys, n_desc;
1732 + struct desc *tab;
1733 +
1734 + if (!(phys = queue_get_entry(queue)))
1735 + return -1;
1736 +
1737 + BUG_ON(phys & 0x1F);
1738 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1739 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1740 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1741 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1742 + debug_desc(phys, &tab[n_desc]);
1743 + BUG_ON(tab[n_desc].next);
1744 + return n_desc;
1745 +}
1746 +
1747 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1748 + struct desc *desc)
1749 +{
1750 + debug_queue(queue, 0, phys);
1751 + debug_desc(phys, desc);
1752 + BUG_ON(phys & 0x1F);
1753 + qmgr_put_entry(queue, phys);
1754 + BUG_ON(qmgr_stat_overflow(queue));
1755 +}
1756 +
1757 +
1758 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1759 +{
1760 +#ifdef __ARMEB__
1761 + dma_unmap_single(&port->netdev->dev, desc->data,
1762 + desc->buf_len, DMA_TO_DEVICE);
1763 +#else
1764 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1765 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1766 + DMA_TO_DEVICE);
1767 +#endif
1768 +}
1769 +
1770 +
1771 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
1772 +{
1773 + struct net_device *dev = pdev;
1774 + if (carrier)
1775 + netif_carrier_on(dev);
1776 + else
1777 + netif_carrier_off(dev);
1778 +}
1779 +
1780 +static void hss_hdlc_rx_irq(void *pdev)
1781 +{
1782 + struct net_device *dev = pdev;
1783 + struct port *port = dev_to_port(dev);
1784 +
1785 +#if DEBUG_RX
1786 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
1787 +#endif
1788 + qmgr_disable_irq(queue_ids[port->id].rx);
1789 + netif_rx_schedule(dev);
1790 +}
1791 +
1792 +static int hss_hdlc_poll(struct net_device *dev, int *budget)
1793 +{
1794 + struct port *port = dev_to_port(dev);
1795 + unsigned int rxq = queue_ids[port->id].rx;
1796 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
1797 + struct net_device_stats *stats = hdlc_stats(dev);
1798 + int quota = dev->quota, received = 0;
1799 +
1800 +#if DEBUG_RX
1801 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
1802 +#endif
1803 +
1804 + while (quota) {
1805 + struct sk_buff *skb;
1806 + struct desc *desc;
1807 + int n;
1808 +#ifdef __ARMEB__
1809 + struct sk_buff *temp;
1810 + u32 phys;
1811 +#endif
1812 +
1813 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1814 + dev->quota -= received; /* No packet received */
1815 + *budget -= received;
1816 + received = 0;
1817 +#if DEBUG_RX
1818 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1819 + " netif_rx_complete\n", dev->name);
1820 +#endif
1821 + netif_rx_complete(dev);
1822 + qmgr_enable_irq(rxq);
1823 + if (!qmgr_stat_empty(rxq) &&
1824 + netif_rx_reschedule(dev, 0)) {
1825 +#if DEBUG_RX
1826 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1827 + " netif_rx_reschedule successed\n",
1828 + dev->name);
1829 +#endif
1830 + qmgr_disable_irq(rxq);
1831 + continue;
1832 + }
1833 +#if DEBUG_RX
1834 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
1835 + dev->name);
1836 +#endif
1837 + return 0; /* all work done */
1838 + }
1839 +
1840 + desc = rx_desc_ptr(port, n);
1841 +
1842 + if (desc->error_count) /* FIXME - remove printk */
1843 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
1844 + " errors %u\n", dev->name, desc->status,
1845 + desc->error_count);
1846 +
1847 + skb = NULL;
1848 + switch (desc->status) {
1849 + case 0:
1850 +#ifdef __ARMEB__
1851 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
1852 + phys = dma_map_single(&dev->dev, skb->data,
1853 + RX_SIZE,
1854 + DMA_FROM_DEVICE);
1855 + if (dma_mapping_error(phys)) {
1856 + dev_kfree_skb(skb);
1857 + skb = NULL;
1858 + }
1859 + }
1860 +#else
1861 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1862 +#endif
1863 + if (!skb)
1864 + stats->rx_dropped++;
1865 + break;
1866 + case ERR_HDLC_ALIGN:
1867 + case ERR_HDLC_ABORT:
1868 + stats->rx_frame_errors++;
1869 + stats->rx_errors++;
1870 + break;
1871 + case ERR_HDLC_FCS:
1872 + stats->rx_crc_errors++;
1873 + stats->rx_errors++;
1874 + break;
1875 + case ERR_HDLC_TOO_LONG:
1876 + stats->rx_length_errors++;
1877 + stats->rx_errors++;
1878 + break;
1879 + default: /* FIXME - remove printk */
1880 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
1881 + " errors %u\n", dev->name, desc->status,
1882 + desc->error_count);
1883 + stats->rx_errors++;
1884 + }
1885 +
1886 + if (!skb) {
1887 + /* put the desc back on RX-ready queue */
1888 + desc->buf_len = RX_SIZE;
1889 + desc->pkt_len = desc->status = 0;
1890 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1891 + continue;
1892 + }
1893 +
1894 + /* process received frame */
1895 +#ifdef __ARMEB__
1896 + temp = skb;
1897 + skb = port->rx_buff_tab[n];
1898 + dma_unmap_single(&dev->dev, desc->data,
1899 + RX_SIZE, DMA_FROM_DEVICE);
1900 +#else
1901 + dma_sync_single(&dev->dev, desc->data,
1902 + RX_SIZE, DMA_FROM_DEVICE);
1903 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1904 + ALIGN(desc->pkt_len, 4) / 4);
1905 +#endif
1906 + skb_put(skb, desc->pkt_len);
1907 +
1908 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
1909 +
1910 + skb->protocol = hdlc_type_trans(skb, dev);
1911 + dev->last_rx = jiffies;
1912 + stats->rx_packets++;
1913 + stats->rx_bytes += skb->len;
1914 + netif_receive_skb(skb);
1915 +
1916 + /* put the new buffer on RX-free queue */
1917 +#ifdef __ARMEB__
1918 + port->rx_buff_tab[n] = temp;
1919 + desc->data = phys;
1920 +#endif
1921 + desc->buf_len = RX_SIZE;
1922 + desc->pkt_len = 0;
1923 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1924 + quota--;
1925 + received++;
1926 + }
1927 + dev->quota -= received;
1928 + *budget -= received;
1929 +#if DEBUG_RX
1930 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
1931 +#endif
1932 + return 1; /* not all work done */
1933 +}
1934 +
1935 +
1936 +static void hss_hdlc_txdone_irq(void *pdev)
1937 +{
1938 + struct net_device *dev = pdev;
1939 + struct port *port = dev_to_port(dev);
1940 + struct net_device_stats *stats = hdlc_stats(dev);
1941 + int n_desc;
1942 +
1943 +#if DEBUG_TX
1944 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
1945 +#endif
1946 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
1947 + port, 1)) >= 0) {
1948 + struct desc *desc;
1949 + int start;
1950 +
1951 + desc = tx_desc_ptr(port, n_desc);
1952 +
1953 + stats->tx_packets++;
1954 + stats->tx_bytes += desc->pkt_len;
1955 +
1956 + dma_unmap_tx(port, desc);
1957 +#if DEBUG_TX
1958 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
1959 + port->netdev->name, port->tx_buff_tab[n_desc]);
1960 +#endif
1961 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1962 + port->tx_buff_tab[n_desc] = NULL;
1963 +
1964 + start = qmgr_stat_empty(port->plat->txreadyq);
1965 + queue_put_desc(port->plat->txreadyq,
1966 + tx_desc_phys(port, n_desc), desc);
1967 + if (start) {
1968 +#if DEBUG_TX
1969 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
1970 + " ready\n", port->netdev->name);
1971 +#endif
1972 + netif_wake_queue(port->netdev);
1973 + }
1974 + }
1975 +}
1976 +
1977 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
1978 +{
1979 + struct port *port = dev_to_port(dev);
1980 + struct net_device_stats *stats = hdlc_stats(dev);
1981 + unsigned int txreadyq = port->plat->txreadyq;
1982 + int len, offset, bytes, n;
1983 + void *mem;
1984 + u32 phys;
1985 + struct desc *desc;
1986 +
1987 +#if DEBUG_TX
1988 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
1989 +#endif
1990 +
1991 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
1992 + dev_kfree_skb(skb);
1993 + stats->tx_errors++;
1994 + return NETDEV_TX_OK;
1995 + }
1996 +
1997 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
1998 +
1999 + len = skb->len;
2000 +#ifdef __ARMEB__
2001 + offset = 0; /* no need to keep alignment */
2002 + bytes = len;
2003 + mem = skb->data;
2004 +#else
2005 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
2006 + bytes = ALIGN(offset + len, 4);
2007 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
2008 + dev_kfree_skb(skb);
2009 + stats->tx_dropped++;
2010 + return NETDEV_TX_OK;
2011 + }
2012 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
2013 + dev_kfree_skb(skb);
2014 +#endif
2015 +
2016 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
2017 + if (dma_mapping_error(phys)) {
2018 +#ifdef __ARMEB__
2019 + dev_kfree_skb(skb);
2020 +#else
2021 + kfree(mem);
2022 +#endif
2023 + stats->tx_dropped++;
2024 + return NETDEV_TX_OK;
2025 + }
2026 +
2027 + n = queue_get_desc(txreadyq, port, 1);
2028 + BUG_ON(n < 0);
2029 + desc = tx_desc_ptr(port, n);
2030 +
2031 +#ifdef __ARMEB__
2032 + port->tx_buff_tab[n] = skb;
2033 +#else
2034 + port->tx_buff_tab[n] = mem;
2035 +#endif
2036 + desc->data = phys + offset;
2037 + desc->buf_len = desc->pkt_len = len;
2038 +
2039 + wmb();
2040 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
2041 + dev->trans_start = jiffies;
2042 +
2043 + if (qmgr_stat_empty(txreadyq)) {
2044 +#if DEBUG_TX
2045 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
2046 +#endif
2047 + netif_stop_queue(dev);
2048 + /* we could miss TX ready interrupt */
2049 + if (!qmgr_stat_empty(txreadyq)) {
2050 +#if DEBUG_TX
2051 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
2052 + dev->name);
2053 +#endif
2054 + netif_wake_queue(dev);
2055 + }
2056 + }
2057 +
2058 +#if DEBUG_TX
2059 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
2060 +#endif
2061 + return NETDEV_TX_OK;
2062 +}
2063 +
2064 +
2065 +static int request_hdlc_queues(struct port *port)
2066 +{
2067 + int err;
2068 +
2069 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
2070 + if (err)
2071 + return err;
2072 +
2073 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
2074 + if (err)
2075 + goto rel_rxfree;
2076 +
2077 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
2078 + if (err)
2079 + goto rel_rx;
2080 +
2081 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
2082 + if (err)
2083 + goto rel_tx;
2084 +
2085 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
2086 + if (err)
2087 + goto rel_txready;
2088 + return 0;
2089 +
2090 +rel_txready:
2091 + qmgr_release_queue(port->plat->txreadyq);
2092 +rel_tx:
2093 + qmgr_release_queue(queue_ids[port->id].tx);
2094 +rel_rx:
2095 + qmgr_release_queue(queue_ids[port->id].rx);
2096 +rel_rxfree:
2097 + qmgr_release_queue(queue_ids[port->id].rxfree);
2098 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
2099 + port->netdev->name);
2100 + return err;
2101 +}
2102 +
2103 +static void release_hdlc_queues(struct port *port)
2104 +{
2105 + qmgr_release_queue(queue_ids[port->id].rxfree);
2106 + qmgr_release_queue(queue_ids[port->id].rx);
2107 + qmgr_release_queue(queue_ids[port->id].txdone);
2108 + qmgr_release_queue(queue_ids[port->id].tx);
2109 + qmgr_release_queue(port->plat->txreadyq);
2110 +}
2111 +
2112 +static int init_hdlc_queues(struct port *port)
2113 +{
2114 + int i;
2115 +
2116 + if (!ports_open)
2117 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
2118 + POOL_ALLOC_SIZE, 32, 0)))
2119 + return -ENOMEM;
2120 +
2121 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
2122 + &port->desc_tab_phys)))
2123 + return -ENOMEM;
2124 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2125 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2126 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2127 +
2128 + /* Setup RX buffers */
2129 + for (i = 0; i < RX_DESCS; i++) {
2130 + struct desc *desc = rx_desc_ptr(port, i);
2131 + buffer_t *buff;
2132 + void *data;
2133 +#ifdef __ARMEB__
2134 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
2135 + return -ENOMEM;
2136 + data = buff->data;
2137 +#else
2138 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
2139 + return -ENOMEM;
2140 + data = buff;
2141 +#endif
2142 + desc->buf_len = RX_SIZE;
2143 + desc->data = dma_map_single(&port->netdev->dev, data,
2144 + RX_SIZE, DMA_FROM_DEVICE);
2145 + if (dma_mapping_error(desc->data)) {
2146 + free_buffer(buff);
2147 + return -EIO;
2148 + }
2149 + port->rx_buff_tab[i] = buff;
2150 + }
2151 +
2152 + return 0;
2153 +}
2154 +
2155 +static void destroy_hdlc_queues(struct port *port)
2156 +{
2157 + int i;
2158 +
2159 + if (port->desc_tab) {
2160 + for (i = 0; i < RX_DESCS; i++) {
2161 + struct desc *desc = rx_desc_ptr(port, i);
2162 + buffer_t *buff = port->rx_buff_tab[i];
2163 + if (buff) {
2164 + dma_unmap_single(&port->netdev->dev,
2165 + desc->data, RX_SIZE,
2166 + DMA_FROM_DEVICE);
2167 + free_buffer(buff);
2168 + }
2169 + }
2170 + for (i = 0; i < TX_DESCS; i++) {
2171 + struct desc *desc = tx_desc_ptr(port, i);
2172 + buffer_t *buff = port->tx_buff_tab[i];
2173 + if (buff) {
2174 + dma_unmap_tx(port, desc);
2175 + free_buffer(buff);
2176 + }
2177 + }
2178 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2179 + port->desc_tab = NULL;
2180 + }
2181 +
2182 + if (!ports_open && dma_pool) {
2183 + dma_pool_destroy(dma_pool);
2184 + dma_pool = NULL;
2185 + }
2186 +}
2187 +
2188 +static int hss_hdlc_open(struct net_device *dev)
2189 +{
2190 + struct port *port = dev_to_port(dev);
2191 + struct npe *npe = port->npe;
2192 + struct msg msg;
2193 + int i, err;
2194 +
2195 + if (!npe_running(npe)) {
2196 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2197 + if (err)
2198 + return err;
2199 + }
2200 +
2201 + if ((err = hdlc_open(dev)) != 0)
2202 + return err;
2203 +
2204 + if (port->plat->open)
2205 + if ((err = port->plat->open(port->id, port->netdev,
2206 + hss_hdlc_set_carrier)) != 0)
2207 + goto err_hdlc_close;
2208 +
2209 + /* HSS main configuration */
2210 + memset(&msg, 0, sizeof(msg));
2211 + msg.cmd = PORT_CONFIG_WRITE;
2212 + msg.hss_port = port->id;
2213 + msg.index = 0; /* offset in HSS config */
2214 +
2215 + msg.data32 = PCR_FRM_PULSE_DISABLED |
2216 + PCR_SOF_NO_FBIT |
2217 + PCR_MSB_ENDIAN |
2218 + PCR_TX_DATA_ENABLE;
2219 +
2220 + if (port->clock_type == CLOCK_INT)
2221 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
2222 +
2223 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
2224 + goto err_plat_close; /* 0: TX PCR */
2225 +
2226 + msg.index = 4;
2227 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
2228 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
2229 + goto err_plat_close; /* 4: RX PCR */
2230 +
2231 + msg.index = 8;
2232 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
2233 + (port->id ? CCR_SECOND_HSS : 0);
2234 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
2235 + goto err_plat_close; /* 8: Core CR */
2236 +
2237 + msg.index = 12;
2238 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
2239 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
2240 + goto err_plat_close; /* 12: CLK CR */
2241 +
2242 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
2243 + msg.index = 16;
2244 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
2245 + goto err_plat_close; /* 16: TX FCR */
2246 +
2247 + msg.index = 20;
2248 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
2249 + goto err_plat_close; /* 20: RX FCR */
2250 +
2251 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
2252 + for (i = 0; i < 32 / LUT_BITS; i++)
2253 + msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i);
2254 +
2255 + for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) {
2256 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
2257 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
2258 + goto err_plat_close;
2259 + }
2260 +
2261 + /* HDLC mode configuration */
2262 + memset(&msg, 0, sizeof(msg));
2263 + msg.cmd = PKT_NUM_PIPES_WRITE;
2264 + msg.hss_port = port->id;
2265 + msg.data8a = PKT_NUM_PIPES;
2266 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
2267 + goto err_plat_close;
2268 +
2269 + memset(&msg, 0, sizeof(msg));
2270 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
2271 + msg.hss_port = port->id;
2272 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
2273 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
2274 + goto err_plat_close;
2275 +
2276 + memset(&msg, 0, sizeof(msg));
2277 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
2278 + msg.hss_port = port->id;
2279 + msg.data32 = 0x7F7F7F7F;
2280 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
2281 + goto err_plat_close;
2282 +
2283 + memset(&msg, 0, sizeof(msg));
2284 + msg.cmd = PORT_CONFIG_LOAD;
2285 + msg.hss_port = port->id;
2286 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
2287 + goto err_plat_close;
2288 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
2289 + goto err_plat_close;
2290 +
2291 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
2292 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
2293 + printk(KERN_DEBUG "%s: unexpected message received in"
2294 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
2295 + err = EIO;
2296 + goto err_plat_close;
2297 + }
2298 +
2299 + memset(&msg, 0, sizeof(msg));
2300 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
2301 + msg.hss_port = port->id;
2302 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
2303 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
2304 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
2305 + goto err_plat_close;
2306 +
2307 + memset(&msg, 0, sizeof(msg));
2308 + msg.cmd = PKT_PIPE_MODE_WRITE;
2309 + msg.hss_port = port->id;
2310 + msg.data8a = NPE_PKT_MODE_HDLC;
2311 + /* msg.data8b = inv_mask */
2312 + /* msg.data8c = or_mask */
2313 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
2314 + goto err_plat_close;
2315 +
2316 + memset(&msg, 0, sizeof(msg));
2317 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
2318 + msg.hss_port = port->id;
2319 + msg.data16a = HDLC_MAX_MRU;
2320 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
2321 + goto err_plat_close;
2322 +
2323 + if ((err = request_hdlc_queues(port)) != 0)
2324 + goto err_plat_close;
2325 +
2326 + if ((err = init_hdlc_queues(port)) != 0)
2327 + goto err_destroy_queues;
2328 +
2329 + memset(&msg, 0, sizeof(msg));
2330 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
2331 + msg.hss_port = port->id;
2332 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
2333 + goto err_destroy_queues;
2334 +
2335 + /* Populate queues with buffers, no failure after this point */
2336 + for (i = 0; i < TX_DESCS; i++)
2337 + queue_put_desc(port->plat->txreadyq,
2338 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2339 +
2340 + for (i = 0; i < RX_DESCS; i++)
2341 + queue_put_desc(queue_ids[port->id].rxfree,
2342 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2343 +
2344 + netif_start_queue(dev);
2345 +
2346 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
2347 + hss_hdlc_rx_irq, dev);
2348 +
2349 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
2350 + hss_hdlc_txdone_irq, dev);
2351 + qmgr_enable_irq(queue_ids[port->id].txdone);
2352 +
2353 + ports_open++;
2354 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2355 + return 0;
2356 +
2357 +err_destroy_queues:
2358 + destroy_hdlc_queues(port);
2359 + release_hdlc_queues(port);
2360 +err_plat_close:
2361 + if (port->plat->close)
2362 + port->plat->close(port->id, port->netdev);
2363 +err_hdlc_close:
2364 + hdlc_close(dev);
2365 + return err;
2366 +}
2367 +
2368 +static int hss_hdlc_close(struct net_device *dev)
2369 +{
2370 + struct port *port = dev_to_port(dev);
2371 + struct npe *npe = port->npe;
2372 + struct msg msg;
2373 + int buffs = RX_DESCS; /* allocated RX buffers */
2374 + int i;
2375 +
2376 + ports_open--;
2377 + qmgr_disable_irq(queue_ids[port->id].rx);
2378 + netif_stop_queue(dev);
2379 +
2380 + memset(&msg, 0, sizeof(msg));
2381 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
2382 + msg.hss_port = port->id;
2383 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
2384 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
2385 + port->id);
2386 + /* The upper level would ignore the error anyway */
2387 + }
2388 +
2389 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
2390 + buffs--;
2391 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
2392 + buffs--;
2393 +
2394 + if (buffs)
2395 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2396 + " left in NPE\n", dev->name, buffs);
2397 +
2398 + buffs = TX_DESCS;
2399 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
2400 + buffs--; /* cancel TX */
2401 +
2402 + i = 0;
2403 + do {
2404 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2405 + buffs--;
2406 + if (!buffs)
2407 + break;
2408 + } while (++i < MAX_CLOSE_WAIT);
2409 +
2410 + if (buffs)
2411 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2412 + "left in NPE\n", dev->name, buffs);
2413 +#if DEBUG_CLOSE
2414 + if (!buffs)
2415 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2416 +#endif
2417 + qmgr_disable_irq(queue_ids[port->id].txdone);
2418 + destroy_hdlc_queues(port);
2419 + release_hdlc_queues(port);
2420 +
2421 + if (port->plat->close)
2422 + port->plat->close(port->id, port->netdev);
2423 + hdlc_close(dev);
2424 + return 0;
2425 +}
2426 +
2427 +
2428 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
2429 + unsigned short parity)
2430 +{
2431 + struct port *port = dev_to_port(dev);
2432 +
2433 + if (encoding != ENCODING_NRZ)
2434 + return -EINVAL;
2435 +
2436 + switch(parity) {
2437 + case PARITY_CRC16_PR1_CCITT:
2438 + port->hdlc_cfg = 0;
2439 + return 0;
2440 +
2441 + case PARITY_CRC32_PR1_CCITT:
2442 + port->hdlc_cfg = PKT_HDLC_CRC_32;
2443 + return 0;
2444 +
2445 + default:
2446 + return -EINVAL;
2447 + }
2448 +}
2449 +
2450 +
2451 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2452 +{
2453 + const size_t size = sizeof(sync_serial_settings);
2454 + sync_serial_settings new_line;
2455 + int clk;
2456 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
2457 + struct port *port = dev_to_port(dev);
2458 +
2459 + if (cmd != SIOCWANDEV)
2460 + return hdlc_ioctl(dev, ifr, cmd);
2461 +
2462 + switch(ifr->ifr_settings.type) {
2463 + case IF_GET_IFACE:
2464 + ifr->ifr_settings.type = IF_IFACE_V35;
2465 + if (ifr->ifr_settings.size < size) {
2466 + ifr->ifr_settings.size = size; /* data size wanted */
2467 + return -ENOBUFS;
2468 + }
2469 + memset(&new_line, 0, sizeof(new_line));
2470 + new_line.clock_type = port->clock_type;
2471 + new_line.clock_rate = port->clock_rate;
2472 + new_line.loopback = port->loopback;
2473 + if (copy_to_user(line, &new_line, size))
2474 + return -EFAULT;
2475 + return 0;
2476 +
2477 + case IF_IFACE_SYNC_SERIAL:
2478 + case IF_IFACE_V35:
2479 + if(!capable(CAP_NET_ADMIN))
2480 + return -EPERM;
2481 + if (dev->flags & IFF_UP)
2482 + return -EBUSY; /* Cannot change parameters when open */
2483 +
2484 + if (copy_from_user(&new_line, line, size))
2485 + return -EFAULT;
2486 +
2487 + clk = new_line.clock_type;
2488 + if (port->plat->set_clock)
2489 + clk = port->plat->set_clock(port->id, clk);
2490 +
2491 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
2492 + return -EINVAL; /* No such clock setting */
2493 +
2494 + if (new_line.loopback != 0 && new_line.loopback != 1)
2495 + return -EINVAL;
2496 +
2497 + port->clock_type = clk; /* Update settings */
2498 + port->clock_rate = new_line.clock_rate;
2499 + port->loopback = new_line.loopback;
2500 + return 0;
2501 +
2502 + default:
2503 + return hdlc_ioctl(dev, ifr, cmd);
2504 + }
2505 +}
2506 +
2507 +
2508 +static int __devinit hss_init_one(struct platform_device *pdev)
2509 +{
2510 + struct port *port;
2511 + struct net_device *dev;
2512 + hdlc_device *hdlc;
2513 + int err;
2514 +
2515 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
2516 + return -ENOMEM;
2517 + platform_set_drvdata(pdev, port);
2518 + port->id = pdev->id;
2519 +
2520 + if ((port->npe = npe_request(0)) == NULL) {
2521 + err = -ENOSYS;
2522 + goto err_free;
2523 + }
2524 +
2525 + port->plat = pdev->dev.platform_data;
2526 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
2527 + err = -ENOMEM;
2528 + goto err_plat;
2529 + }
2530 +
2531 + SET_MODULE_OWNER(net);
2532 + SET_NETDEV_DEV(dev, &pdev->dev);
2533 + hdlc = dev_to_hdlc(dev);
2534 + hdlc->attach = hss_hdlc_attach;
2535 + hdlc->xmit = hss_hdlc_xmit;
2536 + dev->open = hss_hdlc_open;
2537 + dev->poll = hss_hdlc_poll;
2538 + dev->stop = hss_hdlc_close;
2539 + dev->do_ioctl = hss_hdlc_ioctl;
2540 + dev->weight = 16;
2541 + dev->tx_queue_len = 100;
2542 + port->clock_type = CLOCK_EXT;
2543 + port->clock_rate = 2048000;
2544 +
2545 + if (register_hdlc_device(dev)) {
2546 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
2547 + port->id);
2548 + err = -ENOBUFS;
2549 + goto err_free_netdev;
2550 + }
2551 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
2552 + return 0;
2553 +
2554 +err_free_netdev:
2555 + free_netdev(dev);
2556 +err_plat:
2557 + npe_release(port->npe);
2558 + platform_set_drvdata(pdev, NULL);
2559 +err_free:
2560 + kfree(port);
2561 + return err;
2562 +}
2563 +
2564 +static int __devexit hss_remove_one(struct platform_device *pdev)
2565 +{
2566 + struct port *port = platform_get_drvdata(pdev);
2567 +
2568 + unregister_hdlc_device(port->netdev);
2569 + free_netdev(port->netdev);
2570 + npe_release(port->npe);
2571 + platform_set_drvdata(pdev, NULL);
2572 + kfree(port);
2573 + return 0;
2574 +}
2575 +
2576 +static struct platform_driver drv = {
2577 + .driver.name = DRV_NAME,
2578 + .probe = hss_init_one,
2579 + .remove = hss_remove_one,
2580 +};
2581 +
2582 +static int __init hss_init_module(void)
2583 +{
2584 + if ((ixp4xx_read_feature_bits() &
2585 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
2586 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
2587 + return -ENOSYS;
2588 + return platform_driver_register(&drv);
2589 +}
2590 +
2591 +static void __exit hss_cleanup_module(void)
2592 +{
2593 + platform_driver_unregister(&drv);
2594 +}
2595 +
2596 +MODULE_AUTHOR("Krzysztof Halasa");
2597 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
2598 +MODULE_LICENSE("GPL v2");
2599 +module_init(hss_init_module);
2600 +module_exit(hss_cleanup_module);
2601 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2602 ===================================================================
2603 --- linux-2.6.24.7.orig/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2604 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2605 @@ -15,10 +15,6 @@
2606 *
2607 */
2608
2609 -#ifndef __ASM_ARCH_HARDWARE_H__
2610 -#error "Do not include this directly, instead #include <asm/hardware.h>"
2611 -#endif
2612 -
2613 #ifndef _ASM_ARM_IXP4XX_H_
2614 #define _ASM_ARM_IXP4XX_H_
2615
2616 @@ -607,4 +603,36 @@
2617
2618 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
2619
2620 +/* "fuse" bits of IXP_EXP_CFG2 */
2621 +#define IXP4XX_FEATURE_RCOMP (1 << 0)
2622 +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
2623 +#define IXP4XX_FEATURE_HASH (1 << 2)
2624 +#define IXP4XX_FEATURE_AES (1 << 3)
2625 +#define IXP4XX_FEATURE_DES (1 << 4)
2626 +#define IXP4XX_FEATURE_HDLC (1 << 5)
2627 +#define IXP4XX_FEATURE_AAL (1 << 6)
2628 +#define IXP4XX_FEATURE_HSS (1 << 7)
2629 +#define IXP4XX_FEATURE_UTOPIA (1 << 8)
2630 +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
2631 +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
2632 +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
2633 +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
2634 +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
2635 +#define IXP4XX_FEATURE_PCI (1 << 14)
2636 +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
2637 +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
2638 +#define IXP4XX_FEATURE_USB_HOST (1 << 18)
2639 +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
2640 +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
2641 +#define IXP4XX_FEATURE_RSA (1 << 21)
2642 +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
2643 +#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
2644 +
2645 +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
2646 + IXP4XX_FEATURE_USB_HOST | \
2647 + IXP4XX_FEATURE_NPEA_ETH | \
2648 + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
2649 + IXP4XX_FEATURE_RSA | \
2650 + IXP4XX_FEATURE_XSCALE_MAX_FREQ)
2651 +
2652 #endif
2653 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/cpu.h
2654 ===================================================================
2655 --- linux-2.6.24.7.orig/include/asm-arm/arch-ixp4xx/cpu.h
2656 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/cpu.h
2657 @@ -28,4 +28,19 @@ extern unsigned int processor_id;
2658 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
2659 IXP465_PROCESSOR_ID_VALUE)
2660
2661 +static inline u32 ixp4xx_read_feature_bits(void)
2662 +{
2663 + unsigned int val = ~*IXP4XX_EXP_CFG2;
2664 + val &= ~IXP4XX_FEATURE_RESERVED;
2665 + if (!cpu_is_ixp46x())
2666 + val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
2667 +
2668 + return val;
2669 +}
2670 +
2671 +static inline void ixp4xx_write_feature_bits(u32 value)
2672 +{
2673 + *IXP4XX_EXP_CFG2 = ~value;
2674 +}
2675 +
2676 #endif /* _ASM_ARCH_CPU_H */
2677 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/hardware.h
2678 ===================================================================
2679 --- linux-2.6.24.7.orig/include/asm-arm/arch-ixp4xx/hardware.h
2680 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/hardware.h
2681 @@ -27,13 +27,13 @@
2682
2683 #define pcibios_assign_all_busses() 1
2684
2685 +/* Register locations and bits */
2686 +#include "ixp4xx-regs.h"
2687 +
2688 #ifndef __ASSEMBLER__
2689 #include <asm/arch/cpu.h>
2690 #endif
2691
2692 -/* Register locations and bits */
2693 -#include "ixp4xx-regs.h"
2694 -
2695 /* Platform helper functions and definitions */
2696 #include "platform.h"
2697
2698 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/uncompress.h
2699 ===================================================================
2700 --- linux-2.6.24.7.orig/include/asm-arm/arch-ixp4xx/uncompress.h
2701 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/uncompress.h
2702 @@ -13,7 +13,7 @@
2703 #ifndef _ARCH_UNCOMPRESS_H_
2704 #define _ARCH_UNCOMPRESS_H_
2705
2706 -#include <asm/hardware.h>
2707 +#include "ixp4xx-regs.h"
2708 #include <asm/mach-types.h>
2709 #include <linux/serial_reg.h>
2710
2711 Index: linux-2.6.24.7/arch/arm/kernel/setup.c
2712 ===================================================================
2713 --- linux-2.6.24.7.orig/arch/arm/kernel/setup.c
2714 +++ linux-2.6.24.7/arch/arm/kernel/setup.c
2715 @@ -62,6 +62,7 @@ extern int root_mountflags;
2716 extern void _stext, _text, _etext, __data_start, _edata, _end;
2717
2718 unsigned int processor_id;
2719 +EXPORT_SYMBOL(processor_id);
2720 unsigned int __machine_arch_type;
2721 EXPORT_SYMBOL(__machine_arch_type);
2722
2723 Index: linux-2.6.24.7/arch/arm/mach-ixp4xx/Kconfig
2724 ===================================================================
2725 --- linux-2.6.24.7.orig/arch/arm/mach-ixp4xx/Kconfig
2726 +++ linux-2.6.24.7/arch/arm/mach-ixp4xx/Kconfig
2727 @@ -262,6 +262,20 @@ config IXP4XX_INDIRECT_PCI
2728 need to use the indirect method instead. If you don't know
2729 what you need, leave this option unselected.
2730
2731 +config IXP4XX_QMGR
2732 + tristate "IXP4xx Queue Manager support"
2733 + help
2734 + This driver supports IXP4xx built-in hardware queue manager
2735 + and is automatically selected by Ethernet and HSS drivers.
2736 +
2737 +config IXP4XX_NPE
2738 + tristate "IXP4xx Network Processor Engine support"
2739 + select HOTPLUG
2740 + select FW_LOADER
2741 + help
2742 + This driver supports IXP4xx built-in network coprocessors
2743 + and is automatically selected by Ethernet and HSS drivers.
2744 +
2745 endmenu
2746
2747 endif
2748 Index: linux-2.6.24.7/arch/arm/mach-ixp4xx/Makefile
2749 ===================================================================
2750 --- linux-2.6.24.7.orig/arch/arm/mach-ixp4xx/Makefile
2751 +++ linux-2.6.24.7/arch/arm/mach-ixp4xx/Makefile
2752 @@ -48,3 +48,5 @@ obj-$(CONFIG_MACH_AP1000) += ap1000-setu
2753 obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
2754
2755 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
2756 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
2757 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
2758 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/qmgr.h
2759 ===================================================================
2760 --- /dev/null
2761 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/qmgr.h
2762 @@ -0,0 +1,126 @@
2763 +/*
2764 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2765 + *
2766 + * This program is free software; you can redistribute it and/or modify it
2767 + * under the terms of version 2 of the GNU General Public License
2768 + * as published by the Free Software Foundation.
2769 + */
2770 +
2771 +#ifndef IXP4XX_QMGR_H
2772 +#define IXP4XX_QMGR_H
2773 +
2774 +#include <linux/io.h>
2775 +#include <linux/kernel.h>
2776 +
2777 +#define HALF_QUEUES 32
2778 +#define QUEUES 64 /* only 32 lower queues currently supported */
2779 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
2780 +
2781 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
2782 +#define QUEUE_STAT1_NEARLY_EMPTY 2
2783 +#define QUEUE_STAT1_NEARLY_FULL 4
2784 +#define QUEUE_STAT1_FULL 8
2785 +#define QUEUE_STAT2_UNDERFLOW 1
2786 +#define QUEUE_STAT2_OVERFLOW 2
2787 +
2788 +#define QUEUE_WATERMARK_0_ENTRIES 0
2789 +#define QUEUE_WATERMARK_1_ENTRY 1
2790 +#define QUEUE_WATERMARK_2_ENTRIES 2
2791 +#define QUEUE_WATERMARK_4_ENTRIES 3
2792 +#define QUEUE_WATERMARK_8_ENTRIES 4
2793 +#define QUEUE_WATERMARK_16_ENTRIES 5
2794 +#define QUEUE_WATERMARK_32_ENTRIES 6
2795 +#define QUEUE_WATERMARK_64_ENTRIES 7
2796 +
2797 +/* queue interrupt request conditions */
2798 +#define QUEUE_IRQ_SRC_EMPTY 0
2799 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
2800 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
2801 +#define QUEUE_IRQ_SRC_FULL 3
2802 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
2803 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
2804 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
2805 +#define QUEUE_IRQ_SRC_NOT_FULL 7
2806 +
2807 +struct qmgr_regs {
2808 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
2809 + u32 stat1[4]; /* 0x400 - 0x40F */
2810 + u32 stat2[2]; /* 0x410 - 0x417 */
2811 + u32 statne_h; /* 0x418 - queue nearly empty */
2812 + u32 statf_h; /* 0x41C - queue full */
2813 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
2814 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
2815 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
2816 + u32 reserved[1776];
2817 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
2818 +};
2819 +
2820 +void qmgr_set_irq(unsigned int queue, int src,
2821 + void (*handler)(void *pdev), void *pdev);
2822 +void qmgr_enable_irq(unsigned int queue);
2823 +void qmgr_disable_irq(unsigned int queue);
2824 +
2825 +/* request_ and release_queue() must be called from non-IRQ context */
2826 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
2827 + unsigned int nearly_empty_watermark,
2828 + unsigned int nearly_full_watermark);
2829 +void qmgr_release_queue(unsigned int queue);
2830 +
2831 +
2832 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
2833 +{
2834 + extern struct qmgr_regs __iomem *qmgr_regs;
2835 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
2836 +}
2837 +
2838 +static inline u32 qmgr_get_entry(unsigned int queue)
2839 +{
2840 + extern struct qmgr_regs __iomem *qmgr_regs;
2841 + return __raw_readl(&qmgr_regs->acc[queue][0]);
2842 +}
2843 +
2844 +static inline int qmgr_get_stat1(unsigned int queue)
2845 +{
2846 + extern struct qmgr_regs __iomem *qmgr_regs;
2847 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
2848 + >> ((queue & 7) << 2)) & 0xF;
2849 +}
2850 +
2851 +static inline int qmgr_get_stat2(unsigned int queue)
2852 +{
2853 + extern struct qmgr_regs __iomem *qmgr_regs;
2854 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
2855 + >> ((queue & 0xF) << 1)) & 0x3;
2856 +}
2857 +
2858 +static inline int qmgr_stat_empty(unsigned int queue)
2859 +{
2860 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
2861 +}
2862 +
2863 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
2864 +{
2865 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
2866 +}
2867 +
2868 +static inline int qmgr_stat_nearly_full(unsigned int queue)
2869 +{
2870 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
2871 +}
2872 +
2873 +static inline int qmgr_stat_full(unsigned int queue)
2874 +{
2875 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
2876 +}
2877 +
2878 +static inline int qmgr_stat_underflow(unsigned int queue)
2879 +{
2880 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
2881 +}
2882 +
2883 +static inline int qmgr_stat_overflow(unsigned int queue)
2884 +{
2885 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
2886 +}
2887 +
2888 +#endif
2889 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/npe.h
2890 ===================================================================
2891 --- /dev/null
2892 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/npe.h
2893 @@ -0,0 +1,39 @@
2894 +#ifndef __IXP4XX_NPE_H
2895 +#define __IXP4XX_NPE_H
2896 +
2897 +#include <linux/kernel.h>
2898 +
2899 +extern const char *npe_names[];
2900 +
2901 +struct npe_regs {
2902 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
2903 + u32 action_points[4];
2904 + u32 watchpoint_fifo, watch_count;
2905 + u32 profile_count;
2906 + u32 messaging_status, messaging_control;
2907 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
2908 +};
2909 +
2910 +struct npe {
2911 + struct resource *mem_res;
2912 + struct npe_regs __iomem *regs;
2913 + u32 regs_phys;
2914 + int id;
2915 + int valid;
2916 +};
2917 +
2918 +
2919 +static inline const char *npe_name(struct npe *npe)
2920 +{
2921 + return npe_names[npe->id];
2922 +}
2923 +
2924 +int npe_running(struct npe *npe);
2925 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
2926 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
2927 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
2928 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
2929 +struct npe *npe_request(int id);
2930 +void npe_release(struct npe *npe);
2931 +
2932 +#endif /* __IXP4XX_NPE_H */
2933 Index: linux-2.6.24.7/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
2934 ===================================================================
2935 --- /dev/null
2936 +++ linux-2.6.24.7/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
2937 @@ -0,0 +1,274 @@
2938 +/*
2939 + * Intel IXP4xx Queue Manager driver for Linux
2940 + *
2941 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2942 + *
2943 + * This program is free software; you can redistribute it and/or modify it
2944 + * under the terms of version 2 of the GNU General Public License
2945 + * as published by the Free Software Foundation.
2946 + */
2947 +
2948 +#include <linux/ioport.h>
2949 +#include <linux/interrupt.h>
2950 +#include <linux/kernel.h>
2951 +#include <linux/module.h>
2952 +#include <asm/arch/qmgr.h>
2953 +
2954 +#define DEBUG 0
2955 +
2956 +struct qmgr_regs __iomem *qmgr_regs;
2957 +static struct resource *mem_res;
2958 +static spinlock_t qmgr_lock;
2959 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
2960 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
2961 +static void *irq_pdevs[HALF_QUEUES];
2962 +
2963 +void qmgr_set_irq(unsigned int queue, int src,
2964 + void (*handler)(void *pdev), void *pdev)
2965 +{
2966 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
2967 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
2968 + unsigned long flags;
2969 +
2970 + src &= 7;
2971 + spin_lock_irqsave(&qmgr_lock, flags);
2972 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
2973 + irq_handlers[queue] = handler;
2974 + irq_pdevs[queue] = pdev;
2975 + spin_unlock_irqrestore(&qmgr_lock, flags);
2976 +}
2977 +
2978 +
2979 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
2980 +{
2981 + int i;
2982 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
2983 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
2984 +
2985 + for (i = 0; i < HALF_QUEUES; i++)
2986 + if (val & (1 << i))
2987 + irq_handlers[i](irq_pdevs[i]);
2988 +
2989 + return val ? IRQ_HANDLED : 0;
2990 +}
2991 +
2992 +
2993 +void qmgr_enable_irq(unsigned int queue)
2994 +{
2995 + unsigned long flags;
2996 +
2997 + spin_lock_irqsave(&qmgr_lock, flags);
2998 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
2999 + &qmgr_regs->irqen[0]);
3000 + spin_unlock_irqrestore(&qmgr_lock, flags);
3001 +}
3002 +
3003 +void qmgr_disable_irq(unsigned int queue)
3004 +{
3005 + unsigned long flags;
3006 +
3007 + spin_lock_irqsave(&qmgr_lock, flags);
3008 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
3009 + &qmgr_regs->irqen[0]);
3010 + spin_unlock_irqrestore(&qmgr_lock, flags);
3011 +}
3012 +
3013 +static inline void shift_mask(u32 *mask)
3014 +{
3015 + mask[3] = mask[3] << 1 | mask[2] >> 31;
3016 + mask[2] = mask[2] << 1 | mask[1] >> 31;
3017 + mask[1] = mask[1] << 1 | mask[0] >> 31;
3018 + mask[0] <<= 1;
3019 +}
3020 +
3021 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3022 + unsigned int nearly_empty_watermark,
3023 + unsigned int nearly_full_watermark)
3024 +{
3025 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
3026 + int err;
3027 +
3028 + if (queue >= HALF_QUEUES)
3029 + return -ERANGE;
3030 +
3031 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
3032 + return -EINVAL;
3033 +
3034 + switch (len) {
3035 + case 16:
3036 + cfg = 0 << 24;
3037 + mask[0] = 0x1;
3038 + break;
3039 + case 32:
3040 + cfg = 1 << 24;
3041 + mask[0] = 0x3;
3042 + break;
3043 + case 64:
3044 + cfg = 2 << 24;
3045 + mask[0] = 0xF;
3046 + break;
3047 + case 128:
3048 + cfg = 3 << 24;
3049 + mask[0] = 0xFF;
3050 + break;
3051 + default:
3052 + return -EINVAL;
3053 + }
3054 +
3055 + cfg |= nearly_empty_watermark << 26;
3056 + cfg |= nearly_full_watermark << 29;
3057 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
3058 + mask[1] = mask[2] = mask[3] = 0;
3059 +
3060 + if (!try_module_get(THIS_MODULE))
3061 + return -ENODEV;
3062 +
3063 + spin_lock_irq(&qmgr_lock);
3064 + if (__raw_readl(&qmgr_regs->sram[queue])) {
3065 + err = -EBUSY;
3066 + goto err;
3067 + }
3068 +
3069 + while (1) {
3070 + if (!(used_sram_bitmap[0] & mask[0]) &&
3071 + !(used_sram_bitmap[1] & mask[1]) &&
3072 + !(used_sram_bitmap[2] & mask[2]) &&
3073 + !(used_sram_bitmap[3] & mask[3]))
3074 + break; /* found free space */
3075 +
3076 + addr++;
3077 + shift_mask(mask);
3078 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
3079 + printk(KERN_ERR "qmgr: no free SRAM space for"
3080 + " queue %i\n", queue);
3081 + err = -ENOMEM;
3082 + goto err;
3083 + }
3084 + }
3085 +
3086 + used_sram_bitmap[0] |= mask[0];
3087 + used_sram_bitmap[1] |= mask[1];
3088 + used_sram_bitmap[2] |= mask[2];
3089 + used_sram_bitmap[3] |= mask[3];
3090 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
3091 + spin_unlock_irq(&qmgr_lock);
3092 +
3093 +#if DEBUG
3094 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
3095 + queue, addr);
3096 +#endif
3097 + return 0;
3098 +
3099 +err:
3100 + spin_unlock_irq(&qmgr_lock);
3101 + module_put(THIS_MODULE);
3102 + return err;
3103 +}
3104 +
3105 +void qmgr_release_queue(unsigned int queue)
3106 +{
3107 + u32 cfg, addr, mask[4];
3108 +
3109 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
3110 +
3111 + spin_lock_irq(&qmgr_lock);
3112 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
3113 + addr = (cfg >> 14) & 0xFF;
3114 +
3115 + BUG_ON(!addr); /* not requested */
3116 +
3117 + switch ((cfg >> 24) & 3) {
3118 + case 0: mask[0] = 0x1; break;
3119 + case 1: mask[0] = 0x3; break;
3120 + case 2: mask[0] = 0xF; break;
3121 + case 3: mask[0] = 0xFF; break;
3122 + }
3123 +
3124 + while (addr--)
3125 + shift_mask(mask);
3126 +
3127 + __raw_writel(0, &qmgr_regs->sram[queue]);
3128 +
3129 + used_sram_bitmap[0] &= ~mask[0];
3130 + used_sram_bitmap[1] &= ~mask[1];
3131 + used_sram_bitmap[2] &= ~mask[2];
3132 + used_sram_bitmap[3] &= ~mask[3];
3133 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
3134 + spin_unlock_irq(&qmgr_lock);
3135 +
3136 + module_put(THIS_MODULE);
3137 +#if DEBUG
3138 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
3139 +#endif
3140 +}
3141 +
3142 +static int qmgr_init(void)
3143 +{
3144 + int i, err;
3145 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
3146 + IXP4XX_QMGR_REGION_SIZE,
3147 + "IXP4xx Queue Manager");
3148 + if (mem_res == NULL)
3149 + return -EBUSY;
3150 +
3151 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3152 + if (qmgr_regs == NULL) {
3153 + err = -ENOMEM;
3154 + goto error_map;
3155 + }
3156 +
3157 + /* reset qmgr registers */
3158 + for (i = 0; i < 4; i++) {
3159 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
3160 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
3161 + }
3162 + for (i = 0; i < 2; i++) {
3163 + __raw_writel(0, &qmgr_regs->stat2[i]);
3164 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
3165 + __raw_writel(0, &qmgr_regs->irqen[i]);
3166 + }
3167 +
3168 + for (i = 0; i < QUEUES; i++)
3169 + __raw_writel(0, &qmgr_regs->sram[i]);
3170 +
3171 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
3172 + "IXP4xx Queue Manager", NULL);
3173 + if (err) {
3174 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
3175 + IRQ_IXP4XX_QM1);
3176 + goto error_irq;
3177 + }
3178 +
3179 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
3180 + spin_lock_init(&qmgr_lock);
3181 +
3182 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
3183 + return 0;
3184 +
3185 +error_irq:
3186 + iounmap(qmgr_regs);
3187 +error_map:
3188 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3189 + return err;
3190 +}
3191 +
3192 +static void qmgr_remove(void)
3193 +{
3194 + free_irq(IRQ_IXP4XX_QM1, NULL);
3195 + synchronize_irq(IRQ_IXP4XX_QM1);
3196 + iounmap(qmgr_regs);
3197 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3198 +}
3199 +
3200 +module_init(qmgr_init);
3201 +module_exit(qmgr_remove);
3202 +
3203 +MODULE_LICENSE("GPL v2");
3204 +MODULE_AUTHOR("Krzysztof Halasa");
3205 +
3206 +EXPORT_SYMBOL(qmgr_regs);
3207 +EXPORT_SYMBOL(qmgr_set_irq);
3208 +EXPORT_SYMBOL(qmgr_enable_irq);
3209 +EXPORT_SYMBOL(qmgr_disable_irq);
3210 +EXPORT_SYMBOL(qmgr_request_queue);
3211 +EXPORT_SYMBOL(qmgr_release_queue);
3212 Index: linux-2.6.24.7/arch/arm/mach-ixp4xx/ixp4xx_npe.c
3213 ===================================================================
3214 --- /dev/null
3215 +++ linux-2.6.24.7/arch/arm/mach-ixp4xx/ixp4xx_npe.c
3216 @@ -0,0 +1,741 @@
3217 +/*
3218 + * Intel IXP4xx Network Processor Engine driver for Linux
3219 + *
3220 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3221 + *
3222 + * This program is free software; you can redistribute it and/or modify it
3223 + * under the terms of version 2 of the GNU General Public License
3224 + * as published by the Free Software Foundation.
3225 + *
3226 + * The code is based on publicly available information:
3227 + * - Intel IXP4xx Developer's Manual and other e-papers
3228 + * - Intel IXP400 Access Library Software (BSD license)
3229 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
3230 + * Thanks, Christian.
3231 + */
3232 +
3233 +#include <linux/delay.h>
3234 +#include <linux/dma-mapping.h>
3235 +#include <linux/firmware.h>
3236 +#include <linux/io.h>
3237 +#include <linux/kernel.h>
3238 +#include <linux/module.h>
3239 +#include <linux/slab.h>
3240 +#include <asm/arch/npe.h>
3241 +
3242 +#define DEBUG_MSG 0
3243 +#define DEBUG_FW 0
3244 +
3245 +#define NPE_COUNT 3
3246 +#define MAX_RETRIES 1000 /* microseconds */
3247 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
3248 +#define NPE_46X_DATA_SIZE 0x1000
3249 +#define NPE_A_42X_INSTR_SIZE 0x1000
3250 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
3251 +#define NPE_46X_INSTR_SIZE 0x1000
3252 +#define REGS_SIZE 0x1000
3253 +
3254 +#define NPE_PHYS_REG 32
3255 +
3256 +#define FW_MAGIC 0xFEEDF00D
3257 +#define FW_BLOCK_TYPE_INSTR 0x0
3258 +#define FW_BLOCK_TYPE_DATA 0x1
3259 +#define FW_BLOCK_TYPE_EOF 0xF
3260 +
3261 +/* NPE exec status (read) and command (write) */
3262 +#define CMD_NPE_STEP 0x01
3263 +#define CMD_NPE_START 0x02
3264 +#define CMD_NPE_STOP 0x03
3265 +#define CMD_NPE_CLR_PIPE 0x04
3266 +#define CMD_CLR_PROFILE_CNT 0x0C
3267 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
3268 +#define CMD_WR_INS_MEM 0x11
3269 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
3270 +#define CMD_WR_DATA_MEM 0x13
3271 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
3272 +#define CMD_WR_ECS_REG 0x15
3273 +
3274 +#define STAT_RUN 0x80000000
3275 +#define STAT_STOP 0x40000000
3276 +#define STAT_CLEAR 0x20000000
3277 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
3278 +
3279 +#define NPE_STEVT 0x1B
3280 +#define NPE_STARTPC 0x1C
3281 +#define NPE_REGMAP 0x1E
3282 +#define NPE_CINDEX 0x1F
3283 +
3284 +#define INSTR_WR_REG_SHORT 0x0000C000
3285 +#define INSTR_WR_REG_BYTE 0x00004000
3286 +#define INSTR_RD_FIFO 0x0F888220
3287 +#define INSTR_RESET_MBOX 0x0FAC8210
3288 +
3289 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
3290 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
3291 +#define ECS_BG_CTXT_REG_2 0x02
3292 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
3293 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
3294 +#define ECS_PRI_1_CTXT_REG_2 0x06
3295 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
3296 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
3297 +#define ECS_PRI_2_CTXT_REG_2 0x0A
3298 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
3299 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
3300 +#define ECS_DBG_CTXT_REG_2 0x0E
3301 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
3302 +
3303 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
3304 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
3305 +#define ECS_REG_0_LDUR_BITS 8
3306 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
3307 +#define ECS_REG_1_CCTXT_BITS 16
3308 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
3309 +#define ECS_REG_1_SELCTXT_BITS 0
3310 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
3311 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
3312 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
3313 +
3314 +/* NPE watchpoint_fifo register bit */
3315 +#define WFIFO_VALID 0x80000000
3316 +
3317 +/* NPE messaging_status register bit definitions */
3318 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
3319 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
3320 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
3321 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
3322 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
3323 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
3324 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
3325 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
3326 +
3327 +/* NPE messaging_control register bit definitions */
3328 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
3329 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
3330 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
3331 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
3332 +
3333 +/* NPE mailbox_status value for reset */
3334 +#define RESET_MBOX_STAT 0x0000F0F0
3335 +
3336 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
3337 +
3338 +#define print_npe(pri, npe, fmt, ...) \
3339 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
3340 +
3341 +#if DEBUG_MSG
3342 +#define debug_msg(npe, fmt, ...) \
3343 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
3344 +#else
3345 +#define debug_msg(npe, fmt, ...)
3346 +#endif
3347 +
3348 +static struct {
3349 + u32 reg, val;
3350 +} ecs_reset[] = {
3351 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
3352 + { ECS_BG_CTXT_REG_1, 0x01000000 },
3353 + { ECS_BG_CTXT_REG_2, 0x00008000 },
3354 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
3355 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
3356 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
3357 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
3358 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
3359 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
3360 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
3361 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
3362 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
3363 + { ECS_INSTRUCT_REG, 0x1003C00F },
3364 +};
3365 +
3366 +static struct npe npe_tab[NPE_COUNT] = {
3367 + {
3368 + .id = 0,
3369 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
3370 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
3371 + }, {
3372 + .id = 1,
3373 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
3374 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
3375 + }, {
3376 + .id = 2,
3377 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
3378 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
3379 + }
3380 +};
3381 +
3382 +int npe_running(struct npe *npe)
3383 +{
3384 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
3385 +}
3386 +
3387 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
3388 +{
3389 + __raw_writel(data, &npe->regs->exec_data);
3390 + __raw_writel(addr, &npe->regs->exec_addr);
3391 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
3392 +}
3393 +
3394 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
3395 +{
3396 + __raw_writel(addr, &npe->regs->exec_addr);
3397 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
3398 + /* Iintroduce extra read cycles after issuing read command to NPE
3399 + so that we read the register after the NPE has updated it.
3400 + This is to overcome race condition between XScale and NPE */
3401 + __raw_readl(&npe->regs->exec_data);
3402 + __raw_readl(&npe->regs->exec_data);
3403 + return __raw_readl(&npe->regs->exec_data);
3404 +}
3405 +
3406 +static void npe_clear_active(struct npe *npe, u32 reg)
3407 +{
3408 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
3409 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
3410 +}
3411 +
3412 +static void npe_start(struct npe *npe)
3413 +{
3414 + /* ensure only Background Context Stack Level is active */
3415 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
3416 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
3417 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
3418 +
3419 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3420 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
3421 +}
3422 +
3423 +static void npe_stop(struct npe *npe)
3424 +{
3425 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
3426 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
3427 +}
3428 +
3429 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
3430 + u32 ldur)
3431 +{
3432 + u32 wc;
3433 + int i;
3434 +
3435 + /* set the Active bit, and the LDUR, in the debug level */
3436 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
3437 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
3438 +
3439 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
3440 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
3441 + which context store to access.
3442 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
3443 + */
3444 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
3445 + (ctx << ECS_REG_1_CCTXT_BITS) |
3446 + (ctx << ECS_REG_1_SELCTXT_BITS));
3447 +
3448 + /* clear the pipeline */
3449 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3450 +
3451 + /* load NPE instruction into the instruction register */
3452 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
3453 +
3454 + /* we need this value later to wait for completion of NPE execution
3455 + step */
3456 + wc = __raw_readl(&npe->regs->watch_count);
3457 +
3458 + /* issue a Step One command via the Execution Control register */
3459 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
3460 +
3461 + /* Watch Count register increments when NPE completes an instruction */
3462 + for (i = 0; i < MAX_RETRIES; i++) {
3463 + if (wc != __raw_readl(&npe->regs->watch_count))
3464 + return 0;
3465 + udelay(1);
3466 + }
3467 +
3468 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
3469 + return -ETIMEDOUT;
3470 +}
3471 +
3472 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
3473 + u8 val, u32 ctx)
3474 +{
3475 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
3476 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
3477 + addr << 9 | /* base Operand */
3478 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
3479 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
3480 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
3481 +}
3482 +
3483 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
3484 + u16 val, u32 ctx)
3485 +{
3486 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
3487 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
3488 + addr << 9 | /* base Operand */
3489 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
3490 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
3491 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
3492 +}
3493 +
3494 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
3495 + u32 val, u32 ctx)
3496 +{
3497 + /* write in 16 bit steps first the high and then the low value */
3498 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
3499 + return -ETIMEDOUT;
3500 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
3501 +}
3502 +
3503 +static int npe_reset(struct npe *npe)
3504 +{
3505 + u32 val, ctl, exec_count, ctx_reg2;
3506 + int i;
3507 +
3508 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
3509 + 0x3F3FFFFF;
3510 +
3511 + /* disable parity interrupt */
3512 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
3513 +
3514 + /* pre exec - debug instruction */
3515 + /* turn off the halt bit by clearing Execution Count register. */
3516 + exec_count = __raw_readl(&npe->regs->exec_count);
3517 + __raw_writel(0, &npe->regs->exec_count);
3518 + /* ensure that IF and IE are on (temporarily), so that we don't end up
3519 + stepping forever */
3520 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
3521 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
3522 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
3523 +
3524 + /* clear the FIFOs */
3525 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
3526 + ;
3527 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
3528 + /* read from the outFIFO until empty */
3529 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
3530 + __raw_readl(&npe->regs->in_out_fifo));
3531 +
3532 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
3533 + /* step execution of the NPE intruction to read inFIFO using
3534 + the Debug Executing Context stack */
3535 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
3536 + return -ETIMEDOUT;
3537 +
3538 + /* reset the mailbox reg from the XScale side */
3539 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
3540 + /* from NPE side */
3541 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
3542 + return -ETIMEDOUT;
3543 +
3544 + /* Reset the physical registers in the NPE register file */
3545 + for (val = 0; val < NPE_PHYS_REG; val++) {
3546 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
3547 + return -ETIMEDOUT;
3548 + /* address is either 0 or 4 */
3549 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
3550 + return -ETIMEDOUT;
3551 + }
3552 +
3553 + /* Reset the context store = each context's Context Store registers */
3554 +
3555 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
3556 + for Background ECS, to set where NPE starts executing code */
3557 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
3558 + val &= ~ECS_REG_0_NEXTPC_MASK;
3559 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
3560 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
3561 +
3562 + for (i = 0; i < 16; i++) {
3563 + if (i) { /* Context 0 has no STEVT nor STARTPC */
3564 + /* STEVT = off, 0x80 */
3565 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
3566 + return -ETIMEDOUT;
3567 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
3568 + return -ETIMEDOUT;
3569 + }
3570 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
3571 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
3572 + return -ETIMEDOUT;
3573 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
3574 + return -ETIMEDOUT;
3575 + }
3576 +
3577 + /* post exec */
3578 + /* clear active bit in debug level */
3579 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
3580 + /* clear the pipeline */
3581 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3582 + /* restore previous values */
3583 + __raw_writel(exec_count, &npe->regs->exec_count);
3584 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
3585 +
3586 + /* write reset values to Execution Context Stack registers */
3587 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
3588 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
3589 + ecs_reset[val].val);
3590 +
3591 + /* clear the profile counter */
3592 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
3593 +
3594 + __raw_writel(0, &npe->regs->exec_count);
3595 + __raw_writel(0, &npe->regs->action_points[0]);
3596 + __raw_writel(0, &npe->regs->action_points[1]);
3597 + __raw_writel(0, &npe->regs->action_points[2]);
3598 + __raw_writel(0, &npe->regs->action_points[3]);
3599 + __raw_writel(0, &npe->regs->watch_count);
3600 +
3601 + val = ixp4xx_read_feature_bits();
3602 + /* reset the NPE */
3603 + ixp4xx_write_feature_bits(val &
3604 + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
3605 + for (i = 0; i < MAX_RETRIES; i++) {
3606 + if (!(ixp4xx_read_feature_bits() &
3607 + (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
3608 + break; /* reset completed */
3609 + udelay(1);
3610 + }
3611 + if (i == MAX_RETRIES)
3612 + return -ETIMEDOUT;
3613 +
3614 + /* deassert reset */
3615 + ixp4xx_write_feature_bits(val |
3616 + (IXP4XX_FEATURE_RESET_NPEA << npe->id));
3617 + for (i = 0; i < MAX_RETRIES; i++) {
3618 + if (ixp4xx_read_feature_bits() &
3619 + (IXP4XX_FEATURE_RESET_NPEA << npe->id))
3620 + break; /* NPE is back alive */
3621 + udelay(1);
3622 + }
3623 + if (i == MAX_RETRIES)
3624 + return -ETIMEDOUT;
3625 +
3626 + npe_stop(npe);
3627 +
3628 + /* restore NPE configuration bus Control Register - parity settings */
3629 + __raw_writel(ctl, &npe->regs->messaging_control);
3630 + return 0;
3631 +}
3632 +
3633 +
3634 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
3635 +{
3636 + const u32 *send = msg;
3637 + int cycles = 0;
3638 +
3639 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
3640 + what, send[0], send[1]);
3641 +
3642 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
3643 + debug_msg(npe, "NPE input FIFO not empty\n");
3644 + return -EIO;
3645 + }
3646 +
3647 + __raw_writel(send[0], &npe->regs->in_out_fifo);
3648 +
3649 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
3650 + debug_msg(npe, "NPE input FIFO full\n");
3651 + return -EIO;
3652 + }
3653 +
3654 + __raw_writel(send[1], &npe->regs->in_out_fifo);
3655 +
3656 + while ((cycles < MAX_RETRIES) &&
3657 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
3658 + udelay(1);
3659 + cycles++;
3660 + }
3661 +
3662 + if (cycles == MAX_RETRIES) {
3663 + debug_msg(npe, "Timeout sending message\n");
3664 + return -ETIMEDOUT;
3665 + }
3666 +
3667 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
3668 + return 0;
3669 +}
3670 +
3671 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
3672 +{
3673 + u32 *recv = msg;
3674 + int cycles = 0, cnt = 0;
3675 +
3676 + debug_msg(npe, "Trying to receive message %s\n", what);
3677 +
3678 + while (cycles < MAX_RETRIES) {
3679 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
3680 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
3681 + if (cnt == 2)
3682 + break;
3683 + } else {
3684 + udelay(1);
3685 + cycles++;
3686 + }
3687 + }
3688 +
3689 + switch(cnt) {
3690 + case 1:
3691 + debug_msg(npe, "Received [%08X]\n", recv[0]);
3692 + break;
3693 + case 2:
3694 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
3695 + break;
3696 + }
3697 +
3698 + if (cycles == MAX_RETRIES) {
3699 + debug_msg(npe, "Timeout waiting for message\n");
3700 + return -ETIMEDOUT;
3701 + }
3702 +
3703 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
3704 + return 0;
3705 +}
3706 +
3707 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
3708 +{
3709 + int result;
3710 + u32 *send = msg, recv[2];
3711 +
3712 + if ((result = npe_send_message(npe, msg, what)) != 0)
3713 + return result;
3714 + if ((result = npe_recv_message(npe, recv, what)) != 0)
3715 + return result;
3716 +
3717 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
3718 + debug_msg(npe, "Message %s: unexpected message received\n",
3719 + what);
3720 + return -EIO;
3721 + }
3722 + return 0;
3723 +}
3724 +
3725 +
3726 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
3727 +{
3728 + const struct firmware *fw_entry;
3729 +
3730 + struct dl_block {
3731 + u32 type;
3732 + u32 offset;
3733 + } *blk;
3734 +
3735 + struct dl_image {
3736 + u32 magic;
3737 + u32 id;
3738 + u32 size;
3739 + union {
3740 + u32 data[0];
3741 + struct dl_block blocks[0];
3742 + };
3743 + } *image;
3744 +
3745 + struct dl_codeblock {
3746 + u32 npe_addr;
3747 + u32 size;
3748 + u32 data[0];
3749 + } *cb;
3750 +
3751 + int i, j, err, data_size, instr_size, blocks, table_end;
3752 + u32 cmd;
3753 +
3754 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
3755 + return err;
3756 +
3757 + err = -EINVAL;
3758 + if (fw_entry->size < sizeof(struct dl_image)) {
3759 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
3760 + goto err;
3761 + }
3762 + image = (struct dl_image*)fw_entry->data;
3763 +
3764 +#if DEBUG_FW
3765 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
3766 + image->magic, image->id, image->size, image->size * 4);
3767 +#endif
3768 +
3769 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
3770 + image->id = swab32(image->id);
3771 + image->size = swab32(image->size);
3772 + } else if (image->magic != FW_MAGIC) {
3773 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
3774 + image->magic);
3775 + goto err;
3776 + }
3777 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
3778 + print_npe(KERN_ERR, npe,
3779 + "inconsistent size of firmware file\n");
3780 + goto err;
3781 + }
3782 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
3783 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
3784 + goto err;
3785 + }
3786 + if (image->magic == swab32(FW_MAGIC))
3787 + for (i = 0; i < image->size; i++)
3788 + image->data[i] = swab32(image->data[i]);
3789 +
3790 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
3791 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
3792 + "IXP42x\n");
3793 + goto err;
3794 + }
3795 +
3796 + if (npe_running(npe)) {
3797 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
3798 + "already running\n");
3799 + err = -EBUSY;
3800 + goto err;
3801 + }
3802 +#if 0
3803 + npe_stop(npe);
3804 + npe_reset(npe);
3805 +#endif
3806 +
3807 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
3808 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
3809 + (image->id >> 8) & 0xFF, image->id & 0xFF);
3810 +
3811 + if (!cpu_is_ixp46x()) {
3812 + if (!npe->id)
3813 + instr_size = NPE_A_42X_INSTR_SIZE;
3814 + else
3815 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
3816 + data_size = NPE_42X_DATA_SIZE;
3817 + } else {
3818 + instr_size = NPE_46X_INSTR_SIZE;
3819 + data_size = NPE_46X_DATA_SIZE;
3820 + }
3821 +
3822 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
3823 + blocks++)
3824 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
3825 + break;
3826 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
3827 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
3828 + "found\n");
3829 + goto err;
3830 + }
3831 +
3832 +#if DEBUG_FW
3833 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
3834 +#endif
3835 +
3836 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
3837 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
3838 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
3839 + || blk->offset < table_end) {
3840 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
3841 + "firmware block #%i\n", blk->offset, i);
3842 + goto err;
3843 + }
3844 +
3845 + cb = (struct dl_codeblock*)&image->data[blk->offset];
3846 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
3847 + if (cb->npe_addr + cb->size > instr_size)
3848 + goto too_big;
3849 + cmd = CMD_WR_INS_MEM;
3850 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
3851 + if (cb->npe_addr + cb->size > data_size)
3852 + goto too_big;
3853 + cmd = CMD_WR_DATA_MEM;
3854 + } else {
3855 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
3856 + "type 0x%X\n", i, blk->type);
3857 + goto err;
3858 + }
3859 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
3860 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
3861 + "fit in firmware image: type %c, start 0x%X,"
3862 + " length 0x%X\n", i,
3863 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
3864 + cb->npe_addr, cb->size);
3865 + goto err;
3866 + }
3867 +
3868 + for (j = 0; j < cb->size; j++)
3869 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
3870 + }
3871 +
3872 + npe_start(npe);
3873 + if (!npe_running(npe))
3874 + print_npe(KERN_ERR, npe, "unable to start\n");
3875 + release_firmware(fw_entry);
3876 + return 0;
3877 +
3878 +too_big:
3879 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
3880 + "memory: type %c, start 0x%X, length 0x%X\n", i,
3881 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
3882 + cb->npe_addr, cb->size);
3883 +err:
3884 + release_firmware(fw_entry);
3885 + return err;
3886 +}
3887 +
3888 +
3889 +struct npe *npe_request(int id)
3890 +{
3891 + if (id < NPE_COUNT)
3892 + if (npe_tab[id].valid)
3893 + if (try_module_get(THIS_MODULE))
3894 + return &npe_tab[id];
3895 + return NULL;
3896 +}
3897 +
3898 +void npe_release(struct npe *npe)
3899 +{
3900 + module_put(THIS_MODULE);
3901 +}
3902 +
3903 +
3904 +static int __init npe_init_module(void)
3905 +{
3906 +
3907 + int i, found = 0;
3908 +
3909 + for (i = 0; i < NPE_COUNT; i++) {
3910 + struct npe *npe = &npe_tab[i];
3911 + if (!(ixp4xx_read_feature_bits() &
3912 + (IXP4XX_FEATURE_RESET_NPEA << i)))
3913 + continue; /* NPE already disabled or not present */
3914 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
3915 + REGS_SIZE,
3916 + npe_name(npe)))) {
3917 + print_npe(KERN_ERR, npe,
3918 + "failed to request memory region\n");
3919 + continue;
3920 + }
3921 +
3922 + if (npe_reset(npe))
3923 + continue;
3924 + npe->valid = 1;
3925 + found++;
3926 + }
3927 +
3928 + if (!found)
3929 + return -ENOSYS;
3930 + return 0;
3931 +}
3932 +
3933 +static void __exit npe_cleanup_module(void)
3934 +{
3935 + int i;
3936 +
3937 + for (i = 0; i < NPE_COUNT; i++)
3938 + if (npe_tab[i].mem_res) {
3939 + npe_reset(&npe_tab[i]);
3940 + release_resource(npe_tab[i].mem_res);
3941 + }
3942 +}
3943 +
3944 +module_init(npe_init_module);
3945 +module_exit(npe_cleanup_module);
3946 +
3947 +MODULE_AUTHOR("Krzysztof Halasa");
3948 +MODULE_LICENSE("GPL v2");
3949 +
3950 +EXPORT_SYMBOL(npe_names);
3951 +EXPORT_SYMBOL(npe_running);
3952 +EXPORT_SYMBOL(npe_request);
3953 +EXPORT_SYMBOL(npe_release);
3954 +EXPORT_SYMBOL(npe_load_firmware);
3955 +EXPORT_SYMBOL(npe_send_message);
3956 +EXPORT_SYMBOL(npe_recv_message);
3957 +EXPORT_SYMBOL(npe_send_recv_message);
3958 Index: linux-2.6.24.7/include/asm-arm/arch-ixp4xx/platform.h
3959 ===================================================================
3960 --- linux-2.6.24.7.orig/include/asm-arm/arch-ixp4xx/platform.h
3961 +++ linux-2.6.24.7/include/asm-arm/arch-ixp4xx/platform.h
3962 @@ -102,6 +102,27 @@ struct ixp4xx_pata_data {
3963
3964 struct sys_timer;
3965
3966 +#define IXP4XX_ETH_NPEA 0x00
3967 +#define IXP4XX_ETH_NPEB 0x10
3968 +#define IXP4XX_ETH_NPEC 0x20
3969 +
3970 +/* Information about built-in Ethernet MAC interfaces */
3971 +struct eth_plat_info {
3972 + u8 phy; /* MII PHY ID, 0 - 31 */
3973 + u8 rxq; /* configurable, currently 0 - 31 only */
3974 + u8 txreadyq;
3975 + u8 hwaddr[6];
3976 +};
3977 +
3978 +/* Information about built-in HSS (synchronous serial) interfaces */
3979 +struct hss_plat_info {
3980 + int (*set_clock)(int port, unsigned int clock_type);
3981 + int (*open)(int port, void *pdev,
3982 + void (*set_carrier_cb)(void *pdev, int carrier));
3983 + void (*close)(int port, void *pdev);
3984 + u8 txreadyq;
3985 +};
3986 +
3987 /*
3988 * Frequency of clock used for primary clocksource
3989 */
3990 Index: linux-2.6.24.7/arch/arm/mach-ixp4xx/ixdp425-setup.c
3991 ===================================================================
3992 --- linux-2.6.24.7.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c
3993 +++ linux-2.6.24.7/arch/arm/mach-ixp4xx/ixdp425-setup.c
3994 @@ -177,6 +177,31 @@ static struct platform_device ixdp425_ua
3995 .resource = ixdp425_uart_resources
3996 };
3997
3998 +/* Built-in 10/100 Ethernet MAC interfaces */
3999 +static struct eth_plat_info ixdp425_plat_eth[] = {
4000 + {
4001 + .phy = 0,
4002 + .rxq = 3,
4003 + .txreadyq = 20,
4004 + }, {
4005 + .phy = 1,
4006 + .rxq = 4,
4007 + .txreadyq = 21,
4008 + }
4009 +};
4010 +
4011 +static struct platform_device ixdp425_eth[] = {
4012 + {
4013 + .name = "ixp4xx_eth",
4014 + .id = IXP4XX_ETH_NPEB,
4015 + .dev.platform_data = ixdp425_plat_eth,
4016 + }, {
4017 + .name = "ixp4xx_eth",
4018 + .id = IXP4XX_ETH_NPEC,
4019 + .dev.platform_data = ixdp425_plat_eth + 1,
4020 + }
4021 +};
4022 +
4023 static struct platform_device *ixdp425_devices[] __initdata = {
4024 &ixdp425_i2c_gpio,
4025 &ixdp425_flash,
4026 @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_d
4027 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
4028 &ixdp425_flash_nand,
4029 #endif
4030 - &ixdp425_uart
4031 + &ixdp425_uart,
4032 + &ixdp425_eth[0],
4033 + &ixdp425_eth[1],
4034 };
4035
4036 static void __init ixdp425_init(void)
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