[ar7] use correct port type, which sets the correct receive fifo trigger options...
[openwrt.git] / target / linux / coldfire / patches / 022-m5445x_ccm_bitdefs.patch
1 From b100a50c3bf7884a97d5008fc79d9b45f3b6e999 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Fri, 30 Nov 2007 12:55:12 -0700
4 Subject: [PATCH] Fix bitfield definitions.
5
6 LTIBName: m5445x-ccm-bitdefs
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 ---
9 include/asm-m68k/mcf5445x_ccm.h | 34 ++++++++++++++++++----------------
10 1 files changed, 18 insertions(+), 16 deletions(-)
11
12 --- a/include/asm-m68k/mcf5445x_ccm.h
13 +++ b/include/asm-m68k/mcf5445x_ccm.h
14 @@ -118,22 +118,24 @@
15 #define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) /* Bus monitor timing field */
16 #define MCF_CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
17 #define MCF_CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
18 -#define MCF_CCM_MISCCR_BMT_65536 (0)
19 -#define MCF_CCM_MISCCR_BMT_32768 (1)
20 -#define MCF_CCM_MISCCR_BMT_16384 (2)
21 -#define MCF_CCM_MISCCR_BMT_8192 (3)
22 -#define MCF_CCM_MISCCR_BMT_4096 (4)
23 -#define MCF_CCM_MISCCR_BMT_2048 (5)
24 -#define MCF_CCM_MISCCR_BMT_1024 (6)
25 -#define MCF_CCM_MISCCR_BMT_512 (7)
26 -#define MCF_CCM_MISCCR_SSIPUS_UP (1)
27 -#define MCF_CCM_MISCCR_SSIPUS_DOWN (0)
28 -#define MCF_CCM_MISCCR_TIMDMA_TIM (1)
29 -#define MCF_CCM_MISCCR_TIMDMA_SSI (0)
30 -#define MCF_CCM_MISCCR_SSISRC_CLKIN (0)
31 -#define MCF_CCM_MISCCR_SSISRC_PLL (1)
32 -#define MCF_CCM_MISCCR_USBOC_ACTHI (0)
33 -#define MCF_CCM_MISCCR_USBOV_ACTLO (1)
34 +#define MCF_CCM_MISCCR_BMT_65536 (0 << 8)
35 +#define MCF_CCM_MISCCR_BMT_32768 (1 << 8)
36 +#define MCF_CCM_MISCCR_BMT_16384 (2 << 8)
37 +#define MCF_CCM_MISCCR_BMT_8192 (3 << 8)
38 +#define MCF_CCM_MISCCR_BMT_4096 (4 << 8)
39 +#define MCF_CCM_MISCCR_BMT_2048 (5 << 8)
40 +#define MCF_CCM_MISCCR_BMT_1024 (6 << 8)
41 +#define MCF_CCM_MISCCR_BMT_512 (7 << 8)
42 +#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7)
43 +#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7)
44 +#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6)
45 +#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6)
46 +#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5)
47 +#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5)
48 +#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4)
49 +#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4)
50 +#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1)
51 +#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1)
52 #define MCF_CCM_MISCCR_USBSRC_CLKIN (0)
53 #define MCF_CCM_MISCCR_USBSRC_PLL (1)
54
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