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[s3c24xx] Add 2.6.31 patches
[openwrt.git] / target / linux / s3c24xx / files-2.6.31 / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 336x/337x driver
2 *
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/irq.h>
31 #include <linux/interrupt.h>
32 #include <linux/workqueue.h>
33 #include <linux/platform_device.h>
34 #include <linux/kernel_stat.h>
35 #include <linux/spinlock.h>
36 #include <linux/mfd/core.h>
37 #include <linux/mfd/glamo.h>
38 #include <linux/io.h>
39
40 #include <linux/pm.h>
41
42 #include "glamo-regs.h"
43 #include "glamo-core.h"
44
45 #define GLAMO_MEM_REFRESH_COUNT 0x100
46
47 #define GLAMO_NR_IRQS 9
48
49 #define GLAMO_IRQ_HOSTBUS 0
50 #define GLAMO_IRQ_JPEG 1
51 #define GLAMO_IRQ_MPEG 2
52 #define GLAMO_IRQ_MPROC1 3
53 #define GLAMO_IRQ_MPROC0 4
54 #define GLAMO_IRQ_CMDQUEUE 5
55 #define GLAMO_IRQ_2D 6
56 #define GLAMO_IRQ_MMC 7
57 #define GLAMO_IRQ_RISC 8
58
59 /*
60 * Glamo internal settings
61 *
62 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
63 * above. Couple of GTA02 users report trouble with memory bus when they
64 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
65 * scheme if their Glamo chip needs it.
66 *
67 * you can override the faster default on kernel commandline using
68 *
69 * glamo3362.slow_memory=1
70 *
71 * for example
72 */
73
74 static int slow_memory = 0;
75 module_param(slow_memory, int, 0644);
76
77 struct reg_range {
78 int start;
79 int count;
80 char *name;
81 unsigned dump : 1;
82 };
83
84 static const struct reg_range reg_range[] = {
85 { 0x0000, 0x76, "General", 1 },
86 { 0x0200, 0x18, "Host Bus", 1 },
87 { 0x0300, 0x38, "Memory", 1 },
88 /* { 0x0400, 0x100, "Sensor", 0 }, */
89 /* { 0x0500, 0x300, "ISP", 0 }, */
90 /* { 0x0800, 0x400, "JPEG", 0 }, */
91 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
92 { 0x1100, 0xb2, "LCD 1", 1 },
93 { 0x1200, 0x64, "LCD 2", 1 },
94 { 0x1400, 0x42, "MMC", 1 },
95 /* { 0x1500, 0x080, "MPU 0", 0 },
96 { 0x1580, 0x080, "MPU 1", 0 },
97 { 0x1600, 0x080, "Cmd Queue", 0 },
98 { 0x1680, 0x080, "RISC CPU", 0 },*/
99 { 0x1700, 0x400, "2D Unit", 1 },
100 /* { 0x1b00, 0x900, "3D Unit", 0 }, */
101 };
102
103 static inline void __reg_write(struct glamo_core *glamo,
104 uint16_t reg, uint16_t val)
105 {
106 writew(val, glamo->base + reg);
107 }
108
109 void glamo_reg_write(struct glamo_core *glamo,
110 uint16_t reg, uint16_t val)
111 {
112 spin_lock(&glamo->lock);
113 __reg_write(glamo, reg, val);
114 spin_unlock(&glamo->lock);
115 }
116 EXPORT_SYMBOL_GPL(glamo_reg_write);
117
118
119 static inline uint16_t __reg_read(struct glamo_core *glamo,
120 uint16_t reg)
121 {
122 return readw(glamo->base + reg);
123 }
124
125 uint16_t glamo_reg_read(struct glamo_core *glamo, uint16_t reg)
126 {
127 uint16_t val;
128 spin_lock(&glamo->lock);
129 val = __reg_read(glamo, reg);
130 spin_unlock(&glamo->lock);
131
132 return val;
133 }
134 EXPORT_SYMBOL_GPL(glamo_reg_read);
135
136 static void __reg_set_bit_mask(struct glamo_core *glamo,
137 uint16_t reg, uint16_t mask,
138 uint16_t val)
139 {
140 uint16_t tmp;
141
142 val &= mask;
143
144 tmp = __reg_read(glamo, reg);
145 tmp &= ~mask;
146 tmp |= val;
147 __reg_write(glamo, reg, tmp);
148 }
149
150 static void reg_set_bit_mask(struct glamo_core *glamo,
151 uint16_t reg, uint16_t mask,
152 uint16_t val)
153 {
154 spin_lock(&glamo->lock);
155 __reg_set_bit_mask(glamo, reg, mask, val);
156 spin_unlock(&glamo->lock);
157 }
158
159 static inline void __reg_set_bit(struct glamo_core *glamo,
160 uint16_t reg, uint16_t bit)
161 {
162 uint16_t tmp;
163 tmp = __reg_read(glamo, reg);
164 tmp |= bit;
165 __reg_write(glamo, reg, tmp);
166 }
167
168 static inline void __reg_clear_bit(struct glamo_core *glamo,
169 uint16_t reg, uint16_t bit)
170 {
171 uint16_t tmp;
172 tmp = __reg_read(glamo, reg);
173 tmp &= ~bit;
174 __reg_write(glamo, reg, tmp);
175 }
176
177 static void __reg_write_batch(struct glamo_core *glamo, uint16_t reg,
178 uint16_t count, uint16_t *values)
179 {
180 uint16_t end;
181 for (end = reg + count * 2; reg < end; reg += 2, ++values)
182 __reg_write(glamo, reg, *values);
183 }
184
185 static void __reg_read_batch(struct glamo_core *glamo, uint16_t reg,
186 uint16_t count, uint16_t *values)
187 {
188 uint16_t end;
189 for (end = reg + count * 2; reg < end; reg += 2, ++values)
190 *values = __reg_read(glamo, reg);
191 }
192
193 void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg,
194 uint16_t count, uint16_t *values)
195 {
196 spin_lock(&glamo->lock);
197 __reg_write_batch(glamo, reg, count, values);
198 spin_unlock(&glamo->lock);
199 }
200 EXPORT_SYMBOL(glamo_reg_write_batch);
201
202 void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg,
203 uint16_t count, uint16_t *values)
204 {
205 spin_lock(&glamo->lock);
206 __reg_read_batch(glamo, reg, count, values);
207 spin_unlock(&glamo->lock);
208 }
209 EXPORT_SYMBOL(glamo_reg_read_batch);
210
211 /***********************************************************************
212 * resources of sibling devices
213 ***********************************************************************/
214
215 static struct resource glamo_fb_resources[] = {
216 {
217 .name = "glamo-fb-regs",
218 .start = GLAMO_REGOFS_LCD,
219 .end = GLAMO_REGOFS_MMC - 1,
220 .flags = IORESOURCE_MEM,
221 }, {
222 .name = "glamo-fb-mem",
223 .start = GLAMO_OFFSET_FB,
224 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 };
228
229 static struct resource glamo_mmc_resources[] = {
230 {
231 .name = "glamo-mmc-regs",
232 .start = GLAMO_REGOFS_MMC,
233 .end = GLAMO_REGOFS_MPROC0 - 1,
234 .flags = IORESOURCE_MEM
235 }, {
236 .name = "glamo-mmc-mem",
237 .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
238 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
239 GLAMO_MMC_BUFFER_SIZE - 1,
240 .flags = IORESOURCE_MEM
241 }, {
242 .start = GLAMO_IRQ_MMC,
243 .end = GLAMO_IRQ_MMC,
244 .flags = IORESOURCE_IRQ,
245 },
246 };
247
248 enum glamo_cells {
249 GLAMO_CELL_FB,
250 GLAMO_CELL_MMC,
251 GLAMO_CELL_GPIO,
252 };
253
254 static const struct mfd_cell glamo_cells[] = {
255 [GLAMO_CELL_FB] = {
256 .name = "glamo-fb",
257 .num_resources = ARRAY_SIZE(glamo_fb_resources),
258 .resources = glamo_fb_resources,
259 },
260 [GLAMO_CELL_MMC] = {
261 .name = "glamo-mci",
262 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
263 .resources = glamo_mmc_resources,
264 },
265 [GLAMO_CELL_GPIO] = {
266 .name = "glamo-gpio",
267 },
268 };
269
270 /***********************************************************************
271 * IRQ demultiplexer
272 ***********************************************************************/
273 #define glamo_irq_bit(glamo, x) BIT(x - glamo->irq_base)
274
275 static inline struct glamo_core *irq_to_glamo(unsigned int irq)
276 {
277 return (struct glamo_core*)get_irq_chip_data(irq);
278 }
279
280 static void glamo_ack_irq(unsigned int irq)
281 {
282 struct glamo_core *glamo = irq_to_glamo(irq);
283 /* clear interrupt source */
284 __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, glamo_irq_bit(glamo, irq));
285 }
286
287 static void glamo_mask_irq(unsigned int irq)
288 {
289 struct glamo_core *glamo = irq_to_glamo(irq);
290
291 /* clear bit in enable register */
292 __reg_clear_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
293 }
294
295 static void glamo_unmask_irq(unsigned int irq)
296 {
297 struct glamo_core *glamo = irq_to_glamo(irq);
298
299 /* set bit in enable register */
300 __reg_set_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
301 }
302
303 static struct irq_chip glamo_irq_chip = {
304 .name = "glamo",
305 .ack = glamo_ack_irq,
306 .mask = glamo_mask_irq,
307 .unmask = glamo_unmask_irq,
308 };
309
310 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
311 {
312 struct glamo_core *glamo = get_irq_desc_chip_data(desc);
313 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
314
315 if (unlikely(desc->status & IRQ_INPROGRESS)) {
316 desc->status |= (IRQ_PENDING | IRQ_MASKED);
317 desc->chip->mask(irq);
318 desc->chip->ack(irq);
319 return;
320 }
321 kstat_incr_irqs_this_cpu(irq, desc);
322
323 desc->chip->ack(irq);
324 desc->status |= IRQ_INPROGRESS;
325
326 do {
327 uint16_t irqstatus;
328 int i;
329
330 if (unlikely((desc->status &
331 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
332 (IRQ_PENDING | IRQ_MASKED))) {
333 /* dealing with pending IRQ, unmasking */
334 desc->chip->unmask(irq);
335 desc->status &= ~IRQ_MASKED;
336 }
337
338 desc->status &= ~IRQ_PENDING;
339
340 /* read IRQ status register */
341 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
342 for (i = 0; i < 9; ++i) {
343 if (irqstatus & BIT(i))
344 generic_handle_irq(glamo->irq_base + i);
345 }
346
347 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
348
349 desc->status &= ~IRQ_INPROGRESS;
350 }
351
352 /*
353 sysfs
354 */
355
356 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
357 const char *buf, size_t count)
358 {
359 struct glamo_core *glamo = dev_get_drvdata(dev);
360 unsigned long reg = simple_strtoul(buf, &buf, 10);
361
362 printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
363 reg, simple_strtoul(buf, NULL, 10));
364
365 glamo_reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
366
367 return count;
368 }
369
370 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
371 char *buf)
372 {
373 struct glamo_core *glamo = dev_get_drvdata(dev);
374 int i, n;
375 char * end = buf;
376 const struct reg_range *rr = reg_range;
377
378 spin_lock(&glamo->lock);
379
380 for (i = 0; i < ARRAY_SIZE(reg_range); ++i, ++rr) {
381 if (!rr->dump)
382 continue;
383 end += sprintf(end, "\n%s\n", rr->name);
384 for (n = rr->start; n < rr->start + rr->count; n += 2) {
385 if ((n & 15) == 0)
386 end += sprintf(end, "\n%04X: ", n);
387 end += sprintf(end, "%04x ", __reg_read(glamo, n));
388 }
389 end += sprintf(end, "\n");
390 }
391 spin_unlock(&glamo->lock);
392
393 return end - buf;
394 }
395
396 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
397
398 struct glamo_engine_reg_set {
399 uint16_t reg;
400 uint16_t mask_suspended;
401 uint16_t mask_enabled;
402 };
403
404 struct glamo_engine_desc {
405 const char *name;
406 uint16_t hostbus;
407 const struct glamo_engine_reg_set *regs;
408 int num_regs;
409 };
410
411 static const struct glamo_engine_reg_set glamo_lcd_regs[] = {
412 { GLAMO_REG_CLOCK_LCD,
413 GLAMO_CLOCK_LCD_EN_M5CLK |
414 GLAMO_CLOCK_LCD_DG_M5CLK |
415 GLAMO_CLOCK_LCD_EN_DMCLK,
416
417 GLAMO_CLOCK_LCD_EN_DHCLK |
418 GLAMO_CLOCK_LCD_EN_DCLK
419 },
420 { GLAMO_REG_CLOCK_GEN5_1,
421 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK,
422
423 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
424 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
425 }
426 };
427
428 static const struct glamo_engine_reg_set glamo_mmc_regs[] = {
429 { GLAMO_REG_CLOCK_MMC,
430 GLAMO_CLOCK_MMC_EN_M9CLK |
431 GLAMO_CLOCK_MMC_DG_M9CLK,
432
433 GLAMO_CLOCK_MMC_EN_TCLK |
434 GLAMO_CLOCK_MMC_DG_TCLK
435 },
436 { GLAMO_REG_CLOCK_GEN5_1,
437 0,
438 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
439 }
440 };
441
442 static const struct glamo_engine_reg_set glamo_2d_regs[] = {
443 { GLAMO_REG_CLOCK_2D,
444 GLAMO_CLOCK_2D_EN_M7CLK |
445 GLAMO_CLOCK_2D_DG_M7CLK,
446
447 GLAMO_CLOCK_2D_EN_GCLK |
448 GLAMO_CLOCK_2D_DG_GCLK
449 },
450 { GLAMO_REG_CLOCK_GEN5_1,
451 0,
452 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
453 }
454 };
455
456 static const struct glamo_engine_reg_set glamo_cmdq_regs[] = {
457 { GLAMO_REG_CLOCK_2D,
458 GLAMO_CLOCK_2D_EN_M6CLK,
459 0
460 },
461 };
462
463 #define GLAMO_ENGINE(xname, xhostbus, xregs) { \
464 .name = xname, \
465 .hostbus = xhostbus, \
466 .num_regs = ARRAY_SIZE(xregs), \
467 .regs = xregs, \
468 }
469
470 static const struct glamo_engine_desc glamo_engines[] = {
471 [GLAMO_ENGINE_LCD] = GLAMO_ENGINE("LCD", GLAMO_HOSTBUS2_MMIO_EN_LCD,
472 glamo_lcd_regs),
473 [GLAMO_ENGINE_MMC] = GLAMO_ENGINE("MMC", GLAMO_HOSTBUS2_MMIO_EN_MMC,
474 glamo_mmc_regs),
475 [GLAMO_ENGINE_2D] = GLAMO_ENGINE("2D", GLAMO_HOSTBUS2_MMIO_EN_2D,
476 glamo_2d_regs),
477 [GLAMO_ENGINE_CMDQ] = GLAMO_ENGINE("CMDQ", GLAMO_HOSTBUS2_MMIO_EN_CQ,
478 glamo_cmdq_regs),
479 };
480
481 inline static const char *glamo_engine_name(enum glamo_engine engine)
482 {
483 return glamo_engines[engine].name;
484 }
485
486 /***********************************************************************
487 * 'engine' support
488 ***********************************************************************/
489
490 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
491 {
492 int i;
493 const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
494 const struct glamo_engine_reg_set *reg;
495
496 switch(engine) {
497 case GLAMO_ENGINE_LCD:
498 case GLAMO_ENGINE_MMC:
499 case GLAMO_ENGINE_2D:
500 case GLAMO_ENGINE_CMDQ:
501 break;
502 default:
503 return -EINVAL;
504 }
505
506 reg = engine_desc->regs;
507
508 __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
509 engine_desc->hostbus);
510 for (i = engine_desc->num_regs; i; --i, ++reg)
511 __reg_set_bit(glamo, reg->reg, reg->mask_suspended | reg->mask_enabled);
512
513 return 0;
514 }
515
516 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
517 {
518 int ret = 0;
519
520 spin_lock(&glamo->lock);
521
522 if (glamo->engine_state[engine] != GLAMO_ENGINE_ENABLED) {
523 ret = __glamo_engine_enable(glamo, engine);
524 if (!ret)
525 glamo->engine_state[engine] = GLAMO_ENGINE_ENABLED;
526 }
527
528 spin_unlock(&glamo->lock);
529
530 return ret;
531 }
532 EXPORT_SYMBOL_GPL(glamo_engine_enable);
533
534 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
535 {
536 int i;
537 const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
538 const struct glamo_engine_reg_set *reg;
539
540 switch(engine) {
541 case GLAMO_ENGINE_LCD:
542 case GLAMO_ENGINE_MMC:
543 case GLAMO_ENGINE_2D:
544 case GLAMO_ENGINE_CMDQ:
545 break;
546 default:
547 return -EINVAL;
548 }
549
550 reg = engine_desc->regs;
551
552 __reg_clear_bit(glamo, GLAMO_REG_HOSTBUS(2),
553 engine_desc->hostbus);
554 for (i = engine_desc->num_regs; i; --i, ++reg)
555 __reg_clear_bit(glamo, reg->reg, reg->mask_suspended | reg->mask_enabled);
556
557 return 0;
558 }
559 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
560 {
561 int ret = 0;
562
563 spin_lock(&glamo->lock);
564
565 if (glamo->engine_state[engine] != GLAMO_ENGINE_DISABLED) {
566 ret = __glamo_engine_disable(glamo, engine);
567 if (!ret)
568 glamo->engine_state[engine] = GLAMO_ENGINE_DISABLED;
569 }
570
571 spin_unlock(&glamo->lock);
572
573 return ret;
574 }
575 EXPORT_SYMBOL_GPL(glamo_engine_disable);
576
577 int __glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
578 {
579 int i;
580 const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
581 const struct glamo_engine_reg_set *reg;
582
583 switch(engine) {
584 case GLAMO_ENGINE_LCD:
585 case GLAMO_ENGINE_MMC:
586 case GLAMO_ENGINE_2D:
587 case GLAMO_ENGINE_CMDQ:
588 break;
589 default:
590 return -EINVAL;
591 }
592
593 reg = engine_desc->regs;
594
595 __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
596 engine_desc->hostbus);
597 for (i = engine_desc->num_regs; i; --i, ++reg) {
598 __reg_set_bit(glamo, reg->reg, reg->mask_suspended);
599 __reg_clear_bit(glamo, reg->reg, reg->mask_enabled);
600 }
601
602 return 0;
603 }
604
605 int glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
606 {
607 int ret = 0;
608
609 spin_lock(&glamo->lock);
610
611 if (glamo->engine_state[engine] != GLAMO_ENGINE_SUSPENDED) {
612 ret = __glamo_engine_suspend(glamo, engine);
613 if (!ret)
614 glamo->engine_state[engine] = GLAMO_ENGINE_SUSPENDED;
615 }
616
617 spin_unlock(&glamo->lock);
618
619 return ret;
620 }
621 EXPORT_SYMBOL_GPL(glamo_engine_suspend);
622
623 static const struct glamo_script reset_regs[] = {
624 [GLAMO_ENGINE_LCD] = {
625 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
626 },
627 [GLAMO_ENGINE_MMC] = {
628 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
629 },
630 [GLAMO_ENGINE_CMDQ] = {
631 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
632 },
633 [GLAMO_ENGINE_2D] = {
634 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
635 },
636 [GLAMO_ENGINE_JPEG] = {
637 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
638 },
639 };
640
641 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
642 {
643 uint16_t reg = reset_regs[engine].reg;
644 uint16_t val = reset_regs[engine].val;
645
646 if (engine >= ARRAY_SIZE(reset_regs)) {
647 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
648 return;
649 }
650
651 spin_lock(&glamo->lock);
652 __reg_set_bit(glamo, reg, val);
653 __reg_clear_bit(glamo, reg, val);
654 spin_unlock(&glamo->lock);
655 }
656 EXPORT_SYMBOL_GPL(glamo_engine_reset);
657
658 int glamo_pll_rate(struct glamo_core *glamo,
659 enum glamo_pll pll)
660 {
661 uint16_t reg;
662 unsigned int osci = glamo->pdata->osci_clock_rate;
663
664 switch (pll) {
665 case GLAMO_PLL1:
666 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
667 break;
668 case GLAMO_PLL2:
669 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
670 break;
671 default:
672 return -EINVAL;
673 }
674 return osci*reg;
675 }
676 EXPORT_SYMBOL_GPL(glamo_pll_rate);
677
678 int glamo_engine_reclock(struct glamo_core *glamo,
679 enum glamo_engine engine,
680 int hz)
681 {
682 int pll;
683 uint16_t reg, mask, div;
684
685 if (!hz)
686 return -EINVAL;
687
688 switch (engine) {
689 case GLAMO_ENGINE_LCD:
690 pll = GLAMO_PLL1;
691 reg = GLAMO_REG_CLOCK_GEN7;
692 mask = 0xff;
693 break;
694 case GLAMO_ENGINE_MMC:
695 pll = GLAMO_PLL1;
696 reg = GLAMO_REG_CLOCK_GEN8;
697 mask = 0xff;
698 break;
699 default:
700 dev_warn(&glamo->pdev->dev,
701 "reclock of engine 0x%x not supported\n", engine);
702 return -EINVAL;
703 break;
704 }
705
706 pll = glamo_pll_rate(glamo, pll);
707
708 div = pll / hz;
709
710 if (div != 0 && pll / div <= hz)
711 --div;
712
713 if (div > mask)
714 div = mask;
715
716 dev_dbg(&glamo->pdev->dev,
717 "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
718
719 reg_set_bit_mask(glamo, reg, mask, div);
720 mdelay(5); /* wait some time to stabilize */
721
722 return pll / (div + 1);
723 }
724 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
725
726 /***********************************************************************
727 * script support
728 ***********************************************************************/
729
730 #define GLAMO_SCRIPT_END 0xffff
731 #define GLAMO_SCRIPT_WAIT 0xfffe
732 #define GLAMO_SCRIPT_LOCK_PLL 0xfffd
733
734 /*
735 * couple of people reported artefacts with 2.6.28 changes, this
736 * allows reversion to 2.6.24 settings
737 */
738 static const uint16_t reg_0x200[] = {
739 0xe03, /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
740 0xef0, /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
741 0xea0, /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
742 0xe50, /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
743 0xe00, /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
744 0xef3, /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
745 0xea3, /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
746 0xe53, /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
747 };
748
749 static int glamo_run_script(struct glamo_core *glamo,
750 const struct glamo_script *script, int len,
751 int may_sleep)
752 {
753 int i;
754 const struct glamo_script *line = script;
755
756 for (i = 0; i < len; ++i, ++line) {
757 switch (line->reg) {
758 case GLAMO_SCRIPT_END:
759 return 0;
760 case GLAMO_SCRIPT_WAIT:
761 if (may_sleep)
762 msleep(line->val);
763 else
764 mdelay(line->val * 4);
765 break;
766 case GLAMO_SCRIPT_LOCK_PLL:
767 /* spin until PLLs lock */
768 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3);
769 break;
770 case 0x200:
771 __reg_write(glamo, line->reg, reg_0x200[slow_memory & 0x8]);
772 break;
773 default:
774 __reg_write(glamo, line->reg, line->val);
775 break;
776 }
777 }
778
779 return 0;
780 }
781
782 static const struct glamo_script glamo_init_script[] = {
783 { GLAMO_REG_CLOCK_HOST, 0x1000 },
784 { GLAMO_SCRIPT_WAIT, 2 },
785 { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
786 { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
787 { GLAMO_REG_CLOCK_LCD, 0x1000 },
788 { GLAMO_REG_CLOCK_MMC, 0x1000 },
789 { GLAMO_REG_CLOCK_ISP, 0x1000 },
790 { GLAMO_REG_CLOCK_ISP, 0x3000 },
791 { GLAMO_REG_CLOCK_JPEG, 0x1000 },
792 { GLAMO_REG_CLOCK_3D, 0x1000 },
793 { GLAMO_REG_CLOCK_3D, 0x3000 },
794 { GLAMO_REG_CLOCK_2D, 0x1000 },
795 { GLAMO_REG_CLOCK_2D, 0x3000 },
796 { GLAMO_REG_CLOCK_RISC1, 0x1000 },
797 { GLAMO_REG_CLOCK_MPEG, 0x1000 },
798 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
799 { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
800 { GLAMO_SCRIPT_WAIT, 2 },
801 { GLAMO_REG_CLOCK_HOST, 0x0000 },
802 { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
803 { GLAMO_REG_CLOCK_LCD, 0x0000 },
804 { GLAMO_REG_CLOCK_MMC, 0x0000 },
805 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
806 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
807 { GLAMO_SCRIPT_LOCK_PLL, 0 },
808 /*
809 * b9 of this register MUST be zero to get any interrupts on INT#
810 * the other set bits enable all the engine interrupt sources
811 */
812 { GLAMO_REG_IRQ_ENABLE, 0x0100 },
813 { GLAMO_REG_CLOCK_GEN6, 0x2000 },
814 { GLAMO_REG_CLOCK_GEN7, 0x0101 },
815 { GLAMO_REG_CLOCK_GEN8, 0x0100 },
816 { GLAMO_REG_CLOCK_HOST, 0x000d },
817 /*
818 * b7..b4 = 0 = no wait states on read or write
819 * b0 = 1 select PLL2 for Host interface, b1 = enable it
820 */
821 { GLAMO_REG_HOSTBUS(0), 0x0e03 /* this is replaced by script parser */ },
822 { GLAMO_REG_HOSTBUS(1), 0x07ff }, /* TODO: Disable all */
823 { GLAMO_REG_HOSTBUS(10), 0x0000 },
824 { GLAMO_REG_HOSTBUS(11), 0x4000 },
825 { GLAMO_REG_HOSTBUS(12), 0xf00e },
826
827 /* S-Media recommended "set tiling mode to 512 mode for memory access
828 * more efficiency when 640x480" */
829 { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
830 { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
831
832 { GLAMO_REG_MEM_TIMING1, 0x0108 },
833 { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
834 { GLAMO_REG_MEM_TIMING3, 0x0000 },
835 { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
836 { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
837 { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
838 { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
839 { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
840 { GLAMO_REG_MEM_TIMING9, 0x6006 },
841 { GLAMO_REG_MEM_TIMING10, 0x00ff },
842 { GLAMO_REG_MEM_TIMING11, 0x0001 },
843 { GLAMO_REG_MEM_POWER1, 0x0020 },
844 { GLAMO_REG_MEM_POWER2, 0x0000 },
845 { GLAMO_REG_MEM_DRAM1, 0x0000 },
846 { GLAMO_SCRIPT_WAIT, 1 },
847 { GLAMO_REG_MEM_DRAM1, 0xc100 },
848 { GLAMO_SCRIPT_WAIT, 1 },
849 { GLAMO_REG_MEM_DRAM1, 0xe100 },
850 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
851 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
852 };
853
854 /* Find out if we can support this version of the Glamo chip */
855 static int glamo_supported(struct glamo_core *glamo)
856 {
857 uint16_t dev_id, rev_id;
858
859 dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
860 rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
861
862 switch (dev_id) {
863 case 0x3650:
864 switch (rev_id) {
865 case GLAMO_CORE_REV_A2:
866 break;
867 case GLAMO_CORE_REV_A0:
868 case GLAMO_CORE_REV_A1:
869 case GLAMO_CORE_REV_A3:
870 dev_warn(&glamo->pdev->dev, "untested core revision "
871 "%04x, your mileage may vary\n", rev_id);
872 break;
873 default:
874 dev_warn(&glamo->pdev->dev, "unknown glamo revision "
875 "%04x, your mileage may vary\n", rev_id);
876 }
877 break;
878 default:
879 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
880 dev_id);
881 return 0;
882 }
883
884 dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
885 "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
886 glamo_pll_rate(glamo, GLAMO_PLL1),
887 glamo_pll_rate(glamo, GLAMO_PLL2));
888
889 return 1;
890 }
891
892 static int __init glamo_probe(struct platform_device *pdev)
893 {
894 int ret = 0, irq;
895 struct glamo_core *glamo;
896 struct resource *mem;
897
898 glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
899 if (!glamo)
900 return -ENOMEM;
901
902 spin_lock_init(&glamo->lock);
903
904 glamo->pdev = pdev;
905 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
906 glamo->irq = platform_get_irq(pdev, 0);
907 glamo->pdata = pdev->dev.platform_data;
908
909 if (glamo->irq < 0) {
910 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
911 ret = glamo->irq;
912 goto err_free;
913 }
914
915 if (!mem) {
916 dev_err(&pdev->dev, "Failed to get platform memory\n");
917 ret = -ENOENT;
918 goto err_free;
919 }
920
921 if (!glamo->pdata) {
922 dev_err(&pdev->dev, "Missing platform data\n");
923 ret = -ENOENT;
924 goto err_free;
925 }
926
927 /* only request the generic, hostbus and memory controller registers */
928 glamo->mem = request_mem_region(mem->start, GLAMO_REGOFS_VIDCAP,
929 pdev->name);
930
931 if (!glamo->mem) {
932 dev_err(&pdev->dev, "Failed to request io memory region\n");
933 ret = -ENOENT;
934 goto err_free;
935 }
936
937 glamo->base = ioremap(glamo->mem->start, resource_size(glamo->mem));
938 if (!glamo->base) {
939 dev_err(&pdev->dev, "Failed to ioremap() memory region\n");
940 goto err_release_mem_region;
941 }
942
943 /* confirm it isn't insane version */
944 if (!glamo_supported(glamo)) {
945 dev_err(&pdev->dev, "This version of the Glamo is not supported\n");
946 goto err_iounmap;
947 }
948
949 platform_set_drvdata(pdev, glamo);
950
951 /* sysfs */
952 ret = device_create_file(&pdev->dev, &dev_attr_regs);
953 if (ret < 0) {
954 dev_err(&pdev->dev, "Failed to create sysfs file\n");
955 goto err_iounmap;
956 }
957
958 /* init the chip with canned register set */
959 glamo_run_script(glamo, glamo_init_script,
960 ARRAY_SIZE(glamo_init_script), 1);
961
962 /*
963 * finally set the mfd interrupts up
964 */
965 for (irq = glamo->irq_base; irq < glamo->irq_base + GLAMO_NR_IRQS; ++irq) {
966 set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
967 set_irq_flags(irq, IRQF_VALID);
968 set_irq_chip_data(irq, glamo);
969 }
970
971 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
972 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
973 set_irq_chip_data(glamo->irq, glamo);
974 glamo->irq_works = 1;
975
976 ret = mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
977 ARRAY_SIZE(glamo_cells), mem, glamo->irq_base);
978
979 if (ret) {
980 dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret);
981 goto err_free_irqs;
982 }
983
984 dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
985 glamo_pll_rate(glamo, GLAMO_PLL1),
986 glamo_pll_rate(glamo, GLAMO_PLL2));
987
988 return 0;
989
990 err_free_irqs:
991 disable_irq(glamo->irq);
992 set_irq_chained_handler(glamo->irq, NULL);
993 set_irq_chip_data(glamo->irq, NULL);
994
995 for (irq = glamo->irq_base; irq < glamo->irq_base + GLAMO_NR_IRQS; irq++) {
996 set_irq_flags(irq, 0);
997 set_irq_chip(irq, NULL);
998 set_irq_chip_data(irq, NULL);
999 }
1000 err_iounmap:
1001 iounmap(glamo->base);
1002 err_release_mem_region:
1003 release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1004 err_free:
1005 platform_set_drvdata(pdev, NULL);
1006 kfree(glamo);
1007
1008 return ret;
1009 }
1010
1011 static int glamo_remove(struct platform_device *pdev)
1012 {
1013 struct glamo_core *glamo = platform_get_drvdata(pdev);
1014 int irq;
1015
1016 mfd_remove_devices(&pdev->dev);
1017
1018 disable_irq(glamo->irq);
1019 set_irq_chained_handler(glamo->irq, NULL);
1020 set_irq_chip_data(glamo->irq, NULL);
1021
1022 for (irq = glamo->irq_base; irq < glamo->irq_base + GLAMO_NR_IRQS; ++irq) {
1023 set_irq_flags(irq, 0);
1024 set_irq_chip(irq, NULL);
1025 set_irq_chip_data(irq, NULL);
1026 }
1027
1028 platform_set_drvdata(pdev, NULL);
1029 iounmap(glamo->base);
1030 release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1031 kfree(glamo);
1032
1033 return 0;
1034 }
1035
1036 #ifdef CONFIG_PM
1037 #if 0
1038 static struct glamo_script glamo_resume_script[] = {
1039
1040 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
1041 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
1042 { GLAMO_REG_DFT_GEN6, 1 },
1043 { 0xfffe, 100 },
1044 { 0xfffd, 0 },
1045 { 0x200, 0x0e03 },
1046
1047 /*
1048 * b9 of this register MUST be zero to get any interrupts on INT#
1049 * the other set bits enable all the engine interrupt sources
1050 */
1051 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
1052 { GLAMO_REG_CLOCK_HOST, 0x0018 },
1053 { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
1054
1055 { GLAMO_REG_MEM_DRAM1, 0x0000 },
1056 { 0xfffe, 1 },
1057 { GLAMO_REG_MEM_DRAM1, 0xc100 },
1058 { 0xfffe, 1 },
1059 { GLAMO_REG_MEM_DRAM1, 0xe100 },
1060 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
1061 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
1062 };
1063 #endif
1064
1065 #if 0
1066 static void glamo_power(struct glamo_core *glamo)
1067 {
1068 unsigned long flags;
1069
1070 spin_lock_irqsave(&glamo->lock, flags);
1071
1072 /*
1073 Power management
1074 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
1075 {
1076 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
1077 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
1078 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
1079 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
1080 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
1081 };
1082
1083 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1084 {
1085 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
1086 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
1087 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
1088 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
1089 };
1090
1091 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1092 {
1093 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
1094 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
1095 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
1096 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
1097 };
1098 */
1099 switch (new_state) {
1100 case GLAMO_POWER_ON:
1101
1102 /*
1103 * glamo state on resume is nondeterministic in some
1104 * fundamental way, it has also been observed that the
1105 * Glamo reset pin can get asserted by, eg, touching it with
1106 * a scope probe. So the only answer is to roll with it and
1107 * force an external reset on the Glamo during resume.
1108 */
1109
1110
1111 break;
1112
1113 case GLAMO_POWER_SUSPEND:
1114
1115 break;
1116 }
1117 spin_unlock_irqrestore(&glamo->lock, flags);
1118 }
1119 #endif
1120
1121 static int glamo_suspend(struct device *dev)
1122 {
1123 struct glamo_core *glamo = dev_get_drvdata(dev);
1124 int n;
1125
1126 spin_lock(&glamo->lock);
1127
1128 /* nuke interrupts */
1129 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1130
1131 /* take down each engine before we kill mem and pll */
1132 for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1133 if (glamo->engine_state != GLAMO_ENGINE_DISABLED)
1134 __glamo_engine_disable(glamo, n);
1135 }
1136
1137 /* enable self-refresh */
1138
1139 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1140 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1141 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1142 GLAMO_MEM_DRAM1_SELF_REFRESH |
1143 GLAMO_MEM_REFRESH_COUNT);
1144 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1145 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1146 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1147 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1148 GLAMO_MEM_DRAM1_SELF_REFRESH |
1149 GLAMO_MEM_REFRESH_COUNT);
1150
1151 /* force RAM into deep powerdown */
1152 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1153 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1154 (7 << 6) | /* tRC */
1155 (1 << 4) | /* tRP */
1156 (1 << 2) | /* tRCD */
1157 2); /* CAS latency */
1158
1159 /* disable clocks to memory */
1160 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1161
1162 /* all dividers from OSCI */
1163 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1164
1165 /* PLL2 into bypass */
1166 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1167
1168 __reg_write(glamo, GLAMO_BASIC_MMC_EN_TCLK_DLYA1, 0x0e00);
1169
1170 /* kill PLLS 1 then 2 */
1171 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1172 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1173
1174 spin_unlock(&glamo->lock);
1175
1176 return 0;
1177 }
1178
1179 static int glamo_resume(struct device *dev)
1180 {
1181 struct glamo_core *glamo = dev_get_drvdata(dev);
1182 int n;
1183
1184 (glamo->pdata->glamo_external_reset)(0);
1185 udelay(10);
1186 (glamo->pdata->glamo_external_reset)(1);
1187 mdelay(5);
1188
1189 spin_lock(&glamo->lock);
1190
1191 glamo_run_script(glamo, glamo_init_script,
1192 ARRAY_SIZE(glamo_init_script), 0);
1193
1194
1195 for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1196 switch (glamo->engine_state[n]) {
1197 case GLAMO_ENGINE_SUSPENDED:
1198 __glamo_engine_suspend(glamo, n);
1199 break;
1200 case GLAMO_ENGINE_ENABLED:
1201 __glamo_engine_enable(glamo, n);
1202 break;
1203 default:
1204 break;
1205 }
1206 }
1207
1208 spin_unlock(&glamo->lock);
1209
1210 return 0;
1211 }
1212
1213 static struct dev_pm_ops glamo_pm_ops = {
1214 .suspend = glamo_suspend,
1215 .resume = glamo_resume,
1216 };
1217
1218 #define GLAMO_PM_OPS (&glamo_pm_ops)
1219
1220 #else
1221 #define GLAMO_PM_OPS NULL
1222 #endif
1223
1224 static struct platform_driver glamo_driver = {
1225 .probe = glamo_probe,
1226 .remove = glamo_remove,
1227 .driver = {
1228 .name = "glamo3362",
1229 .owner = THIS_MODULE,
1230 .pm = GLAMO_PM_OPS,
1231 },
1232 };
1233
1234 static int __devinit glamo_init(void)
1235 {
1236 return platform_driver_register(&glamo_driver);
1237 }
1238
1239 static void __exit glamo_cleanup(void)
1240 {
1241 platform_driver_unregister(&glamo_driver);
1242 }
1243
1244 module_init(glamo_init);
1245 module_exit(glamo_cleanup);
1246
1247 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1248 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1249 MODULE_LICENSE("GPL");
1250 MODULE_ALIAS("platform:glamo3362");
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