target/linux/lantiq/patches-3.2/0062-MIPS-cleanup-reset-code.patch

   1 From 1748dc7b4974109040d0249ac1fc322c120eb528 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 16 Mar 2012 15:49:32 +0100
   4 Subject: [PATCH 62/70] MIPS: cleanup reset code
   5
   6 ---
   7  arch/mips/lantiq/xway/reset.c |   59 ++++++++++++++++++++++++++++++++++------
   8  1 files changed, 50 insertions(+), 9 deletions(-)
   9
  10 diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
  11 index ca2212a..8a5dff1 100644
  12 --- a/arch/mips/lantiq/xway/reset.c
  13 +++ b/arch/mips/lantiq/xway/reset.c
  14 @@ -11,6 +11,7 @@
  15  #include <linux/ioport.h>
  16  #include <linux/pm.h>
  17  #include <linux/export.h>
  18 +#include <linux/delay.h>
  19  #include <asm/reboot.h>
  20
  21  #include <lantiq_soc.h>
  22 @@ -20,12 +21,45 @@
  23  #define ltq_rcu_w32(x, y)      ltq_w32((x), ltq_rcu_membase + (y))
  24  #define ltq_rcu_r32(x)         ltq_r32(ltq_rcu_membase + (x))
  25
  26 -/* register definitions */
  27 -#define LTQ_RCU_RST            0x0010
  28 -#define LTQ_RCU_RST_ALL                0x40000000
  29 -
  30 -#define LTQ_RCU_RST_STAT       0x0014
  31 -#define LTQ_RCU_STAT_SHIFT     26
  32 +/* reset request register */
  33 +#define RCU_RST_REQ    0x0010
  34 +/* reset status register */
  35 +#define RCU_RST_STAT   0x0014
  36 +
  37 +/* reset cause */
  38 +#define RCU_STAT_SHIFT 26
  39 +/* Global SW Reset */
  40 +#define RCU_RD_SRST            BIT(30)
  41 +/* Memory Controller */
  42 +#define RCU_RD_MC              BIT(14)
  43 +/* PCI core */
  44 +#define RCU_RD_PCI             BIT(13)
  45 +/* Voice DFE/AFE */
  46 +#define RCU_RD_DFE_AFE         BIT(12)
  47 +/* DSL AFE */
  48 +#define RCU_RD_DSL_AFE         BIT(11)
  49 +/* SDIO core */
  50 +#define RCU_RD_SDIO            BIT(10)
  51 +/* DMA core */
  52 +#define RCU_RD_DMA             BIT(9)
  53 +/* PPE core */
  54 +#define RCU_RD_PPE             BIT(8)
  55 +/* ARC/DFE core */
  56 +#define RCU_RD_ARC_DFE         BIT(7)
  57 +/* AHB bus */
  58 +#define RCU_RD_AHB             BIT(6)
  59 +/* Ethernet MAC1 */
  60 +#define RCU_RD_ENET_MAC1       BIT(5)
  61 +/* USB and Phy core */
  62 +#define RCU_RD_USB             BIT(4)
  63 +/* CPU1 subsystem */
  64 +#define RCU_RD_CPU1            BIT(3)
  65 +/* FPI bus */
  66 +#define RCU_RD_FPI             BIT(2)
  67 +/* CPU0 subsystem */
  68 +#define RCU_RD_CPU0            BIT(1)
  69 +/* HW reset via HRST pin */
  70 +#define RCU_RD_HRST            BIT(0)
  71
  72  static struct resource ltq_rcu_resource =
  73         MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
  74 @@ -36,16 +70,23 @@ static void __iomem *ltq_rcu_membase;
  75  /* This function is used by the watchdog driver */
  76  int ltq_reset_cause(void)
  77  {
  78 -       u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
  79 -       return val >> LTQ_RCU_STAT_SHIFT;
  80 +       u32 val = ltq_rcu_r32(RCU_RST_STAT);
  81 +       return val >> RCU_STAT_SHIFT;
  82  }
  83  EXPORT_SYMBOL_GPL(ltq_reset_cause);
  84
  85 +void ltq_reset_once(unsigned int module, ulong usec)
  86 +{
  87 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
  88 +       udelay(usec);
  89 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
  90 +}
  91 +
  92  static void ltq_machine_restart(char *command)
  93  {
  94         pr_notice("System restart\n");
  95         local_irq_disable();
  96 -       ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
  97 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
  98         unreachable();
  99  }
 100
 101 --
 102 1.7.7.1
 103