target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/cpu.h>
  12 #include <bcm63xx_cpu.h>
  13 #include <bcm63xx_regs.h>
  14 #include <bcm63xx_io.h>
  15 #include <bcm63xx_irq.h>
  16
  17 const unsigned long *bcm63xx_regs_base;
  18 EXPORT_SYMBOL(bcm63xx_regs_base);
  19
  20 const int *bcm63xx_irqs;
  21 EXPORT_SYMBOL(bcm63xx_irqs);
  22
  23 static u16 bcm63xx_cpu_id;
  24 static u16 bcm63xx_cpu_rev;
  25 static unsigned int bcm63xx_cpu_freq;
  26 static unsigned int bcm63xx_memory_size;
  27
  28 /*
  29  * 6348 register sets and irqs
  30  */
  31 static const unsigned long bcm96348_regs_base[] = {
  32         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
  33         [RSET_PERF]             = BCM_6348_PERF_BASE,
  34         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
  35         [RSET_WDT]              = BCM_6348_WDT_BASE,
  36         [RSET_UART0]            = BCM_6348_UART0_BASE,
  37         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
  38         [RSET_SPI]              = BCM_6348_SPI_BASE,
  39         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
  40         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
  41         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
  42         [RSET_MPI]              = BCM_6348_MPI_BASE,
  43         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
  44         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
  45         [RSET_DSL]              = BCM_6348_DSL_BASE,
  46         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
  47         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
  48         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
  49         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
  50         [RSET_DDR]              = BCM_6348_DDR_BASE,
  51 };
  52
  53 static const int bcm96348_irqs[] = {
  54         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  55         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  56         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  57         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  58         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
  59         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
  60         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
  61         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
  62         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
  63         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
  64         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
  65         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
  66         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
  67 };
  68
  69 /*
  70  * 6358 register sets and irqs
  71  */
  72 static const unsigned long bcm96358_regs_base[] = {
  73         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
  74         [RSET_PERF]             = BCM_6358_PERF_BASE,
  75         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
  76         [RSET_WDT]              = BCM_6358_WDT_BASE,
  77         [RSET_UART0]            = BCM_6358_UART0_BASE,
  78         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
  79         [RSET_SPI]              = BCM_6358_SPI_BASE,
  80         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
  81         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
  82         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
  83         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
  84         [RSET_MPI]              = BCM_6358_MPI_BASE,
  85         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
  86         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
  87         [RSET_DSL]              = BCM_6358_DSL_BASE,
  88         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
  89         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
  90         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
  91         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
  92         [RSET_DDR]              = BCM_6358_DDR_BASE,
  93 };
  94
  95 static const int bcm96358_irqs[] = {
  96         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  97         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  98         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  99         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 100         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 101         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 102         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 103         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 104         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 105         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 106         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 107         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 108         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 109         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 110 };
 111
 112 u16 __bcm63xx_get_cpu_id(void)
 113 {
 114         return bcm63xx_cpu_id;
 115 }
 116
 117 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 118
 119 u16 bcm63xx_get_cpu_rev(void)
 120 {
 121         return bcm63xx_cpu_rev;
 122 }
 123
 124 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 125
 126 unsigned int bcm63xx_get_cpu_freq(void)
 127 {
 128         return bcm63xx_cpu_freq;
 129 }
 130
 131 unsigned int bcm63xx_get_memory_size(void)
 132 {
 133         return bcm63xx_memory_size;
 134 }
 135
 136 static unsigned int detect_cpu_clock(void)
 137 {
 138         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 139
 140         /*
 141          * frequency depends on PLL configuration:
 142          */
 143         if (BCMCPU_IS_6348()) {
 144                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 145                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 146                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 147                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 148                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 149                 n1 += 1;
 150                 n2 += 2;
 151                 m1 += 1;
 152         }
 153
 154         if (BCMCPU_IS_6358()) {
 155                 /* 16MHz * N1 * N2 / M1_CPU */
 156                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 157                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 158                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 159                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 160         }
 161
 162         return (16 * 1000000 * n1 * n2) / m1;
 163 }
 164
 165 /*
 166  * attempt to detect the amount of memory installed
 167  */
 168 static unsigned int detect_memory_size(void)
 169 {
 170         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 171         u32 val;
 172
 173         if (BCMCPU_IS_6348()) {
 174                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 175                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 176                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 177                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 178                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 179         }
 180
 181         if (BCMCPU_IS_6358()) {
 182                 val = bcm_memc_readl(MEMC_CFG_REG);
 183                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 184                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 185                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 186                 banks = 2;
 187         }
 188
 189         /* 0 => 11 address bits ... 2 => 13 address bits */
 190         rows += 11;
 191
 192         /* 0 => 8 address bits ... 2 => 10 address bits */
 193         cols += 8;
 194
 195         return 1 << (cols + rows + (is_32bits + 1) + banks);
 196 }
 197
 198 void __init bcm63xx_cpu_init(void)
 199 {
 200         unsigned int tmp, expected_cpu_id;
 201         struct cpuinfo_mips *c = &current_cpu_data;
 202
 203         /* soc registers location depends on cpu type */
 204         expected_cpu_id = 0;
 205
 206         switch (c->cputype) {
 207         case CPU_BCM6348:
 208                 expected_cpu_id = BCM6348_CPU_ID;
 209                 bcm63xx_regs_base = bcm96348_regs_base;
 210                 bcm63xx_irqs = bcm96348_irqs;
 211                 break;
 212         case CPU_BCM6358:
 213                 expected_cpu_id = BCM6358_CPU_ID;
 214                 bcm63xx_regs_base = bcm96358_regs_base;
 215                 bcm63xx_irqs = bcm96358_irqs;
 216                 break;
 217         }
 218
 219         /* really early to panic, but delaying panic would not help
 220          * since we will never get any working console */
 221         if (!expected_cpu_id)
 222                 panic("unsupported Broadcom CPU");
 223
 224         /*
 225          * bcm63xx_regs_base is set, we can access soc registers
 226          */
 227
 228         /* double check CPU type */
 229         tmp = bcm_perf_readl(PERF_REV_REG);
 230         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 231         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 232
 233         if (bcm63xx_cpu_id != expected_cpu_id)
 234                 panic("bcm63xx CPU id mismatch");
 235
 236         bcm63xx_cpu_freq = detect_cpu_clock();
 237         bcm63xx_memory_size = detect_memory_size();
 238
 239         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 240                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 241         printk(KERN_INFO "CPU frequency is %u MHz\n",
 242                bcm63xx_cpu_freq);
 243         printk(KERN_INFO "%uMB of RAM installed\n",
 244                bcm63xx_memory_size >> 20);
 245 }