target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/cpu.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #if defined(CONFIG_INCA_IP)
  27 #       include <asm/inca-ip.h>
  28 #elif defined(CONFIG_IFX_MIPS)
  29 #       include <asm/danube.h>
  30 #       include "ifx_cpu.c"
  31 #endif
  32 #include <asm/mipsregs.h>
  33
  34 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  35 {
  36 #if defined(CONFIG_INCA_IP)
  37         *INCA_IP_WDT_RST_REQ = 0x3f;
  38 #elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
  39         void (*f)(void) = (void *) 0xbfc00000;
  40
  41         f();
  42 #elif defined(CONFIG_IFX_MIPS)
  43         IFX_CPU_RESET;
  44 #endif
  45         fprintf(stderr, "*** reset failed ***\n");
  46         return 0;
  47 }
  48
  49 void flush_cache (ulong start_addr, ulong size)
  50 {
  51
  52 }
  53
  54 void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
  55         write_32bit_cp0_register(CP0_ENTRYLO0, low0);
  56         write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
  57         write_32bit_cp0_register(CP0_ENTRYLO1, low1);
  58         write_32bit_cp0_register(CP0_ENTRYHI, hi);
  59         write_32bit_cp0_register(CP0_INDEX, index);
  60         tlb_write_indexed();
  61 }