target/linux/atheros/files/arch/mips/atheros/ar5315/board.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/kernel.h>
  23 #include <linux/reboot.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/reboot.h>
  26 #include <asm/time.h>
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29 #include <ar531x.h>
  30 #include <linux/leds.h>
  31 #include <asm/gpio.h>
  32
  33 static int is_5315 = 0;
  34
  35 static struct resource ar5315_eth_res[] = {
  36         {
  37                 .name = "eth0_membase",
  38                 .flags = IORESOURCE_MEM,
  39                 .start = AR5315_ENET0,
  40                 .end = AR5315_ENET0 + 0x2000,
  41         },
  42         {
  43                 .name = "eth0_irq",
  44                 .flags = IORESOURCE_IRQ,
  45                 .start = AR5315_IRQ_ENET0_INTRS,
  46                 .end = AR5315_IRQ_ENET0_INTRS,
  47         },
  48 };
  49
  50 static struct ar531x_eth ar5315_eth_data = {
  51         .phy = 1,
  52         .mac = 0,
  53         .reset_base = AR5315_RESET,
  54         .reset_mac = AR5315_RESET_ENET0,
  55         .reset_phy = AR5315_RESET_EPHY0,
  56         .phy_base = AR5315_ENET0
  57 };
  58
  59 static struct platform_device ar5315_eth = {
  60         .id = 0,
  61         .name = "ar531x-eth",
  62         .dev.platform_data = &ar5315_eth_data,
  63         .resource = ar5315_eth_res,
  64         .num_resources = ARRAY_SIZE(ar5315_eth_res)
  65 };
  66
  67 static struct platform_device ar5315_wmac = {
  68         .id = 0,
  69         .name = "ar531x-wmac",
  70         /* FIXME: add resources */
  71 };
  72
  73 static struct resource ar5315_spiflash_res[] = {
  74         {
  75                 .name = "flash_base",
  76                 .flags = IORESOURCE_MEM,
  77                 .start = KSEG1ADDR(AR5315_SPI_READ),
  78                 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
  79         },
  80         {
  81                 .name = "flash_regs",
  82                 .flags = IORESOURCE_MEM,
  83                 .start = 0x11300000,
  84                 .end = 0x11300012,
  85         },
  86 };
  87
  88 static struct platform_device ar5315_spiflash = {
  89         .id = 0,
  90         .name = "spiflash",
  91         .resource = ar5315_spiflash_res,
  92         .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
  93 };
  94
  95 #ifdef CONFIG_LEDS_GPIO
  96 static struct gpio_led ar5315_leds[] = {
  97         { .name = "wlan", .gpio = 0, .active_low = 1, },
  98 };
  99
 100 static const struct gpio_led_platform_data ar5315_led_data = {
 101         .num_leds = ARRAY_SIZE(ar5315_leds),
 102         .leds = (void *) ar5315_leds,
 103 };
 104
 105 static struct platform_device ar5315_gpio_leds = {
 106         .name = "leds-gpio",
 107         .id = -1,
 108         .dev = {
 109                 .platform_data = (void *) &ar5315_led_data,
 110         }
 111 };
 112 #endif
 113
 114
 115 static __initdata struct platform_device *ar5315_devs[5];
 116
 117
 118
 119 static void *flash_regs;
 120
 121 static inline __u32 spiflash_regread32(int reg)
 122 {
 123         volatile __u32 *data = (__u32 *)(flash_regs + reg);
 124
 125         return (*data);
 126 }
 127
 128 static inline void spiflash_regwrite32(int reg, __u32 data)
 129 {
 130         volatile __u32 *addr = (__u32 *)(flash_regs + reg);
 131
 132         *addr = data;
 133 }
 134
 135 #define SPI_FLASH_CTL      0x00
 136 #define SPI_FLASH_OPCODE   0x04
 137 #define SPI_FLASH_DATA     0x08
 138
 139 static __u8 spiflash_probe(void)
 140 {
 141          __u32 reg;
 142
 143         do {
 144                 reg = spiflash_regread32(SPI_FLASH_CTL);
 145         } while (reg & SPI_CTL_BUSY);
 146
 147         spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
 148
 149         reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
 150                 (1 << 4) | SPI_CTL_START;
 151
 152         spiflash_regwrite32(SPI_FLASH_CTL, reg);
 153
 154         do {
 155                 reg = spiflash_regread32(SPI_FLASH_CTL);
 156         } while (reg & SPI_CTL_BUSY);
 157
 158         reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
 159         reg &= 0xff;
 160
 161         return (u8) reg;
 162 }
 163
 164
 165 #define STM_8MBIT_SIGNATURE     0x13
 166 #define STM_16MBIT_SIGNATURE    0x14
 167 #define STM_32MBIT_SIGNATURE    0x15
 168 #define STM_64MBIT_SIGNATURE    0x16
 169 #define STM_128MBIT_SIGNATURE   0x17
 170
 171
 172 static char __init *ar5315_flash_limit(void)
 173 {
 174         u8 sig;
 175         u32 flash_size = 0;
 176
 177         /* probe the flash chip size */
 178         flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
 179         sig = spiflash_probe();
 180         iounmap(flash_regs);
 181
 182         switch(sig) {
 183                 case STM_8MBIT_SIGNATURE:
 184                         flash_size = 0x00100000;
 185                         break;
 186                 case STM_16MBIT_SIGNATURE:
 187                         flash_size = 0x00200000;
 188                         break;
 189                 case STM_32MBIT_SIGNATURE:
 190                         flash_size = 0x00400000;
 191                         break;
 192                 case STM_64MBIT_SIGNATURE:
 193                         flash_size = 0x00800000;
 194                         break;
 195                 case STM_128MBIT_SIGNATURE:
 196                         flash_size = 0x01000000;
 197                         break;
 198         }
 199
 200         ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
 201         return (char *) ar5315_spiflash_res[0].end;
 202 }
 203
 204 int __init ar5315_init_devices(void)
 205 {
 206         struct ar531x_config *config;
 207         struct ar531x_boarddata *bcfg;
 208         int dev = 0;
 209
 210         if (!is_5315)
 211                 return 0;
 212
 213         /* Find board configuration */
 214         ar531x_find_config(ar5315_flash_limit());
 215         bcfg = (struct ar531x_boarddata *) board_config;
 216
 217 #if 0
 218         {
 219         /* Detect the hardware based on the device ID */
 220         u32 devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
 221                 switch(devid) {
 222                 case 0x9:
 223                         mips_machtype = MACH_ATHEROS_AR2317;
 224                         break;
 225                 /* FIXME: how can we detect AR2316? */
 226                 case 0x8:
 227                 default:
 228                         mips_machtype = MACH_ATHEROS_AR2315;
 229                         break;
 230                 }
 231         }
 232 #endif
 233
 234         config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
 235         config->board = board_config;
 236         config->radio = radio_config;
 237         config->unit = 0;
 238         config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
 239
 240         ar5315_eth_data.board_config = board_config;
 241         ar5315_eth_data.macaddr = bcfg->enet0Mac;
 242         ar5315_wmac.dev.platform_data = config;
 243
 244         ar5315_devs[dev++] = &ar5315_eth;
 245         ar5315_devs[dev++] = &ar5315_wmac;
 246         ar5315_devs[dev++] = &ar5315_spiflash;
 247
 248 #ifdef CONFIG_LEDS_GPIO
 249         ar5315_leds[0].gpio = bcfg->sysLedGpio;
 250         ar5315_devs[dev++] = &ar5315_gpio_leds;
 251 #endif
 252
 253         return platform_add_devices(ar5315_devs, dev);
 254 }
 255
 256 static void ar5315_halt(void)
 257 {
 258          while (1);
 259 }
 260
 261 static void ar5315_power_off(void)
 262 {
 263          ar5315_halt();
 264 }
 265
 266
 267 static void ar5315_restart(char *command)
 268 {
 269         unsigned int reg;
 270         for(;;) {
 271                 /* reset the system */
 272                 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
 273
 274                 /*
 275                  * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
 276                  */
 277                 gpio_direction_output(AR5315_RESET_GPIO, 0);
 278         }
 279 }
 280
 281
 282 /*
 283  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 284  * to determine the predevisor value.
 285  */
 286 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
 287     1,
 288     2,
 289     4,
 290     5
 291 };
 292
 293 static int __initdata PLLC_DIVIDE_TABLE[5] = {
 294     2,
 295     3,
 296     4,
 297     6,
 298     3
 299 };
 300
 301 static unsigned int __init
 302 ar5315_sys_clk(unsigned int clockCtl)
 303 {
 304     unsigned int pllcCtrl,cpuDiv;
 305     unsigned int pllcOut,refdiv,fdiv,divby2;
 306         unsigned int clkDiv;
 307
 308     pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
 309     refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
 310     refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
 311     fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
 312     divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
 313     divby2 += 1;
 314     pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
 315
 316
 317     /* clkm input selected */
 318         switch(clockCtl & CPUCLK_CLK_SEL_M) {
 319                 case 0:
 320                 case 1:
 321                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
 322                         break;
 323                 case 2:
 324                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
 325                         break;
 326                 default:
 327                         pllcOut = 40000000;
 328                         clkDiv = 1;
 329                         break;
 330         }
 331         cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
 332         cpuDiv = cpuDiv * 2 ?: 1;
 333         return (pllcOut/(clkDiv * cpuDiv));
 334 }
 335
 336 static inline unsigned int ar5315_cpu_frequency(void)
 337 {
 338     return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
 339 }
 340
 341 static inline unsigned int ar5315_apb_frequency(void)
 342 {
 343     return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
 344 }
 345
 346 static void __init ar5315_time_init(void)
 347 {
 348         mips_hpt_frequency = ar5315_cpu_frequency() / 2;
 349 }
 350
 351 void __init ar5315_prom_init(void)
 352 {
 353         u32 memsize, memcfg;
 354
 355         is_5315 = 1;
 356         memcfg = sysRegRead(AR5315_MEM_CFG);
 357         memsize   = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
 358         memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
 359         memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
 360         memsize <<= 3;
 361         add_memory_region(0, memsize, BOOT_MEM_RAM);
 362
 363         /* Initialize it to AR2315 for now. Real detection will be done
 364          * in ar5315_init_devices() */
 365         mips_machtype = MACH_ATHEROS_AR2315;
 366 }
 367
 368 void __init ar5315_plat_setup(void)
 369 {
 370         unsigned int config = read_c0_config();
 371
 372         /* Clear any lingering AHB errors */
 373         write_c0_config(config & ~0x3);
 374         sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
 375         sysRegRead(AR5315_AHB_ERR1);
 376         sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
 377
 378         board_time_init = ar5315_time_init;
 379
 380         _machine_restart = ar5315_restart;
 381         _machine_halt = ar5315_halt;
 382         pm_power_off = ar5315_power_off;
 383
 384         serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
 385 }
 386
 387 arch_initcall(ar5315_init_devices);