2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
11 * This file contains the configuration parameters for SAKC.
17 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
18 #define CONFIG_JzRISC 1 /* JzRISC core */
19 #define CONFIG_JZSOC 1 /* Jz SoC */
20 #define CONFIG_JZ4725 1 /* Jz4725 SoC */
21 #define CONFIG_JZ4740 1 /* Jz4740 SoC */
22 #define CONFIG_SAKC 1 /* SAKC board */
24 #define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */
26 //#define CONFIG_LCD 1 /* LCD support */
27 //#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
28 //#define CONFIG_SYS_WHITE_ON_BLACK 1
30 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
31 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
32 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
33 #define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
35 #define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
36 #define CONFIG_BAUDRATE 57600
37 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
41 #define CONFIG_DOS_PARTITION 1
42 #define CONFIG_SKIP_LOWLEVEL_INIT 1
43 #define CONFIG_BOARD_EARLY_INIT_F 1
44 #define CONFIG_SYS_NO_FLASH 1
45 #define CONFIG_ENV_OVERWRITE 1
47 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
48 #define CONFIG_BOOTDELAY 3
49 #define CONFIG_BOOTFILE "uImage" /* file to load */
50 #define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
51 #define CONFIG_EXTRA_ENV_SETTINGS 1
52 #define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
53 #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
56 * Command line configuration.
58 #define CONFIG_CMD_BDI /* bdinfo */
59 #define CONFIG_CMD_BOOTD /* bootd */
60 #define CONFIG_CMD_CONSOLE /* coninfo */
61 #define CONFIG_CMD_ECHO /* echo arguments */
62 #define CONFIG_CMD_IMI /* iminfo */
63 #define CONFIG_CMD_ITEST /* Integer (and string) test */
65 #define CONFIG_CMD_LOADB /* loadb */
66 #define CONFIG_CMD_LOADS /* loads */
67 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
68 #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
69 #define CONFIG_CMD_RUN /* run command in env variable */
70 #define CONFIG_CMD_SAVEENV /* saveenv */
71 #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
72 #define CONFIG_CMD_SOURCE /* "source" command support */
73 #define CONFIG_CMD_XIMG /* Load part of Multi Image */
75 #define CONFIG_CMD_NAND
76 #define CONFIG_CMD_MMC
77 #define CONFIG_CMD_FAT
80 * Serial download configuration
82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
83 #define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
86 * Miscellaneous configurable options
88 #define CONFIG_SYS_LONGHELP /* undef to save memory */
89 #define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */
90 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
92 /* Print Buffer Size */
93 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
95 #define CONFIG_SYS_MALLOC_LEN 128 * 1024
96 #define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
98 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
99 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
100 #define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
101 #define CONFIG_SYS_MEMTEST_START 0x80100000
102 #define CONFIG_SYS_MEMTEST_END 0x80800000
107 #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
110 * NAND FLASH configuration
112 /* NAND Boot config code */
113 #define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
115 #define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1
116 * if board nand flash is 2GB, set to 2
117 * for change the PAGE_SIZE and BLOCK_SIZE
118 * will delete when there is no 1GB flash
121 #define CONFIG_SYS_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE)
122 /* nand chip block size */
123 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10)
124 /* nand bad block was marked at this page in a block, start from 0 */
125 #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
126 /* ECC offset position in oob area, default value is 6 if it isn't defined */
127 #define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE)
128 #define CONFIG_SYS_MAX_NAND_DEVICE 1
129 #define NAND_MAX_CHIPS 1
130 #define CONFIG_SYS_NAND_BASE 0xB8000000
131 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
132 #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
135 * IPL (Initial Program Loader, integrated inside CPU)
136 * Will load first 8k from NAND (SPL) into cache and execute it from there.
138 * SPL (Secondary Program Loader)
139 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
140 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
141 * controller and the NAND controller so that the special U-Boot image can be
142 * loaded from NAND to SDRAM.
145 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
146 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
149 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
150 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
151 /* Start NUB from this addr*/
154 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
156 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
157 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
159 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
160 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
161 /* environment starts here */
162 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
164 /* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
165 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
170 #define CONFIG_NR_DRAM_BANKS 1
172 /* SDRAM paramters */
173 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
174 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
175 #define SDRAM_ROW 13 /* Row address: 11 to 13 */
176 #define SDRAM_COL 9 /* Column address: 8 to 12 */
177 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
179 /* SDRAM Timings, unit: ns */
180 #define SDRAM_TRAS 45 /* RAS# Active Time */
181 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */
182 #define SDRAM_TPC 20 /* RAS# Precharge Time */
183 #define SDRAM_TRWL 7 /* Write Latency Time */
184 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
187 * Cache Configuration
189 #define CONFIG_SYS_DCACHE_SIZE 16384
190 #define CONFIG_SYS_ICACHE_SIZE 16384
191 #define CONFIG_SYS_CACHELINE_SIZE 32
196 #define GPIO_SD_DETECT (2 * 32 + 27)
197 #define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
198 #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
200 #endif /* __CONFIG_H */
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