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f48c58052fecb2db91a0acc2e0513860f544480e
[openwrt.git] / target / linux / generic / patches-2.6.32 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
4 {
5 if (!cc->dev)
6 return; /* We don't have a ChipCommon */
7 + if (cc->dev->id.revision >= 11)
8 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
9 ssb_pmu_init(cc);
10 chipco_powercontrol_init(cc);
11 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
12 @@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
13 {
14 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
15 }
16 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
17
18 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
19 {
20 --- a/drivers/ssb/driver_chipcommon_pmu.c
21 +++ b/drivers/ssb/driver_chipcommon_pmu.c
22 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
23 case 0x5354:
24 ssb_pmu0_pllinit_r0(cc, crystalfreq);
25 break;
26 + case 0x4322:
27 + if (cc->pmu.rev == 2) {
28 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
29 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
30 + }
31 + break;
32 default:
33 ssb_printk(KERN_ERR PFX
34 "ERROR: PLL init unknown for device %04X\n",
35 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
36
37 switch (bus->chip_id) {
38 case 0x4312:
39 + case 0x4322:
40 /* We keep the default settings:
41 * min_msk = 0xCBB
42 * max_msk = 0x7FFFF
43 --- a/drivers/ssb/driver_gige.c
44 +++ b/drivers/ssb/driver_gige.c
45 @@ -12,6 +12,7 @@
46 #include <linux/ssb/ssb_driver_gige.h>
47 #include <linux/pci.h>
48 #include <linux/pci_regs.h>
49 +#include <linux/slab.h>
50
51
52 /*
53 --- a/drivers/ssb/driver_mipscore.c
54 +++ b/drivers/ssb/driver_mipscore.c
55 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
56 set_irq(dev, irq++);
57 }
58 break;
59 - /* fallthrough */
60 case SSB_DEV_PCI:
61 case SSB_DEV_ETHERNET:
62 case SSB_DEV_ETHERNET_GBIT:
63 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
64 set_irq(dev, irq++);
65 break;
66 }
67 + /* fallthrough */
68 + case SSB_DEV_EXTIF:
69 + set_irq(dev, 0);
70 + break;
71 }
72 }
73 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
74 --- a/drivers/ssb/driver_pcicore.c
75 +++ b/drivers/ssb/driver_pcicore.c
76 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
77 .pci_ops = &ssb_pcicore_pciops,
78 .io_resource = &ssb_pcicore_io_resource,
79 .mem_resource = &ssb_pcicore_mem_resource,
80 - .mem_offset = 0x24000000,
81 };
82
83 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
84 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
85 -
86 /* This function is called when doing a pci_enable_device().
87 * We must first check if the device is a device on the PCI-core bridge. */
88 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
89 {
90 - struct resource *res;
91 - int pos, size;
92 - u32 *base;
93 -
94 if (d->bus->ops != &ssb_pcicore_pciops) {
95 /* This is not a device on the PCI-core bridge. */
96 return -ENODEV;
97 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
98 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
99 pci_name(d));
100
101 - /* Fix up resource bases */
102 - for (pos = 0; pos < 6; pos++) {
103 - res = &d->resource[pos];
104 - if (res->flags & IORESOURCE_IO)
105 - base = &ssb_pcicore_pcibus_iobase;
106 - else
107 - base = &ssb_pcicore_pcibus_membase;
108 - res->flags |= IORESOURCE_PCI_FIXED;
109 - if (res->end) {
110 - size = res->end - res->start + 1;
111 - if (*base & (size - 1))
112 - *base = (*base + size) & ~(size - 1);
113 - res->start = *base;
114 - res->end = res->start + size - 1;
115 - *base += size;
116 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
117 - }
118 - /* Fix up PCI bridge BAR0 only */
119 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
120 - break;
121 - }
122 /* Fix up interrupt lines */
123 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
124 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
125 @@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
126 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
127
128 /* Enable interrupts for this device. */
129 - if (bus->host_pci &&
130 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
131 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
132 u32 coremask;
133
134 /* Calculate the "coremask" for the device. */
135 coremask = (1 << dev->core_index);
136
137 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
138 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
139 if (err)
140 goto out;
141 --- a/drivers/ssb/main.c
142 +++ b/drivers/ssb/main.c
143 @@ -18,6 +18,7 @@
144 #include <linux/dma-mapping.h>
145 #include <linux/pci.h>
146 #include <linux/mmc/sdio_func.h>
147 +#include <linux/slab.h>
148
149 #include <pcmcia/cs_types.h>
150 #include <pcmcia/cs.h>
151 @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
152 put_device(dev->dev);
153 }
154
155 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
156 +{
157 + if (drv)
158 + get_driver(&drv->drv);
159 + return drv;
160 +}
161 +
162 +static inline void ssb_driver_put(struct ssb_driver *drv)
163 +{
164 + if (drv)
165 + put_driver(&drv->drv);
166 +}
167 +
168 static int ssb_device_resume(struct device *dev)
169 {
170 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
171 @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
172 EXPORT_SYMBOL(ssb_bus_suspend);
173
174 #ifdef CONFIG_SSB_SPROM
175 -int ssb_devices_freeze(struct ssb_bus *bus)
176 +/** ssb_devices_freeze - Freeze all devices on the bus.
177 + *
178 + * After freezing no device driver will be handling a device
179 + * on this bus anymore. ssb_devices_thaw() must be called after
180 + * a successful freeze to reactivate the devices.
181 + *
182 + * @bus: The bus.
183 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
184 + */
185 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
186 {
187 - struct ssb_device *dev;
188 - struct ssb_driver *drv;
189 - int err = 0;
190 - int i;
191 - pm_message_t state = PMSG_FREEZE;
192 + struct ssb_device *sdev;
193 + struct ssb_driver *sdrv;
194 + unsigned int i;
195 +
196 + memset(ctx, 0, sizeof(*ctx));
197 + ctx->bus = bus;
198 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
199
200 - /* First check that we are capable to freeze all devices. */
201 for (i = 0; i < bus->nr_devices; i++) {
202 - dev = &(bus->devices[i]);
203 - if (!dev->dev ||
204 - !dev->dev->driver ||
205 - !device_is_registered(dev->dev))
206 - continue;
207 - drv = drv_to_ssb_drv(dev->dev->driver);
208 - if (!drv)
209 + sdev = ssb_device_get(&bus->devices[i]);
210 +
211 + if (!sdev->dev || !sdev->dev->driver ||
212 + !device_is_registered(sdev->dev)) {
213 + ssb_device_put(sdev);
214 continue;
215 - if (!drv->suspend) {
216 - /* Nope, can't suspend this one. */
217 - return -EOPNOTSUPP;
218 }
219 - }
220 - /* Now suspend all devices */
221 - for (i = 0; i < bus->nr_devices; i++) {
222 - dev = &(bus->devices[i]);
223 - if (!dev->dev ||
224 - !dev->dev->driver ||
225 - !device_is_registered(dev->dev))
226 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
227 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
228 + ssb_device_put(sdev);
229 continue;
230 - drv = drv_to_ssb_drv(dev->dev->driver);
231 - if (!drv)
232 - continue;
233 - err = drv->suspend(dev, state);
234 - if (err) {
235 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
236 - dev_name(dev->dev));
237 - goto err_unwind;
238 }
239 + sdrv->remove(sdev);
240 + ctx->device_frozen[i] = 1;
241 }
242
243 return 0;
244 -err_unwind:
245 - for (i--; i >= 0; i--) {
246 - dev = &(bus->devices[i]);
247 - if (!dev->dev ||
248 - !dev->dev->driver ||
249 - !device_is_registered(dev->dev))
250 - continue;
251 - drv = drv_to_ssb_drv(dev->dev->driver);
252 - if (!drv)
253 - continue;
254 - if (drv->resume)
255 - drv->resume(dev);
256 - }
257 - return err;
258 }
259
260 -int ssb_devices_thaw(struct ssb_bus *bus)
261 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
262 + *
263 + * This will re-attach the device drivers and re-init the devices.
264 + *
265 + * @ctx: The context structure from ssb_devices_freeze()
266 + */
267 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
268 {
269 - struct ssb_device *dev;
270 - struct ssb_driver *drv;
271 - int err;
272 - int i;
273 + struct ssb_bus *bus = ctx->bus;
274 + struct ssb_device *sdev;
275 + struct ssb_driver *sdrv;
276 + unsigned int i;
277 + int err, result = 0;
278
279 for (i = 0; i < bus->nr_devices; i++) {
280 - dev = &(bus->devices[i]);
281 - if (!dev->dev ||
282 - !dev->dev->driver ||
283 - !device_is_registered(dev->dev))
284 + if (!ctx->device_frozen[i])
285 continue;
286 - drv = drv_to_ssb_drv(dev->dev->driver);
287 - if (!drv)
288 + sdev = &bus->devices[i];
289 +
290 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
291 continue;
292 - if (SSB_WARN_ON(!drv->resume))
293 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
294 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
295 continue;
296 - err = drv->resume(dev);
297 +
298 + err = sdrv->probe(sdev, &sdev->id);
299 if (err) {
300 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
301 - dev_name(dev->dev));
302 + dev_name(sdev->dev));
303 + result = err;
304 }
305 + ssb_driver_put(sdrv);
306 + ssb_device_put(sdev);
307 }
308
309 - return 0;
310 + return result;
311 }
312 #endif /* CONFIG_SSB_SPROM */
313
314 @@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
315 #endif
316 break;
317 case SSB_BUSTYPE_SDIO:
318 -#ifdef CONFIG_SSB_SDIO
319 - sdev->irq = bus->host_sdio->dev.irq;
320 +#ifdef CONFIG_SSB_SDIOHOST
321 dev->parent = &bus->host_sdio->dev;
322 #endif
323 break;
324 @@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
325 if (!err) {
326 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
327 "PCI device %s\n", dev_name(&host_pci->dev));
328 + } else {
329 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
330 + " of SSB with error %d\n", err);
331 }
332
333 return err;
334 --- a/drivers/ssb/pci.c
335 +++ b/drivers/ssb/pci.c
336 @@ -17,6 +17,7 @@
337
338 #include <linux/ssb/ssb.h>
339 #include <linux/ssb/ssb_regs.h>
340 +#include <linux/slab.h>
341 #include <linux/pci.h>
342 #include <linux/delay.h>
343
344 @@ -167,7 +168,7 @@ err_pci:
345 }
346
347 /* Get the word-offset for a SSB_SPROM_XXX define. */
348 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
349 +#define SPOFF(offset) ((offset) / sizeof(u16))
350 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
351 #define SPEX16(_outvar, _offset, _mask, _shift) \
352 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
353 @@ -253,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
354 int i;
355
356 for (i = 0; i < bus->sprom_size; i++)
357 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
358 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
359
360 return 0;
361 }
362 @@ -284,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
363 ssb_printk("75%%");
364 else if (i % 2)
365 ssb_printk(".");
366 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
367 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
368 mmiowb();
369 msleep(20);
370 }
371 @@ -620,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
372 int err = -ENOMEM;
373 u16 *buf;
374
375 + if (!ssb_is_sprom_available(bus)) {
376 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
377 + return -ENODEV;
378 + }
379 +
380 + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
381 + SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
382 +
383 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
384 if (!buf)
385 goto out;
386 --- a/drivers/ssb/pcihost_wrapper.c
387 +++ b/drivers/ssb/pcihost_wrapper.c
388 @@ -12,6 +12,7 @@
389 */
390
391 #include <linux/pci.h>
392 +#include <linux/slab.h>
393 #include <linux/ssb/ssb.h>
394
395
396 --- a/drivers/ssb/pcmcia.c
397 +++ b/drivers/ssb/pcmcia.c
398 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
399 } \
400 } while (0)
401
402 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
403 - struct ssb_init_invariants *iv)
404 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
405 + tuple_t *tuple,
406 + void *priv)
407 +{
408 + struct ssb_sprom *sprom = priv;
409 +
410 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
411 + return -EINVAL;
412 + if (tuple->TupleDataLen != ETH_ALEN + 2)
413 + return -EINVAL;
414 + if (tuple->TupleData[1] != ETH_ALEN)
415 + return -EINVAL;
416 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
417 + return 0;
418 +};
419 +
420 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
421 + tuple_t *tuple,
422 + void *priv)
423 {
424 - tuple_t tuple;
425 - int res;
426 - unsigned char buf[32];
427 + struct ssb_init_invariants *iv = priv;
428 struct ssb_sprom *sprom = &iv->sprom;
429 struct ssb_boardinfo *bi = &iv->boardinfo;
430 const char *error_description;
431
432 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
433 + switch (tuple->TupleData[0]) {
434 + case SSB_PCMCIA_CIS_ID:
435 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
436 + (tuple->TupleDataLen != 7),
437 + "id tpl size");
438 + bi->vendor = tuple->TupleData[1] |
439 + ((u16)tuple->TupleData[2] << 8);
440 + break;
441 + case SSB_PCMCIA_CIS_BOARDREV:
442 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
443 + "boardrev tpl size");
444 + sprom->board_rev = tuple->TupleData[1];
445 + break;
446 + case SSB_PCMCIA_CIS_PA:
447 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
448 + (tuple->TupleDataLen != 10),
449 + "pa tpl size");
450 + sprom->pa0b0 = tuple->TupleData[1] |
451 + ((u16)tuple->TupleData[2] << 8);
452 + sprom->pa0b1 = tuple->TupleData[3] |
453 + ((u16)tuple->TupleData[4] << 8);
454 + sprom->pa0b2 = tuple->TupleData[5] |
455 + ((u16)tuple->TupleData[6] << 8);
456 + sprom->itssi_a = tuple->TupleData[7];
457 + sprom->itssi_bg = tuple->TupleData[7];
458 + sprom->maxpwr_a = tuple->TupleData[8];
459 + sprom->maxpwr_bg = tuple->TupleData[8];
460 + break;
461 + case SSB_PCMCIA_CIS_OEMNAME:
462 + /* We ignore this. */
463 + break;
464 + case SSB_PCMCIA_CIS_CCODE:
465 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
466 + "ccode tpl size");
467 + sprom->country_code = tuple->TupleData[1];
468 + break;
469 + case SSB_PCMCIA_CIS_ANTENNA:
470 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
471 + "ant tpl size");
472 + sprom->ant_available_a = tuple->TupleData[1];
473 + sprom->ant_available_bg = tuple->TupleData[1];
474 + break;
475 + case SSB_PCMCIA_CIS_ANTGAIN:
476 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
477 + "antg tpl size");
478 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
479 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
480 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
481 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
482 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
483 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
484 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
485 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
486 + break;
487 + case SSB_PCMCIA_CIS_BFLAGS:
488 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
489 + (tuple->TupleDataLen != 5),
490 + "bfl tpl size");
491 + sprom->boardflags_lo = tuple->TupleData[1] |
492 + ((u16)tuple->TupleData[2] << 8);
493 + break;
494 + case SSB_PCMCIA_CIS_LEDS:
495 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
496 + "leds tpl size");
497 + sprom->gpio0 = tuple->TupleData[1];
498 + sprom->gpio1 = tuple->TupleData[2];
499 + sprom->gpio2 = tuple->TupleData[3];
500 + sprom->gpio3 = tuple->TupleData[4];
501 + break;
502 + }
503 + return -ENOSPC; /* continue with next entry */
504 +
505 +error:
506 + ssb_printk(KERN_ERR PFX
507 + "PCMCIA: Failed to fetch device invariants: %s\n",
508 + error_description);
509 + return -ENODEV;
510 +}
511 +
512 +
513 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
514 + struct ssb_init_invariants *iv)
515 +{
516 + struct ssb_sprom *sprom = &iv->sprom;
517 + int res;
518 +
519 memset(sprom, 0xFF, sizeof(*sprom));
520 sprom->revision = 1;
521 sprom->boardflags_lo = 0;
522 sprom->boardflags_hi = 0;
523
524 /* First fetch the MAC address. */
525 - memset(&tuple, 0, sizeof(tuple));
526 - tuple.DesiredTuple = CISTPL_FUNCE;
527 - tuple.TupleData = buf;
528 - tuple.TupleDataMax = sizeof(buf);
529 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
530 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
531 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
532 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
533 - while (1) {
534 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
535 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
536 - break;
537 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
538 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
539 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
540 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
541 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
542 + ssb_pcmcia_get_mac, sprom);
543 + if (res != 0) {
544 + ssb_printk(KERN_ERR PFX
545 + "PCMCIA: Failed to fetch MAC address\n");
546 + return -ENODEV;
547 }
548 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
549 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
550
551 /* Fetch the vendor specific tuples. */
552 - memset(&tuple, 0, sizeof(tuple));
553 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
554 - tuple.TupleData = buf;
555 - tuple.TupleDataMax = sizeof(buf);
556 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
557 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
558 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
559 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
560 - while (1) {
561 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
562 - switch (tuple.TupleData[0]) {
563 - case SSB_PCMCIA_CIS_ID:
564 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
565 - (tuple.TupleDataLen != 7),
566 - "id tpl size");
567 - bi->vendor = tuple.TupleData[1] |
568 - ((u16)tuple.TupleData[2] << 8);
569 - break;
570 - case SSB_PCMCIA_CIS_BOARDREV:
571 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
572 - "boardrev tpl size");
573 - sprom->board_rev = tuple.TupleData[1];
574 - break;
575 - case SSB_PCMCIA_CIS_PA:
576 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
577 - (tuple.TupleDataLen != 10),
578 - "pa tpl size");
579 - sprom->pa0b0 = tuple.TupleData[1] |
580 - ((u16)tuple.TupleData[2] << 8);
581 - sprom->pa0b1 = tuple.TupleData[3] |
582 - ((u16)tuple.TupleData[4] << 8);
583 - sprom->pa0b2 = tuple.TupleData[5] |
584 - ((u16)tuple.TupleData[6] << 8);
585 - sprom->itssi_a = tuple.TupleData[7];
586 - sprom->itssi_bg = tuple.TupleData[7];
587 - sprom->maxpwr_a = tuple.TupleData[8];
588 - sprom->maxpwr_bg = tuple.TupleData[8];
589 - break;
590 - case SSB_PCMCIA_CIS_OEMNAME:
591 - /* We ignore this. */
592 - break;
593 - case SSB_PCMCIA_CIS_CCODE:
594 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
595 - "ccode tpl size");
596 - sprom->country_code = tuple.TupleData[1];
597 - break;
598 - case SSB_PCMCIA_CIS_ANTENNA:
599 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
600 - "ant tpl size");
601 - sprom->ant_available_a = tuple.TupleData[1];
602 - sprom->ant_available_bg = tuple.TupleData[1];
603 - break;
604 - case SSB_PCMCIA_CIS_ANTGAIN:
605 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
606 - "antg tpl size");
607 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
608 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
609 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
610 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
611 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
612 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
613 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
614 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
615 - break;
616 - case SSB_PCMCIA_CIS_BFLAGS:
617 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
618 - (tuple.TupleDataLen != 5),
619 - "bfl tpl size");
620 - sprom->boardflags_lo = tuple.TupleData[1] |
621 - ((u16)tuple.TupleData[2] << 8);
622 - break;
623 - case SSB_PCMCIA_CIS_LEDS:
624 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
625 - "leds tpl size");
626 - sprom->gpio0 = tuple.TupleData[1];
627 - sprom->gpio1 = tuple.TupleData[2];
628 - sprom->gpio2 = tuple.TupleData[3];
629 - sprom->gpio3 = tuple.TupleData[4];
630 - break;
631 - }
632 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
633 - if (res == -ENOSPC)
634 - break;
635 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
636 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
637 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
638 - }
639 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
640 + ssb_pcmcia_do_get_invariants, sprom);
641 + if ((res == 0) || (res == -ENOSPC))
642 + return 0;
643
644 - return 0;
645 -error:
646 ssb_printk(KERN_ERR PFX
647 - "PCMCIA: Failed to fetch device invariants: %s\n",
648 - error_description);
649 + "PCMCIA: Failed to fetch device invariants\n");
650 return -ENODEV;
651 }
652
653 --- a/drivers/ssb/scan.c
654 +++ b/drivers/ssb/scan.c
655 @@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
656 dev->bus = bus;
657 dev->ops = bus->ops;
658
659 - ssb_dprintk(KERN_INFO PFX
660 + printk(KERN_DEBUG PFX
661 "Core %d found: %s "
662 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
663 i, ssb_core_name(dev->id.coreid),
664 --- a/drivers/ssb/sprom.c
665 +++ b/drivers/ssb/sprom.c
666 @@ -14,6 +14,7 @@
667 #include "ssb_private.h"
668
669 #include <linux/ctype.h>
670 +#include <linux/slab.h>
671
672
673 static const struct ssb_sprom *fallback_sprom;
674 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
675 u16 *sprom;
676 int res = 0, err = -ENOMEM;
677 size_t sprom_size_words = bus->sprom_size;
678 + struct ssb_freeze_context freeze;
679
680 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
681 if (!sprom)
682 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
683 err = -ERESTARTSYS;
684 if (mutex_lock_interruptible(&bus->sprom_mutex))
685 goto out_kfree;
686 - err = ssb_devices_freeze(bus);
687 - if (err == -EOPNOTSUPP) {
688 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
689 - "No suspend support. Is CONFIG_PM enabled?\n");
690 - goto out_unlock;
691 - }
692 + err = ssb_devices_freeze(bus, &freeze);
693 if (err) {
694 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
695 goto out_unlock;
696 }
697 res = sprom_write(bus, sprom);
698 - err = ssb_devices_thaw(bus);
699 + err = ssb_devices_thaw(&freeze);
700 if (err)
701 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
702 out_unlock:
703 @@ -179,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
704 {
705 return fallback_sprom;
706 }
707 +
708 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
709 +bool ssb_is_sprom_available(struct ssb_bus *bus)
710 +{
711 + /* status register only exists on chipcomon rev >= 11 and we need check
712 + for >= 31 only */
713 + /* this routine differs from specs as we do not access SPROM directly
714 + on PCMCIA */
715 + if (bus->bustype == SSB_BUSTYPE_PCI &&
716 + bus->chipco.dev->id.revision >= 31)
717 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
718 +
719 + return true;
720 +}
721 --- a/drivers/ssb/ssb_private.h
722 +++ b/drivers/ssb/ssb_private.h
723 @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
724
725 /* core.c */
726 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
727 -extern int ssb_devices_freeze(struct ssb_bus *bus);
728 -extern int ssb_devices_thaw(struct ssb_bus *bus);
729 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
730 int ssb_for_each_bus_call(unsigned long data,
731 int (*func)(struct ssb_bus *bus, unsigned long data));
732 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
733
734 +struct ssb_freeze_context {
735 + /* Pointer to the bus */
736 + struct ssb_bus *bus;
737 + /* Boolean list to indicate whether a device is frozen on this bus. */
738 + bool device_frozen[SSB_MAX_NR_CORES];
739 +};
740 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
741 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
742 +
743 +
744
745 /* b43_pci_bridge.c */
746 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
747 extern int __init b43_pci_ssb_bridge_init(void);
748 extern void __exit b43_pci_ssb_bridge_exit(void);
749 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
750 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
751 static inline int b43_pci_ssb_bridge_init(void)
752 {
753 return 0;
754 @@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
755 static inline void b43_pci_ssb_bridge_exit(void)
756 {
757 }
758 -#endif /* CONFIG_SSB_PCIHOST */
759 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
760
761 #endif /* LINUX_SSB_PRIVATE_H_ */
762 --- a/include/linux/ssb/ssb.h
763 +++ b/include/linux/ssb/ssb.h
764 @@ -269,7 +269,8 @@ struct ssb_bus {
765
766 const struct ssb_bus_ops *ops;
767
768 - /* The core in the basic address register window. (PCI bus only) */
769 + /* The core currently mapped into the MMIO window.
770 + * Not valid on all host-buses. So don't use outside of SSB. */
771 struct ssb_device *mapped_device;
772 union {
773 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
774 @@ -281,14 +282,17 @@ struct ssb_bus {
775 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
776 spinlock_t bar_lock;
777
778 - /* The bus this backplane is running on. */
779 + /* The host-bus this backplane is running on. */
780 enum ssb_bustype bustype;
781 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
782 - struct pci_dev *host_pci;
783 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
784 - struct pcmcia_device *host_pcmcia;
785 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
786 - struct sdio_func *host_sdio;
787 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
788 + union {
789 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
790 + struct pci_dev *host_pci;
791 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
792 + struct pcmcia_device *host_pcmcia;
793 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
794 + struct sdio_func *host_sdio;
795 + };
796
797 /* See enum ssb_quirks */
798 unsigned int quirks;
799 @@ -301,6 +305,7 @@ struct ssb_bus {
800 /* ID information about the Chip. */
801 u16 chip_id;
802 u16 chip_rev;
803 + u16 sprom_offset;
804 u16 sprom_size; /* number of words in sprom */
805 u8 chip_package;
806
807 @@ -390,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
808
809 extern void ssb_bus_unregister(struct ssb_bus *bus);
810
811 +/* Does the device have an SPROM? */
812 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
813 +
814 /* Set a fallback SPROM.
815 * See kdoc at the function definition for complete documentation. */
816 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
817 --- a/include/linux/ssb/ssb_driver_chipcommon.h
818 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
819 @@ -53,6 +53,7 @@
820 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
821 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
822 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
823 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
824 #define SSB_CHIPCO_CORECTL 0x0008
825 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
826 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
827 @@ -385,6 +386,7 @@
828
829
830 /** Chip specific Chip-Status register contents. */
831 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
832 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
833 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
834 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
835 @@ -398,6 +400,18 @@
836 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
837 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
838
839 +/** Macros to determine SPROM presence based on Chip-Status register. */
840 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
841 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
842 + SSB_CHIPCO_CHST_4325_OTP_SEL)
843 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
844 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
845 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
846 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
847 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
848 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
849 + SSB_CHIPCO_CHST_4325_OTP_SEL))
850 +
851
852
853 /** Clockcontrol masks and values **/
854 @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
855 struct ssb_chipcommon {
856 struct ssb_device *dev;
857 u32 capabilities;
858 + u32 status;
859 /* Fast Powerup Delay constant */
860 u16 fast_pwrup_delay;
861 struct ssb_chipcommon_pmu pmu;
862 --- a/include/linux/ssb/ssb_regs.h
863 +++ b/include/linux/ssb/ssb_regs.h
864 @@ -170,26 +170,27 @@
865 #define SSB_SPROMSIZE_WORDS_R4 220
866 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
867 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
868 -#define SSB_SPROM_BASE 0x1000
869 -#define SSB_SPROM_REVISION 0x107E
870 +#define SSB_SPROM_BASE1 0x1000
871 +#define SSB_SPROM_BASE31 0x0800
872 +#define SSB_SPROM_REVISION 0x007E
873 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
874 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
875 #define SSB_SPROM_REVISION_CRC_SHIFT 8
876
877 /* SPROM Revision 1 */
878 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
879 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
880 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
881 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
882 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
883 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
884 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
885 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
886 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
887 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
888 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
889 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
890 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
891 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
892 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
893 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
894 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
895 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
896 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
897 -#define SSB_SPROM1_BINF 0x105C /* Board info */
898 +#define SSB_SPROM1_BINF 0x005C /* Board info */
899 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
900 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
901 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
902 @@ -197,63 +198,63 @@
903 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
904 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
905 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
906 -#define SSB_SPROM1_PA0B0 0x105E
907 -#define SSB_SPROM1_PA0B1 0x1060
908 -#define SSB_SPROM1_PA0B2 0x1062
909 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
910 +#define SSB_SPROM1_PA0B0 0x005E
911 +#define SSB_SPROM1_PA0B1 0x0060
912 +#define SSB_SPROM1_PA0B2 0x0062
913 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
914 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
915 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
916 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
917 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
918 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
919 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
920 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
921 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
922 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
923 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
924 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
925 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
926 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
927 -#define SSB_SPROM1_PA1B0 0x106A
928 -#define SSB_SPROM1_PA1B1 0x106C
929 -#define SSB_SPROM1_PA1B2 0x106E
930 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
931 +#define SSB_SPROM1_PA1B0 0x006A
932 +#define SSB_SPROM1_PA1B1 0x006C
933 +#define SSB_SPROM1_PA1B2 0x006E
934 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
935 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
936 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
937 #define SSB_SPROM1_ITSSI_A_SHIFT 8
938 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
939 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
940 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
941 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
942 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
943 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
944 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
945 #define SSB_SPROM1_AGAIN_A_SHIFT 8
946
947 /* SPROM Revision 2 (inherits from rev 1) */
948 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
949 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
950 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
951 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
952 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
953 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
954 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
955 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
956 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
957 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
958 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
959 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
960 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
961 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
962 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
963 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
964 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
965 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
966 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
967 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
968 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
969 #define SSB_SPROM2_OPO_VALUE 0x00FF
970 #define SSB_SPROM2_OPO_UNUSED 0xFF00
971 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
972 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
973
974 /* SPROM Revision 3 (inherits most data from rev 2) */
975 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
976 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
977 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
978 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
979 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
980 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
981 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
982 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
983 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
984 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
985 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
986 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
987 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
988 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
989 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
990 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
991 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
992 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
993 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
994 @@ -264,100 +265,100 @@
995 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
996
997 /* SPROM Revision 4 */
998 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
999 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
1000 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
1001 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
1002 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
1003 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
1004 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
1005 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1006 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1007 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1008 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
1009 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1010 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1011 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1012 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
1013 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
1014 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1015 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1016 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1017 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1018 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
1019 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
1020 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1021 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1022 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1023 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1024 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
1025 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
1026 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1027 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1028 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1029 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1030 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1031 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1032 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1033 #define SSB_SPROM4_AGAIN0_SHIFT 0
1034 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
1035 #define SSB_SPROM4_AGAIN1_SHIFT 8
1036 -#define SSB_SPROM4_AGAIN23 0x1060
1037 +#define SSB_SPROM4_AGAIN23 0x0060
1038 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
1039 #define SSB_SPROM4_AGAIN2_SHIFT 0
1040 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1041 #define SSB_SPROM4_AGAIN3_SHIFT 8
1042 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
1043 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
1044 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1045 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1046 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1047 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
1048 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
1049 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
1050 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
1051 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1052 #define SSB_SPROM4_ITSSI_A_SHIFT 8
1053 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
1054 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1055 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1056 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1057 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
1058 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1059 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1060 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1061 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
1062 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1063 -#define SSB_SPROM4_PA0B2 0x1086
1064 -#define SSB_SPROM4_PA1B0 0x108E
1065 -#define SSB_SPROM4_PA1B1 0x1090
1066 -#define SSB_SPROM4_PA1B2 0x1092
1067 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1068 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1069 +#define SSB_SPROM4_PA0B2 0x0086
1070 +#define SSB_SPROM4_PA1B0 0x008E
1071 +#define SSB_SPROM4_PA1B1 0x0090
1072 +#define SSB_SPROM4_PA1B2 0x0092
1073
1074 /* SPROM Revision 5 (inherits most data from rev 4) */
1075 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1076 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1077 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1078 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1079 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1080 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1081 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1082 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1083 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1084 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1085 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1086 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1087 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1088 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1089 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1090 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1091 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1092 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1093
1094 /* SPROM Revision 8 */
1095 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1096 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1097 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1098 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1099 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1100 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1101 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1102 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1103 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1104 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1105 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1106 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1107 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1108 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1109 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1110 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1111 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1112 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1113 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1114 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1115 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1116 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1117 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1118 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1119 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1120 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1121 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1122 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1123 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1124 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1125 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1126 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1127 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1128 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1129 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1130 #define SSB_SPROM8_AGAIN0_SHIFT 0
1131 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1132 #define SSB_SPROM8_AGAIN1_SHIFT 8
1133 -#define SSB_SPROM8_AGAIN23 0x10A0
1134 +#define SSB_SPROM8_AGAIN23 0x00A0
1135 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1136 #define SSB_SPROM8_AGAIN2_SHIFT 0
1137 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1138 #define SSB_SPROM8_AGAIN3_SHIFT 8
1139 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1140 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1141 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1142 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1143 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1144 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1145 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1146 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1147 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1148 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1149 #define SSB_SPROM8_RSSISMF2G 0x000F
1150 #define SSB_SPROM8_RSSISMC2G 0x00F0
1151 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
1152 @@ -365,7 +366,7 @@
1153 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1154 #define SSB_SPROM8_BXA2G 0x1800
1155 #define SSB_SPROM8_BXA2G_SHIFT 11
1156 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1157 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1158 #define SSB_SPROM8_RSSISMF5G 0x000F
1159 #define SSB_SPROM8_RSSISMC5G 0x00F0
1160 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1161 @@ -373,47 +374,47 @@
1162 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1163 #define SSB_SPROM8_BXA5G 0x1800
1164 #define SSB_SPROM8_BXA5G_SHIFT 11
1165 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1166 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1167 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1168 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1169 #define SSB_SPROM8_TRI5G_SHIFT 8
1170 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1171 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1172 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1173 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1174 #define SSB_SPROM8_TRI5GH_SHIFT 8
1175 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1176 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1177 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1178 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1179 #define SSB_SPROM8_RXPO5G_SHIFT 8
1180 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1181 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1182 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1183 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1184 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1185 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1186 -#define SSB_SPROM8_PA0B1 0x10C4
1187 -#define SSB_SPROM8_PA0B2 0x10C6
1188 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1189 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1190 +#define SSB_SPROM8_PA0B1 0x00C4
1191 +#define SSB_SPROM8_PA0B2 0x00C6
1192 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1193 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1194 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1195 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1196 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1197 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1198 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1199 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1200 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1201 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1202 -#define SSB_SPROM8_PA1B1 0x10CE
1203 -#define SSB_SPROM8_PA1B2 0x10D0
1204 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1205 -#define SSB_SPROM8_PA1LOB1 0x10D4
1206 -#define SSB_SPROM8_PA1LOB2 0x10D6
1207 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1208 -#define SSB_SPROM8_PA1HIB1 0x10DA
1209 -#define SSB_SPROM8_PA1HIB2 0x10DC
1210 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1211 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1212 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1213 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1214 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1215 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1216 +#define SSB_SPROM8_PA1B1 0x00CE
1217 +#define SSB_SPROM8_PA1B2 0x00D0
1218 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1219 +#define SSB_SPROM8_PA1LOB1 0x00D4
1220 +#define SSB_SPROM8_PA1LOB2 0x00D6
1221 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1222 +#define SSB_SPROM8_PA1HIB1 0x00DA
1223 +#define SSB_SPROM8_PA1HIB2 0x00DC
1224 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1225 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1226 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1227 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1228 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1229
1230 /* Values for SSB_SPROM1_BINF_CCODE */
1231 enum {
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