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[openwrt.git] / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-01-12 00:25:32.203973000 +0100
3 +++ linux.dev/arch/mips/Kconfig 2006-01-12 00:20:30.697130000 +0100
4 @@ -244,6 +244,17 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SYS_SUPPORTS_LITTLE_ENDIAN
16 + help
17 + Support for BCM947xx based boards
18 +
19 config LASAT
20 bool "Support for LASAT Networks platforms"
21 select DMA_NONCOHERENT
22 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
23 --- linux.old/arch/mips/Makefile 2006-01-12 00:25:32.223974250 +0100
24 +++ linux.dev/arch/mips/Makefile 2006-01-12 00:20:30.701130250 +0100
25 @@ -689,6 +689,13 @@
26 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
27
28 #
29 +# Broadcom BCM47XX boards
30 +#
31 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
32 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
33 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
34 +
35 +#
36 # SNI RM200 PCI
37 #
38 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
39 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
40 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-01-12 00:20:30.701130250 +0100
42 @@ -0,0 +1,6 @@
43 +#
44 +# Makefile for the BCM47xx specific kernel interface routines
45 +# under Linux.
46 +#
47 +
48 +obj-y := irq.o int-handler.o prom.o setup.o time.o pci.o
49 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
50 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2006-01-12 00:20:30.713131000 +0100
52 @@ -0,0 +1,6 @@
53 +#
54 +# Makefile for the BCM47xx specific kernel interface routines
55 +# under Linux.
56 +#
57 +
58 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
59 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
60 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
61 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2006-01-12 00:20:30.717131250 +0100
62 @@ -0,0 +1,481 @@
63 +/*
64 + * Misc useful routines to access NIC SROM/OTP .
65 + *
66 + * Copyright 2005, Broadcom Corporation
67 + * All Rights Reserved.
68 + *
69 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
70 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
71 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
72 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
73 + * $Id$
74 + */
75 +
76 +#include <typedefs.h>
77 +#include <osl.h>
78 +#include <bcmutils.h>
79 +#include <bcmsrom.h>
80 +#include <bcmdevs.h>
81 +#include <bcmendian.h>
82 +#include <pcicfg.h>
83 +#include <sbutils.h>
84 +
85 +#include <proto/ethernet.h> /* for sprom content groking */
86 +
87 +#define VARS_MAX 4096 /* should be reduced */
88 +
89 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
90 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
91 +
92 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
93 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
94 +
95 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
96 +
97 +/*
98 + * Initialize local vars from the right source for this platform.
99 + * Return 0 on success, nonzero on error.
100 + */
101 +int
102 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
103 +{
104 + ASSERT(bustype == BUSTYPE(bustype));
105 + if (vars == NULL || count == NULL)
106 + return (0);
107 +
108 + switch (BUSTYPE(bustype)) {
109 +
110 + case PCI_BUS:
111 + ASSERT(curmap); /* can not be NULL */
112 + return initvars_srom_pci(sbh, curmap, vars, count);
113 +
114 + default:
115 + return 0;
116 + }
117 + return (-1);
118 +}
119 +
120 +/* support only 16-bit word read from srom */
121 +int
122 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
123 +{
124 + void *srom;
125 + uint off, nw;
126 +
127 + ASSERT(bustype == BUSTYPE(bustype));
128 +
129 + /* check input - 16-bit access only */
130 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
131 + return 1;
132 +
133 + off = byteoff / 2;
134 + nw = nbytes / 2;
135 +
136 + if (BUSTYPE(bustype) == PCI_BUS) {
137 + if (!curmap)
138 + return 1;
139 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
140 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
141 + return 1;
142 + } else {
143 + return 1;
144 + }
145 +
146 + return 0;
147 +}
148 +
149 +/* support only 16-bit word write into srom */
150 +int
151 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
152 +{
153 + uint16 *srom;
154 + uint i, off, nw, crc_range;
155 + uint16 image[SPROM_SIZE], *p;
156 + uint8 crc;
157 + volatile uint32 val32;
158 +
159 + ASSERT(bustype == BUSTYPE(bustype));
160 +
161 + /* check input - 16-bit access only */
162 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
163 + return 1;
164 +
165 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
166 +
167 + /* if changes made inside crc cover range */
168 + if (byteoff < crc_range) {
169 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
170 + /* read data including entire first 64 words from srom */
171 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
172 + return 1;
173 + /* make changes */
174 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
175 + /* calculate crc */
176 + htol16_buf(image, crc_range);
177 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
178 + ltoh16_buf(image, crc_range);
179 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
180 + p = image;
181 + off = 0;
182 + } else {
183 + p = buf;
184 + off = byteoff / 2;
185 + nw = nbytes / 2;
186 + }
187 +
188 + if (BUSTYPE(bustype) == PCI_BUS) {
189 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
190 + /* enable writes to the SPROM */
191 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
192 + val32 |= SPROM_WRITEEN;
193 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
194 + bcm_mdelay(WRITE_ENABLE_DELAY);
195 + /* write srom */
196 + for (i = 0; i < nw; i++) {
197 + W_REG(&srom[off + i], p[i]);
198 + bcm_mdelay(WRITE_WORD_DELAY);
199 + }
200 + /* disable writes to the SPROM */
201 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
202 + } else {
203 + return 1;
204 + }
205 +
206 + bcm_mdelay(WRITE_ENABLE_DELAY);
207 + return 0;
208 +}
209 +
210 +
211 +/*
212 + * Read in and validate sprom.
213 + * Return 0 on success, nonzero on error.
214 + */
215 +static int
216 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
217 +{
218 + int err = 0;
219 + uint i;
220 +
221 + /* read the sprom */
222 + for (i = 0; i < nwords; i++)
223 + buf[i] = R_REG(&sprom[wordoff + i]);
224 +
225 + if (check_crc) {
226 + /* fixup the endianness so crc8 will pass */
227 + htol16_buf(buf, nwords * 2);
228 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
229 + err = 1;
230 + /* now correct the endianness of the byte array */
231 + ltoh16_buf(buf, nwords * 2);
232 + }
233 +
234 + return err;
235 +}
236 +
237 +/*
238 +* Create variable table from memory.
239 +* Return 0 on success, nonzero on error.
240 +*/
241 +static int
242 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
243 +{
244 + int c = (int)(end - start);
245 +
246 + /* do it only when there is more than just the null string */
247 + if (c > 1) {
248 + char *vp = MALLOC(osh, c);
249 + ASSERT(vp);
250 + if (!vp)
251 + return BCME_NOMEM;
252 + bcopy(start, vp, c);
253 + *vars = vp;
254 + *count = c;
255 + }
256 + else {
257 + *vars = NULL;
258 + *count = 0;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +/*
265 + * Initialize nonvolatile variable table from sprom.
266 + * Return 0 on success, nonzero on error.
267 + */
268 +static int
269 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
270 +{
271 + uint16 w, b[64];
272 + uint8 sromrev;
273 + struct ether_addr ea;
274 + char eabuf[32];
275 + uint32 w32;
276 + int woff, i;
277 + char *vp, *base;
278 + osl_t *osh = sb_osh(sbh);
279 + int err;
280 +
281 + /*
282 + * Apply CRC over SROM content regardless SROM is present or not,
283 + * and use variable <devpath>sromrev's existance in flash to decide
284 + * if we should return an error when CRC fails or read SROM variables
285 + * from flash.
286 + */
287 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
288 +
289 + /* top word of sprom contains version and crc8 */
290 + sromrev = b[63] & 0xff;
291 + /* bcm4401 sroms misprogrammed */
292 + if (sromrev == 0x10)
293 + sromrev = 1;
294 +
295 + /* srom version check */
296 + if (sromrev > 3)
297 + return (-2);
298 +
299 + ASSERT(vars);
300 + ASSERT(count);
301 +
302 + base = vp = MALLOC(osh, VARS_MAX);
303 + ASSERT(vp);
304 + if (!vp)
305 + return -2;
306 +
307 + vp += sprintf(vp, "sromrev=%d", sromrev);
308 + vp++;
309 +
310 + if (sromrev >= 3) {
311 + /* New section takes over the 3th hardware function space */
312 +
313 + /* Words 22+23 are 11a (mid) ofdm power offsets */
314 + w32 = ((uint32)b[23] << 16) | b[22];
315 + vp += sprintf(vp, "ofdmapo=%d", w32);
316 + vp++;
317 +
318 + /* Words 24+25 are 11a (low) ofdm power offsets */
319 + w32 = ((uint32)b[25] << 16) | b[24];
320 + vp += sprintf(vp, "ofdmalpo=%d", w32);
321 + vp++;
322 +
323 + /* Words 26+27 are 11a (high) ofdm power offsets */
324 + w32 = ((uint32)b[27] << 16) | b[26];
325 + vp += sprintf(vp, "ofdmahpo=%d", w32);
326 + vp++;
327 +
328 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
329 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
330 + vp += sprintf(vp, "gpiotimerval=%d", w32);
331 +
332 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
333 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
334 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
335 + vp += sprintf(vp, "gpiotimerval=%d", w32);
336 +
337 + vp++;
338 + }
339 +
340 + if (sromrev >= 2) {
341 + /* New section takes over the 4th hardware function space */
342 +
343 + /* Word 29 is max power 11a high/low */
344 + w = b[29];
345 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
346 + vp++;
347 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
348 + vp++;
349 +
350 + /* Words 30-32 set the 11alow pa settings,
351 + * 33-35 are the 11ahigh ones.
352 + */
353 + for (i = 0; i < 3; i++) {
354 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
355 + vp++;
356 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
357 + vp++;
358 + }
359 + w = b[59];
360 + if (w == 0)
361 + vp += sprintf(vp, "ccode=");
362 + else
363 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
364 + vp++;
365 +
366 + }
367 +
368 + /* parameter section of sprom starts at byte offset 72 */
369 + woff = 72/2;
370 +
371 + /* first 6 bytes are il0macaddr */
372 + ea.octet[0] = (b[woff] >> 8) & 0xff;
373 + ea.octet[1] = b[woff] & 0xff;
374 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
375 + ea.octet[3] = b[woff+1] & 0xff;
376 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
377 + ea.octet[5] = b[woff+2] & 0xff;
378 + woff += ETHER_ADDR_LEN/2 ;
379 + bcm_ether_ntoa((uchar*)&ea, eabuf);
380 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
381 + vp++;
382 +
383 + /* next 6 bytes are et0macaddr */
384 + ea.octet[0] = (b[woff] >> 8) & 0xff;
385 + ea.octet[1] = b[woff] & 0xff;
386 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
387 + ea.octet[3] = b[woff+1] & 0xff;
388 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
389 + ea.octet[5] = b[woff+2] & 0xff;
390 + woff += ETHER_ADDR_LEN/2 ;
391 + bcm_ether_ntoa((uchar*)&ea, eabuf);
392 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
393 + vp++;
394 +
395 + /* next 6 bytes are et1macaddr */
396 + ea.octet[0] = (b[woff] >> 8) & 0xff;
397 + ea.octet[1] = b[woff] & 0xff;
398 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
399 + ea.octet[3] = b[woff+1] & 0xff;
400 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
401 + ea.octet[5] = b[woff+2] & 0xff;
402 + woff += ETHER_ADDR_LEN/2 ;
403 + bcm_ether_ntoa((uchar*)&ea, eabuf);
404 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
405 + vp++;
406 +
407 + /*
408 + * Enet phy settings one or two singles or a dual
409 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
410 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
411 + * Bit 14 : Mdio for enet0
412 + * Bit 15 : Mdio for enet1
413 + */
414 + w = b[woff];
415 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
416 + vp++;
417 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
418 + vp++;
419 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
420 + vp++;
421 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
422 + vp++;
423 +
424 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
425 + w = b[46];
426 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
427 + vp++;
428 +
429 + if (sromrev > 1)
430 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
431 + else
432 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
433 + vp++;
434 +
435 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
436 + vp++;
437 +
438 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
439 + vp++;
440 +
441 + /* Words 47-49 set the (wl) pa settings */
442 + woff = 47;
443 +
444 + for (i = 0; i < 3; i++) {
445 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
446 + vp++;
447 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
448 + vp++;
449 + }
450 +
451 + /*
452 + * Words 50-51 set the customer-configured wl led behavior.
453 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
454 + * LED behavior values defined in wlioctl.h .
455 + */
456 + w = b[50];
457 + if ((w != 0) && (w != 0xffff)) {
458 + /* gpio0 */
459 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
460 + vp++;
461 +
462 + /* gpio1 */
463 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
464 + vp++;
465 + }
466 + w = b[51];
467 + if ((w != 0) && (w != 0xffff)) {
468 + /* gpio2 */
469 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
470 + vp++;
471 +
472 + /* gpio3 */
473 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
474 + vp++;
475 + }
476 +
477 + /* Word 52 is max power 0/1 */
478 + w = b[52];
479 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
480 + vp++;
481 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
482 + vp++;
483 +
484 + /* Word 56 is idle tssi target 0/1 */
485 + w = b[56];
486 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
487 + vp++;
488 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
489 + vp++;
490 +
491 + /* Word 57 is boardflags, if not programmed make it zero */
492 + w32 = (uint32)b[57];
493 + if (w32 == 0xffff) w32 = 0;
494 + if (sromrev > 1) {
495 + /* Word 28 is the high bits of boardflags */
496 + w32 |= (uint32)b[28] << 16;
497 + }
498 + vp += sprintf(vp, "boardflags=%d", w32);
499 + vp++;
500 +
501 + /* Word 58 is antenna gain 0/1 */
502 + w = b[58];
503 + vp += sprintf(vp, "ag0=%d", w & 0xff);
504 + vp++;
505 +
506 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
507 + vp++;
508 +
509 + if (sromrev == 1) {
510 + /* set the oem string */
511 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
512 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
513 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
514 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
515 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
516 + vp++;
517 + } else if (sromrev == 2) {
518 + /* Word 60 OFDM tx power offset from CCK level */
519 + /* OFDM Power Offset - opo */
520 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
521 + vp++;
522 + } else {
523 + /* Word 60: cck power offsets */
524 + vp += sprintf(vp, "cckpo=%d", b[60]);
525 + vp++;
526 +
527 + /* Words 61+62: 11g ofdm power offsets */
528 + w32 = ((uint32)b[62] << 16) | b[61];
529 + vp += sprintf(vp, "ofdmgpo=%d", w32);
530 + vp++;
531 + }
532 +
533 + /* final nullbyte terminator */
534 + *vp++ = '\0';
535 +
536 + ASSERT((vp - base) <= VARS_MAX);
537 +
538 + err = initvars_table(osh, base, vp, vars, count);
539 +
540 + MFREE(osh, base, VARS_MAX);
541 + return err;
542 +}
543 +
544 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
545 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
546 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2006-01-12 00:20:30.717131250 +0100
547 @@ -0,0 +1,356 @@
548 +/*
549 + * Misc useful OS-independent routines.
550 + *
551 + * Copyright 2005, Broadcom Corporation
552 + * All Rights Reserved.
553 + *
554 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
555 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
556 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
557 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
558 + * $Id$
559 + */
560 +
561 +#include <typedefs.h>
562 +#include <osl.h>
563 +#include <sbutils.h>
564 +#include <bcmnvram.h>
565 +#include <bcmutils.h>
566 +#include <bcmendian.h>
567 +#include <bcmdevs.h>
568 +
569 +unsigned char bcm_ctype[] = {
570 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
571 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
572 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
573 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
574 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
575 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
576 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
577 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
578 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
579 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
580 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
581 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
582 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
583 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
584 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
585 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
586 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
587 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
588 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
589 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
590 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
591 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
592 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
593 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
594 +};
595 +
596 +uchar
597 +bcm_toupper(uchar c)
598 +{
599 + if (bcm_islower(c))
600 + c -= 'a'-'A';
601 + return (c);
602 +}
603 +
604 +ulong
605 +bcm_strtoul(char *cp, char **endp, uint base)
606 +{
607 + ulong result, value;
608 + bool minus;
609 +
610 + minus = FALSE;
611 +
612 + while (bcm_isspace(*cp))
613 + cp++;
614 +
615 + if (cp[0] == '+')
616 + cp++;
617 + else if (cp[0] == '-') {
618 + minus = TRUE;
619 + cp++;
620 + }
621 +
622 + if (base == 0) {
623 + if (cp[0] == '0') {
624 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
625 + base = 16;
626 + cp = &cp[2];
627 + } else {
628 + base = 8;
629 + cp = &cp[1];
630 + }
631 + } else
632 + base = 10;
633 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
634 + cp = &cp[2];
635 + }
636 +
637 + result = 0;
638 +
639 + while (bcm_isxdigit(*cp) &&
640 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
641 + result = result*base + value;
642 + cp++;
643 + }
644 +
645 + if (minus)
646 + result = (ulong)(result * -1);
647 +
648 + if (endp)
649 + *endp = (char *)cp;
650 +
651 + return (result);
652 +}
653 +
654 +uint
655 +bcm_atoi(char *s)
656 +{
657 + uint n;
658 +
659 + n = 0;
660 +
661 + while (bcm_isdigit(*s))
662 + n = (n * 10) + *s++ - '0';
663 + return (n);
664 +}
665 +
666 +/* return pointer to location of substring 'needle' in 'haystack' */
667 +char*
668 +bcmstrstr(char *haystack, char *needle)
669 +{
670 + int len, nlen;
671 + int i;
672 +
673 + if ((haystack == NULL) || (needle == NULL))
674 + return (haystack);
675 +
676 + nlen = strlen(needle);
677 + len = strlen(haystack) - nlen + 1;
678 +
679 + for (i = 0; i < len; i++)
680 + if (bcmp(needle, &haystack[i], nlen) == 0)
681 + return (&haystack[i]);
682 + return (NULL);
683 +}
684 +
685 +char*
686 +bcmstrcat(char *dest, const char *src)
687 +{
688 + strcpy(&dest[strlen(dest)], src);
689 + return (dest);
690 +}
691 +
692 +
693 +char*
694 +bcm_ether_ntoa(char *ea, char *buf)
695 +{
696 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
697 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
698 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
699 + return (buf);
700 +}
701 +
702 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
703 +int
704 +bcm_ether_atoe(char *p, char *ea)
705 +{
706 + int i = 0;
707 +
708 + for (;;) {
709 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
710 + if (!*p++ || i == 6)
711 + break;
712 + }
713 +
714 + return (i == 6);
715 +}
716 +
717 +void
718 +bcm_mdelay(uint ms)
719 +{
720 + uint i;
721 +
722 + for (i = 0; i < ms; i++) {
723 + OSL_DELAY(1000);
724 + }
725 +}
726 +
727 +/*
728 + * Search the name=value vars for a specific one and return its value.
729 + * Returns NULL if not found.
730 + */
731 +char*
732 +getvar(char *vars, char *name)
733 +{
734 + char *s;
735 + int len;
736 +
737 + len = strlen(name);
738 +
739 + /* first look in vars[] */
740 + for (s = vars; s && *s; ) {
741 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
742 + return (&s[len+1]);
743 +
744 + while (*s++)
745 + ;
746 + }
747 +
748 + /* then query nvram */
749 + return (BCMINIT(nvram_get)(name));
750 +}
751 +
752 +/*
753 + * Search the vars for a specific one and return its value as
754 + * an integer. Returns 0 if not found.
755 + */
756 +int
757 +getintvar(char *vars, char *name)
758 +{
759 + char *val;
760 +
761 + if ((val = getvar(vars, name)) == NULL)
762 + return (0);
763 +
764 + return (bcm_strtoul(val, NULL, 0));
765 +}
766 +
767 +
768 +/* Search for token in comma separated token-string */
769 +static int
770 +findmatch(char *string, char *name)
771 +{
772 + uint len;
773 + char *c;
774 +
775 + len = strlen(name);
776 + while ((c = strchr(string, ',')) != NULL) {
777 + if (len == (uint)(c - string) && !strncmp(string, name, len))
778 + return 1;
779 + string = c + 1;
780 + }
781 +
782 + return (!strcmp(string, name));
783 +}
784 +
785 +/* Return gpio pin number assigned to the named pin */
786 +/*
787 +* Variable should be in format:
788 +*
789 +* gpio<N>=pin_name,pin_name
790 +*
791 +* This format allows multiple features to share the gpio with mutual
792 +* understanding.
793 +*
794 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
795 +* and if def_pin is not used by others.
796 +*/
797 +uint
798 +getgpiopin(char *vars, char *pin_name, uint def_pin)
799 +{
800 + char name[] = "gpioXXXX";
801 + char *val;
802 + uint pin;
803 +
804 + /* Go thru all possibilities till a match in pin name */
805 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
806 + sprintf(name, "gpio%d", pin);
807 + val = getvar(vars, name);
808 + if (val && findmatch(val, pin_name))
809 + return pin;
810 + }
811 +
812 + if (def_pin != GPIO_PIN_NOTDEFINED) {
813 + /* make sure the default pin is not used by someone else */
814 + sprintf(name, "gpio%d", def_pin);
815 + if (getvar(vars, name)) {
816 + def_pin = GPIO_PIN_NOTDEFINED;
817 + }
818 + }
819 +
820 + return def_pin;
821 +}
822 +
823 +
824 +/*******************************************************************************
825 + * crc8
826 + *
827 + * Computes a crc8 over the input data using the polynomial:
828 + *
829 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
830 + *
831 + * The caller provides the initial value (either CRC8_INIT_VALUE
832 + * or the previous returned value) to allow for processing of
833 + * discontiguous blocks of data. When generating the CRC the
834 + * caller is responsible for complementing the final return value
835 + * and inserting it into the byte stream. When checking, a final
836 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
837 + *
838 + * Reference: Dallas Semiconductor Application Note 27
839 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
840 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
841 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
842 + *
843 + ******************************************************************************/
844 +
845 +static uint8 crc8_table[256] = {
846 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
847 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
848 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
849 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
850 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
851 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
852 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
853 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
854 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
855 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
856 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
857 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
858 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
859 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
860 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
861 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
862 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
863 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
864 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
865 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
866 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
867 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
868 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
869 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
870 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
871 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
872 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
873 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
874 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
875 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
876 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
877 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
878 +};
879 +
880 +#define CRC_INNER_LOOP(n, c, x) \
881 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
882 +
883 +uint8
884 +hndcrc8(
885 + uint8 *pdata, /* pointer to array of data to process */
886 + uint nbytes, /* number of input data bytes to process */
887 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
888 +)
889 +{
890 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
891 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
892 + while (nbytes-- > 0)
893 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
894 +
895 + return crc;
896 +}
897 +
898 +#ifdef notdef
899 +#define CLEN 1499
900 +#define CBUFSIZ (CLEN+4)
901 +#define CNBUFS 5
902 +
903 +#endif
904 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
905 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
906 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2006-01-12 00:20:30.717131250 +0100
907 @@ -0,0 +1,234 @@
908 +/*
909 + * NVRAM variable manipulation (Linux kernel half)
910 + *
911 + * Copyright 2001-2003, Broadcom Corporation
912 + * All Rights Reserved.
913 + *
914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
918 + *
919 + * $Id$
920 + */
921 +
922 +#include <linux/config.h>
923 +#include <linux/init.h>
924 +#include <linux/module.h>
925 +#include <linux/kernel.h>
926 +#include <linux/string.h>
927 +#include <asm/io.h>
928 +#include <asm/uaccess.h>
929 +
930 +#include <typedefs.h>
931 +#include <osl.h>
932 +#include <bcmendian.h>
933 +#include <bcmutils.h>
934 +
935 +#define NVRAM_SIZE (0x1ff0)
936 +static char _nvdata[NVRAM_SIZE] __initdata;
937 +static char _valuestr[256] __initdata;
938 +
939 +/*
940 + * TLV types. These codes are used in the "type-length-value"
941 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
942 + *
943 + * The layout of the flash/nvram is as follows:
944 + *
945 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
946 + *
947 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
948 + * The "length" field marks the length of the data section, not
949 + * including the type and length fields.
950 + *
951 + * Environment variables are stored as follows:
952 + *
953 + * <type_env> <length> <flags> <name> = <value>
954 + *
955 + * If bit 0 (low bit) is set, the length is an 8-bit value.
956 + * If bit 0 (low bit) is clear, the length is a 16-bit value
957 + *
958 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
959 + * indicates the size of the length field.
960 + *
961 + * Flags are from the constants below:
962 + *
963 + */
964 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
965 +#define ENV_LENGTH_8BITS 0x01
966 +
967 +#define ENV_TYPE_USER 0x80
968 +
969 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
970 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
971 +
972 +/*
973 + * The actual TLV types we support
974 + */
975 +
976 +#define ENV_TLV_TYPE_END 0x00
977 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
978 +
979 +/*
980 + * Environment variable flags
981 + */
982 +
983 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
984 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
985 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
986 +
987 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
988 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
989 +
990 +
991 +/* *********************************************************************
992 + * _nvram_read(buffer,offset,length)
993 + *
994 + * Read data from the NVRAM device
995 + *
996 + * Input parameters:
997 + * buffer - destination buffer
998 + * offset - offset of data to read
999 + * length - number of bytes to read
1000 + *
1001 + * Return value:
1002 + * number of bytes read, or <0 if error occured
1003 + ********************************************************************* */
1004 +static int
1005 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1006 +{
1007 + int i;
1008 + if (offset > NVRAM_SIZE)
1009 + return -1;
1010 +
1011 + for ( i = 0; i < length; i++) {
1012 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1013 + }
1014 + return length;
1015 +}
1016 +
1017 +
1018 +static char*
1019 +_strnchr(const char *dest,int c,size_t cnt)
1020 +{
1021 + while (*dest && (cnt > 0)) {
1022 + if (*dest == c) return (char *) dest;
1023 + dest++;
1024 + cnt--;
1025 + }
1026 + return NULL;
1027 +}
1028 +
1029 +
1030 +
1031 +/*
1032 + * Core support API: Externally visible.
1033 + */
1034 +
1035 +/*
1036 + * Get the value of an NVRAM variable
1037 + * @param name name of variable to get
1038 + * @return value of variable or NULL if undefined
1039 + */
1040 +
1041 +char*
1042 +cfe_env_get(unsigned char *nv_buf, char* name)
1043 +{
1044 + int size;
1045 + unsigned char *buffer;
1046 + unsigned char *ptr;
1047 + unsigned char *envval;
1048 + unsigned int reclen;
1049 + unsigned int rectype;
1050 + int offset;
1051 + int flg;
1052 +
1053 + size = NVRAM_SIZE;
1054 + buffer = &_nvdata[0];
1055 +
1056 + ptr = buffer;
1057 + offset = 0;
1058 +
1059 + /* Read the record type and length */
1060 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1061 + goto error;
1062 + }
1063 +
1064 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1065 +
1066 + /* Adjust pointer for TLV type */
1067 + rectype = *(ptr);
1068 + offset++;
1069 + size--;
1070 +
1071 + /*
1072 + * Read the length. It can be either 1 or 2 bytes
1073 + * depending on the code
1074 + */
1075 + if (rectype & ENV_LENGTH_8BITS) {
1076 + /* Read the record type and length - 8 bits */
1077 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1078 + goto error;
1079 + }
1080 + reclen = *(ptr);
1081 + size--;
1082 + offset++;
1083 + }
1084 + else {
1085 + /* Read the record type and length - 16 bits, MSB first */
1086 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1087 + goto error;
1088 + }
1089 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1090 + size -= 2;
1091 + offset += 2;
1092 + }
1093 +
1094 + if (reclen > size)
1095 + break; /* should not happen, bad NVRAM */
1096 +
1097 + switch (rectype) {
1098 + case ENV_TLV_TYPE_ENV:
1099 + /* Read the TLV data */
1100 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1101 + goto error;
1102 + flg = *ptr++;
1103 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1104 + if (envval) {
1105 + *envval++ = '\0';
1106 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1107 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1108 +#if 0
1109 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1110 +#endif
1111 + if(!strcmp(ptr, name)){
1112 + return _valuestr;
1113 + }
1114 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1115 + return _valuestr;
1116 + }
1117 + break;
1118 +
1119 + default:
1120 + /* Unknown TLV type, skip it. */
1121 + break;
1122 + }
1123 +
1124 + /*
1125 + * Advance to next TLV
1126 + */
1127 +
1128 + size -= (int)reclen;
1129 + offset += reclen;
1130 +
1131 + /* Read the next record type */
1132 + ptr = buffer;
1133 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1134 + goto error;
1135 + }
1136 +
1137 +error:
1138 + return NULL;
1139 +
1140 +}
1141 +
1142 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1143 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1144 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2006-01-12 00:20:30.717131250 +0100
1145 @@ -0,0 +1,102 @@
1146 +/*
1147 + * Linux OS Independent Layer
1148 + *
1149 + * Copyright 2005, Broadcom Corporation
1150 + * All Rights Reserved.
1151 + *
1152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1156 + *
1157 + * $Id$
1158 + */
1159 +
1160 +#define LINUX_OSL
1161 +
1162 +#include <typedefs.h>
1163 +#include <bcmendian.h>
1164 +#include <linux/module.h>
1165 +#include <linuxver.h>
1166 +#include <osl.h>
1167 +#include <bcmutils.h>
1168 +#include <linux/delay.h>
1169 +#ifdef mips
1170 +#include <asm/paccess.h>
1171 +#endif
1172 +#include <pcicfg.h>
1173 +
1174 +#define PCI_CFG_RETRY 10
1175 +
1176 +#define OS_HANDLE_MAGIC 0x1234abcd
1177 +#define BCM_MEM_FILENAME_LEN 24
1178 +
1179 +typedef struct bcm_mem_link {
1180 + struct bcm_mem_link *prev;
1181 + struct bcm_mem_link *next;
1182 + uint size;
1183 + int line;
1184 + char file[BCM_MEM_FILENAME_LEN];
1185 +} bcm_mem_link_t;
1186 +
1187 +struct os_handle {
1188 + uint magic;
1189 + void *pdev;
1190 + uint malloced;
1191 + uint failed;
1192 + bcm_mem_link_t *dbgmem_list;
1193 +};
1194 +
1195 +uint32
1196 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1197 +{
1198 + uint val;
1199 + uint retry=PCI_CFG_RETRY;
1200 +
1201 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1202 +
1203 + /* only 4byte access supported */
1204 + ASSERT(size == 4);
1205 +
1206 + do {
1207 + pci_read_config_dword(osh->pdev, offset, &val);
1208 + if (val != 0xffffffff)
1209 + break;
1210 + } while (retry--);
1211 +
1212 +
1213 + return (val);
1214 +}
1215 +
1216 +void
1217 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1218 +{
1219 + uint retry=PCI_CFG_RETRY;
1220 +
1221 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1222 +
1223 + /* only 4byte access supported */
1224 + ASSERT(size == 4);
1225 +
1226 + do {
1227 + pci_write_config_dword(osh->pdev, offset, val);
1228 + if (offset!=PCI_BAR0_WIN)
1229 + break;
1230 + if (osl_pci_read_config(osh,offset,size) == val)
1231 + break;
1232 + } while (retry--);
1233 +
1234 +}
1235 +
1236 +void
1237 +osl_delay(uint usec)
1238 +{
1239 + uint d;
1240 +
1241 + while (usec > 0) {
1242 + d = MIN(usec, 1000);
1243 + udelay(d);
1244 + usec -= d;
1245 + }
1246 +}
1247 +
1248 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1249 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1250 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2006-01-12 00:20:30.717131250 +0100
1251 @@ -0,0 +1,192 @@
1252 +/*
1253 + * NVRAM variable manipulation (Linux kernel half)
1254 + *
1255 + * Copyright 2005, Broadcom Corporation
1256 + * All Rights Reserved.
1257 + *
1258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1262 + *
1263 + * $Id$
1264 + */
1265 +
1266 +#include <linux/config.h>
1267 +#include <linux/init.h>
1268 +#include <linux/module.h>
1269 +#include <linux/kernel.h>
1270 +#include <linux/string.h>
1271 +#include <linux/interrupt.h>
1272 +#include <linux/spinlock.h>
1273 +#include <linux/slab.h>
1274 +#include <asm/bootinfo.h>
1275 +#include <asm/addrspace.h>
1276 +#include <asm/io.h>
1277 +#include <asm/uaccess.h>
1278 +
1279 +#include <typedefs.h>
1280 +#include <bcmendian.h>
1281 +#include <bcmnvram.h>
1282 +#include <bcmutils.h>
1283 +#include <sbconfig.h>
1284 +#include <sbchipc.h>
1285 +#include <sbutils.h>
1286 +#include <sbmips.h>
1287 +#include <sflash.h>
1288 +
1289 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1290 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1291 +
1292 +/* Global SB handle */
1293 +extern void *sbh;
1294 +extern spinlock_t bcm947xx_sbh_lock;
1295 +static int cfe_env;
1296 +
1297 +extern char *cfe_env_get(char *nv_buf, const char *name);
1298 +
1299 +
1300 +/* Convenience */
1301 +#define sbh_lock bcm947xx_sbh_lock
1302 +#define KB * 1024
1303 +#define MB * 1024 * 1024
1304 +
1305 +/* Probe for NVRAM header */
1306 +static void __init
1307 +early_nvram_init(void)
1308 +{
1309 + struct nvram_header *header;
1310 + chipcregs_t *cc;
1311 + struct sflash *info = NULL;
1312 + int i;
1313 + uint32 base, off, lim;
1314 + u32 *src, *dst;
1315 +
1316 + cfe_env = 0;
1317 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1318 + base = KSEG1ADDR(SB_FLASH2);
1319 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1320 + case PFLASH:
1321 + lim = SB_FLASH2_SZ;
1322 + break;
1323 +
1324 + case SFLASH_ST:
1325 + case SFLASH_AT:
1326 + if ((info = sflash_init(cc)) == NULL)
1327 + return;
1328 + lim = info->size;
1329 + break;
1330 +
1331 + case FLASH_NONE:
1332 + default:
1333 + return;
1334 + }
1335 + } else {
1336 + /* extif assumed, Stop at 4 MB */
1337 + base = KSEG1ADDR(SB_FLASH1);
1338 + lim = SB_FLASH1_SZ;
1339 + }
1340 +
1341 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1342 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1343 + dst = (u32 *) nvram_buf;
1344 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1345 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1346 +
1347 + for (i = 0; i < 0x1ff0; i++) {
1348 + if (*src == 0xFFFFFFFF)
1349 + break;
1350 + *dst++ = *src++;
1351 + }
1352 + cfe_env = 1;
1353 + return;
1354 + }
1355 +
1356 + off = FLASH_MIN;
1357 + while (off <= lim) {
1358 + /* Windowed flash access */
1359 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1360 + if (header->magic == NVRAM_MAGIC)
1361 + goto found;
1362 + off <<= 1;
1363 + }
1364 +
1365 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1366 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1367 + if (header->magic == NVRAM_MAGIC)
1368 + goto found;
1369 +
1370 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1371 + if (header->magic == NVRAM_MAGIC)
1372 + goto found;
1373 +
1374 + return;
1375 +
1376 +found:
1377 + src = (u32 *) header;
1378 + dst = (u32 *) nvram_buf;
1379 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1380 + *dst++ = *src++;
1381 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1382 + *dst++ = ltoh32(*src++);
1383 +}
1384 +
1385 +/* Early (before mm or mtd) read-only access to NVRAM */
1386 +char * __init early_nvram_get(const char *name)
1387 +{
1388 + char *var, *value, *end, *eq;
1389 +
1390 + if (!name)
1391 + return NULL;
1392 +
1393 + /* Too early? */
1394 + if (sbh == NULL)
1395 + return NULL;
1396 +
1397 + if (!nvram_buf[0])
1398 + early_nvram_init();
1399 +
1400 + if (cfe_env)
1401 + return cfe_env_get(nvram_buf, name);
1402 +
1403 + /* Look for name=value and return value */
1404 + var = &nvram_buf[sizeof(struct nvram_header)];
1405 + end = nvram_buf + sizeof(nvram_buf) - 2;
1406 + end[0] = end[1] = '\0';
1407 + for (; *var; var = value + strlen(value) + 1) {
1408 + if (!(eq = strchr(var, '=')))
1409 + break;
1410 + value = eq + 1;
1411 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1412 + return value;
1413 + }
1414 +
1415 + return NULL;
1416 +}
1417 +
1418 +char *nvram_get(const char *name)
1419 +{
1420 + char *var, *value, *end, *eq;
1421 +
1422 + if (!name)
1423 + return NULL;
1424 +
1425 + if (!nvram_buf[0])
1426 + return NULL;
1427 +
1428 + /* Look for name=value and return value */
1429 + var = &nvram_buf[sizeof(struct nvram_header)];
1430 + end = nvram_buf + sizeof(nvram_buf) - 2;
1431 + end[0] = end[1] = '\0';
1432 + for (; *var; var = value + strlen(value) + 1) {
1433 + if (!(eq = strchr(var, '=')))
1434 + break;
1435 + value = eq + 1;
1436 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1437 + return value;
1438 + }
1439 +
1440 + return NULL;
1441 +}
1442 +
1443 +EXPORT_SYMBOL(nvram_get);
1444 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1445 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1446 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2006-01-12 00:27:27.399172250 +0100
1447 @@ -0,0 +1,1055 @@
1448 +/*
1449 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1450 + *
1451 + * Copyright 2005, Broadcom Corporation
1452 + * All Rights Reserved.
1453 + *
1454 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1455 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1456 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1457 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1458 + *
1459 + * $Id$
1460 + */
1461 +
1462 +#include <typedefs.h>
1463 +#include <osl.h>
1464 +#include <sbutils.h>
1465 +#include <bcmdevs.h>
1466 +#include <bcmnvram.h>
1467 +#include <bcmutils.h>
1468 +#include <hndmips.h>
1469 +#include <sbconfig.h>
1470 +#include <sbextif.h>
1471 +#include <sbchipc.h>
1472 +#include <sbmemc.h>
1473 +#include <mipsinc.h>
1474 +#include <sbutils.h>
1475 +
1476 +/*
1477 + * Returns TRUE if an external UART exists at the given base
1478 + * register.
1479 + */
1480 +static bool
1481 +BCMINITFN(serial_exists)(uint8 *regs)
1482 +{
1483 + uint8 save_mcr, status1;
1484 +
1485 + save_mcr = R_REG(&regs[UART_MCR]);
1486 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1487 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1488 + W_REG(&regs[UART_MCR], save_mcr);
1489 +
1490 + return (status1 == 0x90);
1491 +}
1492 +
1493 +/*
1494 + * Initializes UART access. The callback function will be called once
1495 + * per found UART.
1496 + */
1497 +void
1498 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1499 +{
1500 + void *regs;
1501 + ulong base;
1502 + uint irq;
1503 + int i, n;
1504 +
1505 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1506 + extifregs_t *eir = (extifregs_t *) regs;
1507 + sbconfig_t *sb;
1508 +
1509 + /* Determine external UART register base */
1510 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1511 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1512 +
1513 + /* Determine IRQ */
1514 + irq = sb_irq(sbh);
1515 +
1516 + /* Disable GPIO interrupt initially */
1517 + W_REG(&eir->gpiointpolarity, 0);
1518 + W_REG(&eir->gpiointmask, 0);
1519 +
1520 + /* Search for external UARTs */
1521 + n = 2;
1522 + for (i = 0; i < 2; i++) {
1523 + regs = (void *) REG_MAP(base + (i * 8), 8);
1524 + if (BCMINIT(serial_exists)(regs)) {
1525 + /* Set GPIO 1 to be the external UART IRQ */
1526 + W_REG(&eir->gpiointmask, 2);
1527 + if (add)
1528 + add(regs, irq, 13500000, 0);
1529 + }
1530 + }
1531 +
1532 + /* Add internal UART if enabled */
1533 + if (R_REG(&eir->corecontrol) & CC_UE)
1534 + if (add)
1535 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1536 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1537 + chipcregs_t *cc = (chipcregs_t *) regs;
1538 + uint32 rev, cap, pll, baud_base, div;
1539 +
1540 + /* Determine core revision and capabilities */
1541 + rev = sb_corerev(sbh);
1542 + cap = R_REG(&cc->capabilities);
1543 + pll = cap & CAP_PLL_MASK;
1544 +
1545 + /* Determine IRQ */
1546 + irq = sb_irq(sbh);
1547 +
1548 + if (pll == PLL_TYPE1) {
1549 + /* PLL clock */
1550 + baud_base = sb_clock_rate(pll,
1551 + R_REG(&cc->clockcontrol_n),
1552 + R_REG(&cc->clockcontrol_m2));
1553 + div = 1;
1554 + } else {
1555 + if (rev >= 11) {
1556 + /* Fixed ALP clock */
1557 + baud_base = 20000000;
1558 + div = 1;
1559 + /* Set the override bit so we don't divide it */
1560 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1561 + } else if (rev >= 3) {
1562 + /* Internal backplane clock */
1563 + baud_base = sb_clock(sbh);
1564 + div = 2; /* Minimum divisor */
1565 + W_REG(&cc->clkdiv,
1566 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1567 + } else {
1568 + /* Fixed internal backplane clock */
1569 + baud_base = 88000000;
1570 + div = 48;
1571 + }
1572 +
1573 + /* Clock source depends on strapping if UartClkOverride is unset */
1574 + if ((rev > 0) &&
1575 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1576 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1577 + /* Internal divided backplane clock */
1578 + baud_base /= div;
1579 + } else {
1580 + /* Assume external clock of 1.8432 MHz */
1581 + baud_base = 1843200;
1582 + }
1583 + }
1584 + }
1585 +
1586 + /* Add internal UARTs */
1587 + n = cap & CAP_UARTS_MASK;
1588 + for (i = 0; i < n; i++) {
1589 + /* Register offset changed after revision 0 */
1590 + if (rev)
1591 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1592 + else
1593 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1594 +
1595 + if (add)
1596 + add(regs, irq, baud_base, 0);
1597 + }
1598 + }
1599 +}
1600 +
1601 +/*
1602 + * Initialize jtag master and return handle for
1603 + * jtag_rwreg. Returns NULL on failure.
1604 + */
1605 +void *
1606 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1607 +{
1608 + void *regs;
1609 +
1610 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1611 + chipcregs_t *cc = (chipcregs_t *) regs;
1612 + uint32 tmp;
1613 +
1614 + /*
1615 + * Determine jtagm availability from
1616 + * core revision and capabilities.
1617 + */
1618 + tmp = sb_corerev(sbh);
1619 + /*
1620 + * Corerev 10 has jtagm, but the only chip
1621 + * with it does not have a mips, and
1622 + * the layout of the jtagcmd register is
1623 + * different. We'll only accept >= 11.
1624 + */
1625 + if (tmp < 11)
1626 + return (NULL);
1627 +
1628 + tmp = R_REG(&cc->capabilities);
1629 + if ((tmp & CAP_JTAGP) == 0)
1630 + return (NULL);
1631 +
1632 + /* Set clock divider if requested */
1633 + if (clkd != 0) {
1634 + tmp = R_REG(&cc->clkdiv);
1635 + tmp = (tmp & ~CLKD_JTAG) |
1636 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1637 + W_REG(&cc->clkdiv, tmp);
1638 + }
1639 +
1640 + /* Enable jtagm */
1641 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1642 + W_REG(&cc->jtagctrl, tmp);
1643 + }
1644 +
1645 + return (regs);
1646 +}
1647 +
1648 +void
1649 +sb_jtagm_disable(void *h)
1650 +{
1651 + chipcregs_t *cc = (chipcregs_t *)h;
1652 +
1653 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1654 +}
1655 +
1656 +/*
1657 + * Read/write a jtag register. Assumes a target with
1658 + * 8 bit IR and 32 bit DR.
1659 + */
1660 +#define IRWIDTH 8
1661 +#define DRWIDTH 32
1662 +uint32
1663 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1664 +{
1665 + chipcregs_t *cc = (chipcregs_t *) h;
1666 + uint32 tmp;
1667 +
1668 + W_REG(&cc->jtagir, ir);
1669 + W_REG(&cc->jtagdr, dr);
1670 + tmp = JCMD_START | JCMD_ACC_IRDR |
1671 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1672 + (DRWIDTH - 1);
1673 + W_REG(&cc->jtagcmd, tmp);
1674 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1675 + /* OSL_DELAY(1); */
1676 + }
1677 +
1678 + tmp = R_REG(&cc->jtagdr);
1679 + return (tmp);
1680 +}
1681 +
1682 +/* Returns the SB interrupt flag of the current core. */
1683 +uint32
1684 +sb_flag(sb_t *sbh)
1685 +{
1686 + void *regs;
1687 + sbconfig_t *sb;
1688 +
1689 + regs = sb_coreregs(sbh);
1690 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1691 +
1692 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1693 +}
1694 +
1695 +static const uint32 sbips_int_mask[] = {
1696 + 0,
1697 + SBIPS_INT1_MASK,
1698 + SBIPS_INT2_MASK,
1699 + SBIPS_INT3_MASK,
1700 + SBIPS_INT4_MASK
1701 +};
1702 +
1703 +static const uint32 sbips_int_shift[] = {
1704 + 0,
1705 + 0,
1706 + SBIPS_INT2_SHIFT,
1707 + SBIPS_INT3_SHIFT,
1708 + SBIPS_INT4_SHIFT
1709 +};
1710 +
1711 +/*
1712 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1713 + * 0 is returned.
1714 + */
1715 +uint
1716 +sb_irq(sb_t *sbh)
1717 +{
1718 + uint idx;
1719 + void *regs;
1720 + sbconfig_t *sb;
1721 + uint32 flag, sbipsflag;
1722 + uint irq = 0;
1723 +
1724 + flag = sb_flag(sbh);
1725 +
1726 + idx = sb_coreidx(sbh);
1727 +
1728 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1729 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1730 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1731 +
1732 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1733 + sbipsflag = R_REG(&sb->sbipsflag);
1734 + for (irq = 1; irq <= 4; irq++) {
1735 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1736 + break;
1737 + }
1738 + if (irq == 5)
1739 + irq = 0;
1740 + }
1741 +
1742 + sb_setcoreidx(sbh, idx);
1743 +
1744 + return irq;
1745 +}
1746 +
1747 +/* Clears the specified MIPS IRQ. */
1748 +static void
1749 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1750 +{
1751 + void *regs;
1752 + sbconfig_t *sb;
1753 +
1754 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1755 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1756 + ASSERT(regs);
1757 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1758 +
1759 + if (irq == 0)
1760 + W_REG(&sb->sbintvec, 0);
1761 + else
1762 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1763 +}
1764 +
1765 +/*
1766 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1767 + * IRQ 0 may be assigned more than once.
1768 + */
1769 +static void
1770 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1771 +{
1772 + void *regs;
1773 + sbconfig_t *sb;
1774 + uint32 flag;
1775 +
1776 + regs = sb_setcore(sbh, coreid, coreunit);
1777 + ASSERT(regs);
1778 + flag = sb_flag(sbh);
1779 +
1780 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1781 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1782 + ASSERT(regs);
1783 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1784 +
1785 + if (irq == 0)
1786 + OR_REG(&sb->sbintvec, 1 << flag);
1787 + else {
1788 + flag <<= sbips_int_shift[irq];
1789 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1790 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1791 + W_REG(&sb->sbipsflag, flag);
1792 + }
1793 +}
1794 +
1795 +/*
1796 + * Initializes clocks and interrupts. SB and NVRAM access must be
1797 + * initialized prior to calling.
1798 + */
1799 +void
1800 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1801 +{
1802 + ulong hz, ns, tmp;
1803 + extifregs_t *eir;
1804 + chipcregs_t *cc;
1805 + char *value;
1806 + uint irq;
1807 +
1808 + /* Figure out current SB clock speed */
1809 + if ((hz = sb_clock(sbh)) == 0)
1810 + hz = 100000000;
1811 + ns = 1000000000 / hz;
1812 +
1813 + /* Setup external interface timing */
1814 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1815 + /* Initialize extif so we can get to the LEDs and external UART */
1816 + W_REG(&eir->prog_config, CF_EN);
1817 +
1818 + /* Set timing for the flash */
1819 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1820 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1821 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1822 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1823 +
1824 + /* Set programmable interface timing for external uart */
1825 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1826 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1827 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1828 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1829 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1830 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1831 + /* set register for external IO to control LED. */
1832 + W_REG(&cc->prog_config, 0x11);
1833 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1834 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1835 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
1836 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1837 +
1838 + /* Set timing for the flash */
1839 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1840 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1841 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1842 +
1843 + // Added by Chen-I for 5365
1844 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1845 + {
1846 + W_REG(&cc->flash_waitcount, tmp);
1847 + W_REG(&cc->pcmcia_memwait, tmp);
1848 + }
1849 + else
1850 + {
1851 + if (sb_corerev(sbh) < 9)
1852 + W_REG(&cc->flash_waitcount, tmp);
1853 +
1854 + if ((sb_corerev(sbh) < 9) ||
1855 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1856 + W_REG(&cc->pcmcia_memwait, tmp);
1857 + }
1858 + }
1859 + // Added by Chen-I & Yen for enabling 5350 EXTIF
1860 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
1861 + {
1862 + /* Set programmable interface timing for external uart */
1863 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1864 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1865 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1866 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1867 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1868 + }
1869 + }
1870 +
1871 + /* Chip specific initialization */
1872 + switch (BCMINIT(sb_chip)(sbh)) {
1873 + case BCM4710_DEVICE_ID:
1874 + /* Clear interrupt map */
1875 + for (irq = 0; irq <= 4; irq++)
1876 + BCMINIT(sb_clearirq)(sbh, irq);
1877 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1878 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1879 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1880 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1881 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1882 + ASSERT(eir);
1883 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1884 + if (value && !strcmp(value, "31")) {
1885 + /* Enable internal UART */
1886 + W_REG(&eir->corecontrol, CC_UE);
1887 + /* Give USB its own interrupt */
1888 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1889 + } else {
1890 + /* Disable internal UART */
1891 + W_REG(&eir->corecontrol, 0);
1892 + /* Give Ethernet its own interrupt */
1893 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1894 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1895 + }
1896 + break;
1897 + case BCM5350_DEVICE_ID:
1898 + /* Clear interrupt map */
1899 + for (irq = 0; irq <= 4; irq++)
1900 + BCMINIT(sb_clearirq)(sbh, irq);
1901 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1902 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1903 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1904 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1905 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1906 + break;
1907 + }
1908 +}
1909 +
1910 +uint32
1911 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1912 +{
1913 + extifregs_t *eir;
1914 + chipcregs_t *cc;
1915 + uint32 n, m;
1916 + uint idx;
1917 + uint32 pll_type, rate = 0;
1918 +
1919 + /* get index of the current core */
1920 + idx = sb_coreidx(sbh);
1921 + pll_type = PLL_TYPE1;
1922 +
1923 + /* switch to extif or chipc core */
1924 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1925 + n = R_REG(&eir->clockcontrol_n);
1926 + m = R_REG(&eir->clockcontrol_sb);
1927 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1928 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1929 + n = R_REG(&cc->clockcontrol_n);
1930 + if ((pll_type == PLL_TYPE2) ||
1931 + (pll_type == PLL_TYPE4) ||
1932 + (pll_type == PLL_TYPE6) ||
1933 + (pll_type == PLL_TYPE7))
1934 + m = R_REG(&cc->clockcontrol_mips);
1935 + else if (pll_type == PLL_TYPE5) {
1936 + rate = 200000000;
1937 + goto out;
1938 + }
1939 + else if (pll_type == PLL_TYPE3) {
1940 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1941 + rate = 200000000;
1942 + goto out;
1943 + } else
1944 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1945 + } else
1946 + m = R_REG(&cc->clockcontrol_sb);
1947 + } else
1948 + goto out;
1949 +
1950 + // Added by Chen-I for 5365
1951 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1952 + rate = 100000000;
1953 + else
1954 + /* calculate rate */
1955 + rate = sb_clock_rate(pll_type, n, m);
1956 +
1957 + if (pll_type == PLL_TYPE6)
1958 + rate = SB2MIPS_T6(rate);
1959 +
1960 +out:
1961 + /* switch back to previous core */
1962 + sb_setcoreidx(sbh, idx);
1963 +
1964 + return rate;
1965 +}
1966 +
1967 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1968 +
1969 +static void
1970 +BCMINITFN(handler)(void)
1971 +{
1972 + /* Step 11 */
1973 + __asm__ (
1974 + ".set\tmips32\n\t"
1975 + "ssnop\n\t"
1976 + "ssnop\n\t"
1977 + /* Disable interrupts */
1978 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1979 + "mfc0 $15, $12\n\t"
1980 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1981 + "li $14, -31746\n\t"
1982 + "and $15, $15, $14\n\t"
1983 + "mtc0 $15, $12\n\t"
1984 + "eret\n\t"
1985 + "nop\n\t"
1986 + "nop\n\t"
1987 + ".set\tmips0"
1988 + );
1989 +}
1990 +
1991 +/* The following MUST come right after handler() */
1992 +static void
1993 +BCMINITFN(afterhandler)(void)
1994 +{
1995 +}
1996 +
1997 +/*
1998 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1999 + */
2000 +bool
2001 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
2002 +{
2003 + extifregs_t *eir = NULL;
2004 + chipcregs_t *cc = NULL;
2005 + mipsregs_t *mipsr = NULL;
2006 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
2007 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
2008 + uint32 pll_type, sync_mode;
2009 + uint ic_size, ic_lsize;
2010 + uint idx, i;
2011 + typedef struct {
2012 + uint32 mipsclock;
2013 + uint16 n;
2014 + uint32 sb;
2015 + uint32 pci33;
2016 + uint32 pci25;
2017 + } n3m_table_t;
2018 + static n3m_table_t BCMINITDATA(type1_table)[] = {
2019 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
2020 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
2021 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
2022 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
2023 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
2024 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
2025 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
2026 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
2027 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
2028 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
2029 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
2030 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
2031 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
2032 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
2033 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
2034 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
2035 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
2036 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
2037 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
2038 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
2039 + };
2040 + typedef struct {
2041 + uint32 mipsclock;
2042 + uint16 n;
2043 + uint32 m2; /* that is the clockcontrol_m2 */
2044 + } type3_table_t;
2045 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
2046 + { 150000000, 0x311, 0x4020005 },
2047 + { 200000000, 0x311, 0x4020003 },
2048 + };
2049 + typedef struct {
2050 + uint32 mipsclock;
2051 + uint32 sbclock;
2052 + uint16 n;
2053 + uint32 sb;
2054 + uint32 pci33;
2055 + uint32 m2;
2056 + uint32 m3;
2057 + uint32 ratio_cfg;
2058 + uint32 ratio_parm;
2059 + } n4m_table_t;
2060 +
2061 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2062 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2063 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2064 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2065 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2066 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2067 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2068 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2069 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2070 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2071 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2072 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2073 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2074 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2075 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2076 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2077 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2078 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2079 + };
2080 +
2081 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2082 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2083 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2084 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2085 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2086 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2087 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2088 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2089 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2090 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2091 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2092 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2093 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2094 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2095 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2096 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2097 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2098 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2099 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2100 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2101 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2102 + };
2103 +
2104 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2105 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2106 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2107 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2108 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2109 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2110 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2111 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2112 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2113 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2114 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2115 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2116 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2117 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2118 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2119 + };
2120 +
2121 + ulong start, end, dst;
2122 + bool ret = FALSE;
2123 +
2124 + /* get index of the current core */
2125 + idx = sb_coreidx(sbh);
2126 + clockcontrol_m2 = NULL;
2127 +
2128 + /* switch to extif or chipc core */
2129 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2130 + pll_type = PLL_TYPE1;
2131 + clockcontrol_n = &eir->clockcontrol_n;
2132 + clockcontrol_sb = &eir->clockcontrol_sb;
2133 + clockcontrol_pci = &eir->clockcontrol_pci;
2134 + clockcontrol_m2 = &cc->clockcontrol_m2;
2135 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2136 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2137 + if (pll_type == PLL_TYPE6) {
2138 + clockcontrol_n = NULL;
2139 + clockcontrol_sb = NULL;
2140 + clockcontrol_pci = NULL;
2141 + } else {
2142 + clockcontrol_n = &cc->clockcontrol_n;
2143 + clockcontrol_sb = &cc->clockcontrol_sb;
2144 + clockcontrol_pci = &cc->clockcontrol_pci;
2145 + clockcontrol_m2 = &cc->clockcontrol_m2;
2146 + }
2147 + } else
2148 + goto done;
2149 +
2150 + if (pll_type == PLL_TYPE6) {
2151 + /* Silence compilers */
2152 + orig_n = orig_sb = orig_pci = 0;
2153 + } else {
2154 + /* Store the current clock register values */
2155 + orig_n = R_REG(clockcontrol_n);
2156 + orig_sb = R_REG(clockcontrol_sb);
2157 + orig_pci = R_REG(clockcontrol_pci);
2158 + }
2159 +
2160 + if (pll_type == PLL_TYPE1) {
2161 + /* Keep the current PCI clock if not specified */
2162 + if (pciclock == 0) {
2163 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2164 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2165 + }
2166 +
2167 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2168 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2169 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2170 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2171 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2172 + break;
2173 + }
2174 + if (i == 0) {
2175 + ret = FALSE;
2176 + goto done;
2177 + } else {
2178 + ret = TRUE;
2179 + i--;
2180 + }
2181 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2182 +
2183 + /* No PLL change */
2184 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2185 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2186 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2187 + goto done;
2188 +
2189 + /* Set the PLL controls */
2190 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2191 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2192 + if (pciclock == 25000000)
2193 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2194 + else
2195 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2196 +
2197 + /* Reset */
2198 + sb_watchdog(sbh, 1);
2199 +
2200 + while (1);
2201 + } else if ((pll_type == PLL_TYPE3) &&
2202 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2203 + /* 5350 */
2204 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2205 +
2206 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2207 + if (type3_table[i].mipsclock > mipsclock)
2208 + break;
2209 + }
2210 + if (i == 0) {
2211 + ret = FALSE;
2212 + goto done;
2213 + } else {
2214 + ret = TRUE;
2215 + i--;
2216 + }
2217 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2218 +
2219 + /* No PLL change */
2220 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2221 + if ((orig_n == type3_table[i].n) &&
2222 + (orig_m2 == type3_table[i].m2)) {
2223 + goto done;
2224 + }
2225 +
2226 + /* Set the PLL controls */
2227 + W_REG(clockcontrol_n, type3_table[i].n);
2228 + W_REG(clockcontrol_m2, type3_table[i].m2);
2229 +
2230 + /* Reset */
2231 + sb_watchdog(sbh, 1);
2232 + while (1);
2233 + } else if ((pll_type == PLL_TYPE2) ||
2234 + (pll_type == PLL_TYPE4) ||
2235 + (pll_type == PLL_TYPE6) ||
2236 + (pll_type == PLL_TYPE7)) {
2237 + n4m_table_t *table = NULL, *te;
2238 + uint tabsz = 0;
2239 +
2240 + ASSERT(cc);
2241 +
2242 + orig_mips = R_REG(&cc->clockcontrol_mips);
2243 +
2244 + if (pll_type == PLL_TYPE6) {
2245 + uint32 new_mips = 0;
2246 +
2247 + ret = TRUE;
2248 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2249 + new_mips = CC_T6_MMASK;
2250 +
2251 + if (orig_mips == new_mips)
2252 + goto done;
2253 +
2254 + W_REG(&cc->clockcontrol_mips, new_mips);
2255 + goto end_fill;
2256 + }
2257 +
2258 + if (pll_type == PLL_TYPE2) {
2259 + table = BCMINIT(type2_table);
2260 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2261 + } else if (pll_type == PLL_TYPE4) {
2262 + table = BCMINIT(type4_table);
2263 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2264 + } else if (pll_type == PLL_TYPE7) {
2265 + table = BCMINIT(type7_table);
2266 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2267 + } else
2268 + ASSERT("No table for plltype" == NULL);
2269 +
2270 + /* Store the current clock register values */
2271 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2272 + orig_ratio_parm = 0;
2273 + orig_ratio_cfg = 0;
2274 +
2275 + /* Look up current ratio */
2276 + for (i = 0; i < tabsz; i++) {
2277 + if ((orig_n == table[i].n) &&
2278 + (orig_sb == table[i].sb) &&
2279 + (orig_pci == table[i].pci33) &&
2280 + (orig_m2 == table[i].m2) &&
2281 + (orig_mips == table[i].m3)) {
2282 + orig_ratio_parm = table[i].ratio_parm;
2283 + orig_ratio_cfg = table[i].ratio_cfg;
2284 + break;
2285 + }
2286 + }
2287 +
2288 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2289 + for (i = 0; i < tabsz; i++) {
2290 + ASSERT(table[i].mipsclock ==
2291 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2292 + if ((mipsclock <= table[i].mipsclock) &&
2293 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2294 + break;
2295 + }
2296 + if (i == tabsz) {
2297 + ret = FALSE;
2298 + goto done;
2299 + } else {
2300 + te = &table[i];
2301 + ret = TRUE;
2302 + }
2303 +
2304 + /* No PLL change */
2305 + if ((orig_n == te->n) &&
2306 + (orig_sb == te->sb) &&
2307 + (orig_pci == te->pci33) &&
2308 + (orig_m2 == te->m2) &&
2309 + (orig_mips == te->m3))
2310 + goto done;
2311 +
2312 + /* Set the PLL controls */
2313 + W_REG(clockcontrol_n, te->n);
2314 + W_REG(clockcontrol_sb, te->sb);
2315 + W_REG(clockcontrol_pci, te->pci33);
2316 + W_REG(&cc->clockcontrol_m2, te->m2);
2317 + W_REG(&cc->clockcontrol_mips, te->m3);
2318 +
2319 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2320 + if ((pll_type == PLL_TYPE7) &&
2321 + (te->sb != te->m2) &&
2322 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2323 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2324 +
2325 + /* No ratio change */
2326 + if (orig_ratio_parm == te->ratio_parm)
2327 + goto end_fill;
2328 +
2329 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2330 +
2331 + /* Preload the code into the cache */
2332 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2333 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2334 + while (start < end) {
2335 + cache_op(start, Fill_I);
2336 + start += ic_lsize;
2337 + }
2338 +
2339 + /* Copy the handler */
2340 + start = (ulong) &BCMINIT(handler);
2341 + end = (ulong) &BCMINIT(afterhandler);
2342 + dst = KSEG1ADDR(0x180);
2343 + for (i = 0; i < (end - start); i += 4)
2344 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2345 +
2346 + /* Preload handler into the cache one line at a time */
2347 + for (i = 0; i < (end - start); i += 4)
2348 + cache_op(dst + i, Fill_I);
2349 +
2350 + /* Clear BEV bit */
2351 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2352 +
2353 + /* Enable interrupts */
2354 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2355 +
2356 + /* Enable MIPS timer interrupt */
2357 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2358 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2359 + ASSERT(mipsr);
2360 + W_REG(&mipsr->intmask, 1);
2361 +
2362 + start_fill:
2363 + /* step 1, set clock ratios */
2364 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2365 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2366 +
2367 + /* step 2: program timer intr */
2368 + W_REG(&mipsr->timer, 100);
2369 + (void) R_REG(&mipsr->timer);
2370 +
2371 + /* step 3, switch to async */
2372 + sync_mode = MFC0(C0_BROADCOM, 4);
2373 + MTC0(C0_BROADCOM, 4, 1 << 22);
2374 +
2375 + /* step 4, set cfg active */
2376 + MTC0(C0_BROADCOM, 2, 0x9);
2377 +
2378 +
2379 + /* steps 5 & 6 */
2380 + __asm__ __volatile__ (
2381 + ".set\tmips3\n\t"
2382 + "wait\n\t"
2383 + ".set\tmips0"
2384 + );
2385 +
2386 + /* step 7, clear cfg_active */
2387 + MTC0(C0_BROADCOM, 2, 0);
2388 +
2389 + /* Additional Step: set back to orig sync mode */
2390 + MTC0(C0_BROADCOM, 4, sync_mode);
2391 +
2392 + /* step 8, fake soft reset */
2393 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2394 +
2395 + end_fill:
2396 + /* step 9 set watchdog timer */
2397 + sb_watchdog(sbh, 20);
2398 + (void) R_REG(&cc->chipid);
2399 +
2400 + /* step 11 */
2401 + __asm__ __volatile__ (
2402 + ".set\tmips3\n\t"
2403 + "sync\n\t"
2404 + "wait\n\t"
2405 + ".set\tmips0"
2406 + );
2407 + while (1);
2408 + }
2409 +
2410 +done:
2411 + /* switch back to previous core */
2412 + sb_setcoreidx(sbh, idx);
2413 +
2414 + return ret;
2415 +}
2416 +
2417 +/*
2418 + * This also must be run from the cache on 47xx
2419 + * so there are no mips core BIU ops in progress
2420 + * when the PFC is enabled.
2421 + */
2422 +
2423 +static void
2424 +BCMINITFN(_enable_pfc)(uint32 mode)
2425 +{
2426 + /* write range */
2427 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2428 +
2429 + /* enable */
2430 + *(volatile uint32 *)PFC_CR0 = mode;
2431 +}
2432 +
2433 +void
2434 +BCMINITFN(enable_pfc)(uint32 mode)
2435 +{
2436 + ulong start, end;
2437 + int i;
2438 +
2439 + /* If auto then choose the correct mode for this
2440 + platform, currently we only ever select one mode */
2441 + if (mode == PFC_AUTO)
2442 + mode = PFC_INST;
2443 +
2444 + /* enable prefetch cache if available */
2445 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2446 + start = (ulong) &BCMINIT(_enable_pfc);
2447 + end = (ulong) &BCMINIT(enable_pfc);
2448 +
2449 + /* Preload handler into the cache one line at a time */
2450 + for (i = 0; i < (end - start); i += 4)
2451 + cache_op(start + i, Fill_I);
2452 +
2453 + BCMINIT(_enable_pfc)(mode);
2454 + }
2455 +}
2456 +
2457 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2458 +uint32
2459 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2460 +{
2461 + sbmemcregs_t *memc;
2462 + uint32 ret = 0;
2463 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2464 + uint idx, rev;
2465 +
2466 + idx = sb_coreidx(sbh);
2467 +
2468 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2469 + if (memc == 0)
2470 + goto out;
2471 +
2472 + rev = sb_corerev(sbh);
2473 +
2474 + config = R_REG(&memc->config);
2475 + wr = R_REG(&memc->wrncdlcor);
2476 + rd = R_REG(&memc->rdncdlcor);
2477 + misc = R_REG(&memc->miscdlyctl);
2478 + dqsg = R_REG(&memc->dqsgatencdl);
2479 +
2480 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2481 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2482 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2483 +
2484 + if (config & MEMC_CONFIG_DDR) {
2485 + ret = (wr << 16) | (rd << 8) | dqsg;
2486 + } else {
2487 + if (rev > 0)
2488 + cd = rd;
2489 + else
2490 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2491 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2492 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2493 + ret = (sm << 16) | (sd << 8) | cd;
2494 + }
2495 +
2496 +out:
2497 + /* switch back to previous core */
2498 + sb_setcoreidx(sbh, idx);
2499 +
2500 + return ret;
2501 +}
2502 +
2503 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2504 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2505 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2006-01-12 00:52:25.864820500 +0100
2506 @@ -0,0 +1,534 @@
2507 +/*
2508 + * Low-Level PCI and SB support for BCM47xx
2509 + *
2510 + * Copyright 2005, Broadcom Corporation
2511 + * All Rights Reserved.
2512 + *
2513 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2514 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2515 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2516 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2517 + *
2518 + * $Id$
2519 + */
2520 +
2521 +#include <typedefs.h>
2522 +#include <pcicfg.h>
2523 +#include <bcmdevs.h>
2524 +#include <sbconfig.h>
2525 +#include <osl.h>
2526 +#include <sbutils.h>
2527 +#include <sbpci.h>
2528 +#include <bcmendian.h>
2529 +#include <bcmutils.h>
2530 +#include <bcmnvram.h>
2531 +#include <hndmips.h>
2532 +
2533 +/* Can free sbpci_init() memory after boot */
2534 +#ifndef linux
2535 +#define __init
2536 +#endif
2537 +
2538 +/* Emulated configuration space */
2539 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2540 +
2541 +/* Banned cores */
2542 +static uint16 pci_ban[32] = { 0 };
2543 +static uint pci_banned = 0;
2544 +
2545 +/* CardBus mode */
2546 +static bool cardbus = FALSE;
2547 +
2548 +/* Disable PCI host core */
2549 +static bool pci_disabled = FALSE;
2550 +
2551 +/*
2552 + * Functions for accessing external PCI configuration space
2553 + */
2554 +
2555 +/* Assume one-hot slot wiring */
2556 +#define PCI_SLOT_MAX 16
2557 +
2558 +static uint32
2559 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2560 +{
2561 + uint coreidx;
2562 + sbpciregs_t *regs;
2563 + uint32 addr = 0;
2564 +
2565 + /* CardBusMode supports only one device */
2566 + if (cardbus && dev > 1)
2567 + return 0;
2568 +
2569 + coreidx = sb_coreidx(sbh);
2570 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2571 +
2572 + /* Type 0 transaction */
2573 + if (bus == 1) {
2574 + /* Skip unwired slots */
2575 + if (dev < PCI_SLOT_MAX) {
2576 + /* Slide the PCI window to the appropriate slot */
2577 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2578 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2579 + (func << 8) | (off & ~3);
2580 + }
2581 + }
2582 +
2583 + /* Type 1 transaction */
2584 + else {
2585 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2586 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2587 + }
2588 +
2589 + sb_setcoreidx(sbh, coreidx);
2590 +
2591 + return addr;
2592 +}
2593 +
2594 +static int
2595 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2596 +{
2597 + uint32 addr, *reg = NULL, val;
2598 + int ret = 0;
2599 +
2600 + if (pci_disabled ||
2601 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2602 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2603 + BUSPROBE(val, reg))
2604 + val = 0xffffffff;
2605 +
2606 + val >>= 8 * (off & 3);
2607 + if (len == 4)
2608 + *((uint32 *) buf) = val;
2609 + else if (len == 2)
2610 + *((uint16 *) buf) = (uint16) val;
2611 + else if (len == 1)
2612 + *((uint8 *) buf) = (uint8) val;
2613 + else
2614 + ret = -1;
2615 +
2616 + if (reg)
2617 + REG_UNMAP(reg);
2618 +
2619 + return ret;
2620 +}
2621 +
2622 +static int
2623 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2624 +{
2625 + uint32 addr, *reg = NULL, val;
2626 + int ret = 0;
2627 +
2628 + if (pci_disabled ||
2629 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2630 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2631 + BUSPROBE(val, reg))
2632 + goto done;
2633 +
2634 + if (len == 4)
2635 + val = *((uint32 *) buf);
2636 + else if (len == 2) {
2637 + val &= ~(0xffff << (8 * (off & 3)));
2638 + val |= *((uint16 *) buf) << (8 * (off & 3));
2639 + } else if (len == 1) {
2640 + val &= ~(0xff << (8 * (off & 3)));
2641 + val |= *((uint8 *) buf) << (8 * (off & 3));
2642 + } else
2643 + ret = -1;
2644 +
2645 + W_REG(reg, val);
2646 +
2647 + done:
2648 + if (reg)
2649 + REG_UNMAP(reg);
2650 +
2651 + return ret;
2652 +}
2653 +
2654 +/*
2655 + * Functions for accessing translated SB configuration space
2656 + */
2657 +
2658 +static int
2659 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2660 +{
2661 + pci_config_regs *cfg;
2662 +
2663 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2664 + return -1;
2665 + cfg = &sb_config_regs[dev];
2666 +
2667 + ASSERT(ISALIGNED(off, len));
2668 + ASSERT(ISALIGNED((uintptr)buf, len));
2669 +
2670 + if (len == 4)
2671 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2672 + else if (len == 2)
2673 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2674 + else if (len == 1)
2675 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2676 + else
2677 + return -1;
2678 +
2679 + return 0;
2680 +}
2681 +
2682 +static int
2683 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2684 +{
2685 + uint coreidx, n;
2686 + void *regs;
2687 + sbconfig_t *sb;
2688 + pci_config_regs *cfg;
2689 +
2690 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2691 + return -1;
2692 + cfg = &sb_config_regs[dev];
2693 +
2694 + ASSERT(ISALIGNED(off, len));
2695 + ASSERT(ISALIGNED((uintptr)buf, len));
2696 +
2697 + /* Emulate BAR sizing */
2698 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2699 + len == 4 && *((uint32 *) buf) == ~0) {
2700 + coreidx = sb_coreidx(sbh);
2701 + if ((regs = sb_setcoreidx(sbh, dev))) {
2702 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2703 + /* Highest numbered address match register */
2704 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2705 + if (off == OFFSETOF(pci_config_regs, base[0]))
2706 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2707 +#if 0
2708 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2709 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2710 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2711 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2712 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2713 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2714 +#endif
2715 + }
2716 + sb_setcoreidx(sbh, coreidx);
2717 + return 0;
2718 + }
2719 +
2720 + if (len == 4)
2721 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2722 + else if (len == 2)
2723 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2724 + else if (len == 1)
2725 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2726 + else
2727 + return -1;
2728 +
2729 + return 0;
2730 +}
2731 +
2732 +int
2733 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2734 +{
2735 + if (bus == 0)
2736 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2737 + else
2738 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2739 +}
2740 +
2741 +int
2742 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2743 +{
2744 + if (bus == 0)
2745 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2746 + else
2747 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2748 +}
2749 +
2750 +void
2751 +sbpci_ban(uint16 core)
2752 +{
2753 + if (pci_banned < ARRAYSIZE(pci_ban))
2754 + pci_ban[pci_banned++] = core;
2755 +}
2756 +
2757 +static int
2758 +sbpci_init_pci(sb_t *sbh)
2759 +{
2760 + uint chip, chiprev, chippkg, host;
2761 + uint32 boardflags;
2762 + sbpciregs_t *pci;
2763 + sbconfig_t *sb;
2764 + uint32 val;
2765 +
2766 + chip = sb_chip(sbh);
2767 + chiprev = sb_chiprev(sbh);
2768 + chippkg = sb_chippkg(sbh);
2769 +
2770 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2771 + printf("PCI: no core\n");
2772 + pci_disabled = TRUE;
2773 + return -1;
2774 + }
2775 + sb_core_reset(sbh, 0);
2776 +
2777 + boardflags = (uint32) getintvar(NULL, "boardflags");
2778 +
2779 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2780 + pci_disabled = TRUE;
2781 +
2782 + /*
2783 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2784 + * PCI is bonded out, some boards may leave the pins
2785 + * floating.
2786 + */
2787 + if (((chip == BCM4712_DEVICE_ID) &&
2788 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2789 + (chippkg == BCM4712MID_PKG_ID))) ||
2790 + (chip == BCM5350_DEVICE_ID) ||
2791 + (boardflags & BFL_NOPCI))
2792 + pci_disabled = TRUE;
2793 +
2794 + /*
2795 + * If the PCI core should not be touched (disabled, not bonded
2796 + * out, or pins floating), do not even attempt to access core
2797 + * registers. Otherwise, try to determine if it is in host
2798 + * mode.
2799 + */
2800 + if (pci_disabled)
2801 + host = 0;
2802 + else
2803 + host = !BUSPROBE(val, &pci->control);
2804 +
2805 + if (!host) {
2806 + /* Disable PCI interrupts in client mode */
2807 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2808 + W_REG(&sb->sbintvec, 0);
2809 +
2810 + /* Disable the PCI bridge in client mode */
2811 + sbpci_ban(SB_PCI);
2812 + printf("PCI: Disabled\n");
2813 + } else {
2814 + /* Reset the external PCI bus and enable the clock */
2815 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2816 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2817 + OSL_DELAY(150); /* delay > 100 us */
2818 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2819 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2820 + OSL_DELAY(1); /* delay 1 us */
2821 +
2822 + /* Enable CardBusMode */
2823 + cardbus = nvram_match("cardbus", "1");
2824 + if (cardbus) {
2825 + printf("PCI: Enabling CardBus\n");
2826 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2827 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2828 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2829 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2830 + }
2831 +
2832 + /* 64 MB I/O access window */
2833 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2834 + /* 64 MB configuration access window */
2835 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2836 + /* 1 GB memory access window */
2837 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2838 +
2839 + /* Enable PCI bridge BAR0 prefetch and burst */
2840 + val = 6;
2841 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2842 +
2843 + /* Enable PCI interrupts */
2844 + W_REG(&pci->intmask, PCI_INTA);
2845 + }
2846 +
2847 + return 0;
2848 +}
2849 +
2850 +static int
2851 +sbpci_init_cores(sb_t *sbh)
2852 +{
2853 + uint chip, chiprev, chippkg, coreidx, i;
2854 + sbconfig_t *sb;
2855 + pci_config_regs *cfg;
2856 + void *regs;
2857 + char varname[8];
2858 + uint wlidx = 0;
2859 + uint16 vendor, core;
2860 + uint8 class, subclass, progif;
2861 + uint32 val;
2862 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2863 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2864 +
2865 + chip = sb_chip(sbh);
2866 + chiprev = sb_chiprev(sbh);
2867 + chippkg = sb_chippkg(sbh);
2868 + coreidx = sb_coreidx(sbh);
2869 +
2870 + /* Scan the SB bus */
2871 + bzero(sb_config_regs, sizeof(sb_config_regs));
2872 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2873 + cfg->vendor = 0xffff;
2874 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2875 + continue;
2876 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2877 +
2878 + /* Read ID register and parse vendor and core */
2879 + val = R_REG(&sb->sbidhigh);
2880 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2881 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2882 + progif = 0;
2883 +
2884 + /* Check if this core is banned */
2885 + for (i = 0; i < pci_banned; i++)
2886 + if (core == pci_ban[i])
2887 + break;
2888 + if (i < pci_banned)
2889 + continue;
2890 +
2891 + /* Known vendor translations */
2892 + switch (vendor) {
2893 + case SB_VEND_BCM:
2894 + vendor = VENDOR_BROADCOM;
2895 + break;
2896 + }
2897 +
2898 + /* Determine class based on known core codes */
2899 + switch (core) {
2900 + case SB_ILINE20:
2901 + class = PCI_CLASS_NET;
2902 + subclass = PCI_NET_ETHER;
2903 + core = BCM47XX_ILINE_ID;
2904 + break;
2905 + case SB_ILINE100:
2906 + class = PCI_CLASS_NET;
2907 + subclass = PCI_NET_ETHER;
2908 + core = BCM4610_ILINE_ID;
2909 + break;
2910 + case SB_ENET:
2911 + class = PCI_CLASS_NET;
2912 + subclass = PCI_NET_ETHER;
2913 + core = BCM47XX_ENET_ID;
2914 + break;
2915 + case SB_SDRAM:
2916 + case SB_MEMC:
2917 + class = PCI_CLASS_MEMORY;
2918 + subclass = PCI_MEMORY_RAM;
2919 + break;
2920 + case SB_PCI:
2921 +#if 0
2922 + class = PCI_CLASS_BRIDGE;
2923 + subclass = PCI_BRIDGE_PCI;
2924 + break;
2925 +#endif
2926 + case SB_MIPS:
2927 + case SB_MIPS33:
2928 + class = PCI_CLASS_CPU;
2929 + subclass = PCI_CPU_MIPS;
2930 + break;
2931 + case SB_CODEC:
2932 + class = PCI_CLASS_COMM;
2933 + subclass = PCI_COMM_MODEM;
2934 + core = BCM47XX_V90_ID;
2935 + break;
2936 + case SB_USB:
2937 + class = PCI_CLASS_SERIAL;
2938 + subclass = PCI_SERIAL_USB;
2939 + progif = 0x10; /* OHCI */
2940 + core = BCM47XX_USB_ID;
2941 + break;
2942 + case SB_USB11H:
2943 + class = PCI_CLASS_SERIAL;
2944 + subclass = PCI_SERIAL_USB;
2945 + progif = 0x10; /* OHCI */
2946 + core = BCM47XX_USBH_ID;
2947 + break;
2948 + case SB_USB11D:
2949 + class = PCI_CLASS_SERIAL;
2950 + subclass = PCI_SERIAL_USB;
2951 + core = BCM47XX_USBD_ID;
2952 + break;
2953 + case SB_IPSEC:
2954 + class = PCI_CLASS_CRYPT;
2955 + subclass = PCI_CRYPT_NETWORK;
2956 + core = BCM47XX_IPSEC_ID;
2957 + break;
2958 + case SB_ROBO:
2959 + class = PCI_CLASS_NET;
2960 + subclass = PCI_NET_OTHER;
2961 + core = BCM47XX_ROBO_ID;
2962 + break;
2963 + case SB_EXTIF:
2964 + case SB_CC:
2965 + class = PCI_CLASS_MEMORY;
2966 + subclass = PCI_MEMORY_FLASH;
2967 + break;
2968 + case SB_D11:
2969 + class = PCI_CLASS_NET;
2970 + subclass = PCI_NET_OTHER;
2971 + /* Let an nvram variable override this */
2972 + sprintf(varname, "wl%did", wlidx);
2973 + wlidx++;
2974 + if ((core = getintvar(NULL, varname)) == 0) {
2975 + if (chip == BCM4712_DEVICE_ID) {
2976 + if (chippkg == BCM4712SMALL_PKG_ID)
2977 + core = BCM4306_D11G_ID;
2978 + else
2979 + core = BCM4306_D11DUAL_ID;
2980 + } else {
2981 + /* 4310 */
2982 + core = BCM4310_D11B_ID;
2983 + }
2984 + }
2985 + break;
2986 +
2987 + default:
2988 + class = subclass = progif = 0xff;
2989 + break;
2990 + }
2991 +
2992 + /* Supported translations */
2993 + cfg->vendor = htol16(vendor);
2994 + cfg->device = htol16(core);
2995 + cfg->rev_id = chiprev;
2996 + cfg->prog_if = progif;
2997 + cfg->sub_class = subclass;
2998 + cfg->base_class = class;
2999 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
3000 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
3001 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
3002 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
3003 + cfg->base[4] = 0;
3004 + cfg->base[5] = 0;
3005 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
3006 + cfg->header_type = PCI_HEADER_BRIDGE;
3007 + else
3008 + cfg->header_type = PCI_HEADER_NORMAL;
3009 + /* Save core interrupt flag */
3010 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
3011 + /* Default to MIPS shared interrupt 0 */
3012 + cfg->int_line = 0;
3013 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
3014 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3015 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3016 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3017 + val = R_REG(&sb->sbipsflag);
3018 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
3019 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
3020 + break;
3021 + }
3022 + if (cfg->int_line > 4)
3023 + cfg->int_line = 0;
3024 + }
3025 + /* Emulated core */
3026 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
3027 + }
3028 +
3029 + sb_setcoreidx(sbh, coreidx);
3030 + return 0;
3031 +}
3032 +
3033 +int __init
3034 +sbpci_init(sb_t *sbh)
3035 +{
3036 + sbpci_init_pci(sbh);
3037 + sbpci_init_cores(sbh);
3038 + return 0;
3039 +}
3040 +
3041 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
3042 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
3043 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2006-01-12 00:20:30.725131750 +0100
3044 @@ -0,0 +1,2370 @@
3045 +/*
3046 + * Misc utility routines for accessing chip-specific features
3047 + * of the SiliconBackplane-based Broadcom chips.
3048 + *
3049 + * Copyright 2005, Broadcom Corporation
3050 + * All Rights Reserved.
3051 + *
3052 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3053 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3054 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3055 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3056 + * $Id$
3057 + */
3058 +
3059 +#include <typedefs.h>
3060 +#include <osl.h>
3061 +#include <sbutils.h>
3062 +#include <bcmutils.h>
3063 +#include <bcmdevs.h>
3064 +#include <sbconfig.h>
3065 +#include <sbchipc.h>
3066 +#include <sbpci.h>
3067 +#include <pcicfg.h>
3068 +#include <sbextif.h>
3069 +#include <bcmsrom.h>
3070 +
3071 +/* debug/trace */
3072 +#define SB_ERROR(args)
3073 +
3074 +
3075 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3076 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3077 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3078 +
3079 +/* misc sb info needed by some of the routines */
3080 +typedef struct sb_info {
3081 +
3082 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3083 +
3084 + void *osh; /* osl os handle */
3085 + void *sdh; /* bcmsdh handle */
3086 +
3087 + void *curmap; /* current regs va */
3088 + void *regs[SB_MAXCORES]; /* other regs va */
3089 +
3090 + uint curidx; /* current core index */
3091 + uint dev_coreid; /* the core provides driver functions */
3092 +
3093 + uint gpioidx; /* gpio control core index */
3094 + uint gpioid; /* gpio control coretype */
3095 +
3096 + uint numcores; /* # discovered cores */
3097 + uint coreid[SB_MAXCORES]; /* id of each core */
3098 +
3099 + void *intr_arg; /* interrupt callback function arg */
3100 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3101 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3102 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3103 +
3104 +} sb_info_t;
3105 +
3106 +/* local prototypes */
3107 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3108 + uint bustype, void *sdh, char **vars, int *varsz);
3109 +static void BCMINIT(sb_scan)(sb_info_t *si);
3110 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3111 +static uint _sb_coreidx(sb_info_t *si);
3112 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3113 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3114 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3115 +static int sb_pci_fixcfg(sb_info_t *si);
3116 +
3117 +/* delay needed between the mdio control/ mdiodata register data access */
3118 +#define PR28829_DELAY() OSL_DELAY(10)
3119 +
3120 +
3121 +/* global variable to indicate reservation/release of gpio's*/
3122 +static uint32 sb_gpioreservation = 0;
3123 +
3124 +#define SB_INFO(sbh) (sb_info_t*)sbh
3125 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3126 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3127 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3128 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3129 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3130 +#define BADIDX (SB_MAXCORES+1)
3131 +#define NOREV -1
3132 +
3133 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3134 +
3135 +/* sonicsrev */
3136 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3137 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3138 +
3139 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3140 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3141 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3142 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3143 +
3144 +/*
3145 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3146 + * after core switching to avoid invalid register accesss inside ISR.
3147 + */
3148 +#define INTR_OFF(si, intr_val) \
3149 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3150 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3151 +#define INTR_RESTORE(si, intr_val) \
3152 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3153 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3154 +
3155 +/* dynamic clock control defines */
3156 +#define LPOMINFREQ 25000 /* low power oscillator min */
3157 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3158 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3159 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3160 +#define PCIMINFREQ 25000000 /* 25 MHz */
3161 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3162 +
3163 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3164 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3165 +
3166 +#define MIN_DUMPBUFLEN 32 /* debug */
3167 +
3168 +/* GPIO Based LED powersave defines */
3169 +#define DEFAULT_GPIO_ONTIME 10
3170 +#define DEFAULT_GPIO_OFFTIME 90
3171 +
3172 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3173 +
3174 +static uint32
3175 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3176 +{
3177 + uint32 val = R_REG(sbr);
3178 +
3179 + return (val);
3180 +}
3181 +
3182 +static void
3183 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3184 +{
3185 + W_REG(sbr, v);
3186 +}
3187 +
3188 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3189 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3190 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3191 +
3192 +/* global kernel resource */
3193 +static sb_info_t ksi;
3194 +
3195 +/* generic kernel variant of sb_attach() */
3196 +sb_t *
3197 +BCMINITFN(sb_kattach)()
3198 +{
3199 + uint32 *regs;
3200 +
3201 + if (ksi.curmap == NULL) {
3202 + uint32 cid;
3203 +
3204 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3205 + cid = R_REG((uint32 *)regs);
3206 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3207 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3208 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3209 + uint32 *scc, val;
3210 +
3211 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3212 + val = R_REG(scc);
3213 + SB_ERROR((" initial scc = 0x%x\n", val));
3214 + val |= SCC_SS_XTAL;
3215 + W_REG(scc, val);
3216 + }
3217 +
3218 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3219 + SB_BUS, NULL, NULL, NULL) == NULL) {
3220 + return NULL;
3221 + }
3222 + }
3223 +
3224 + return (sb_t *)&ksi;
3225 +}
3226 +#endif
3227 +
3228 +static sb_info_t *
3229 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3230 + uint bustype, void *sdh, char **vars, int *varsz)
3231 +{
3232 + uint origidx;
3233 + chipcregs_t *cc;
3234 + sbconfig_t *sb;
3235 + uint32 w;
3236 +
3237 + ASSERT(GOODREGS(regs));
3238 +
3239 + bzero((uchar*)si, sizeof (sb_info_t));
3240 +
3241 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3242 +
3243 + si->osh = osh;
3244 + si->curmap = regs;
3245 + si->sdh = sdh;
3246 +
3247 + /* check to see if we are a sb core mimic'ing a pci core */
3248 + if (bustype == PCI_BUS) {
3249 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3250 + bustype = SB_BUS;
3251 + else
3252 + bustype = PCI_BUS;
3253 + }
3254 +
3255 + si->sb.bustype = bustype;
3256 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3257 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3258 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3259 + return NULL;
3260 + }
3261 +
3262 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3263 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3264 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3265 +
3266 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3267 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3268 + if (!GOODCOREADDR(w))
3269 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3270 + }
3271 +
3272 + /* initialize current core index value */
3273 + si->curidx = _sb_coreidx(si);
3274 +
3275 + if (si->curidx == BADIDX) {
3276 + SB_ERROR(("sb_doattach: bad core index\n"));
3277 + return NULL;
3278 + }
3279 +
3280 + /* get sonics backplane revision */
3281 + sb = REGS2SB(si->curmap);
3282 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3283 +
3284 + /* keep and reuse the initial register mapping */
3285 + origidx = si->curidx;
3286 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3287 + si->regs[origidx] = regs;
3288 +
3289 + /* is core-0 a chipcommon core? */
3290 + si->numcores = 1;
3291 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3292 + if (sb_coreid(&si->sb) != SB_CC)
3293 + cc = NULL;
3294 +
3295 + /* determine chip id and rev */
3296 + if (cc) {
3297 + /* chip common core found! */
3298 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3299 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3300 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3301 + } else {
3302 + /* no chip common core -- must convert device id to chip id */
3303 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3304 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3305 + sb_setcoreidx(&si->sb, origidx);
3306 + return NULL;
3307 + }
3308 + }
3309 +
3310 + /* get chipcommon rev */
3311 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3312 +
3313 + /* determine numcores */
3314 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3315 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3316 + else
3317 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3318 +
3319 + /* return to original core */
3320 + sb_setcoreidx(&si->sb, origidx);
3321 +
3322 + /* sanity checks */
3323 + ASSERT(si->sb.chip);
3324 +
3325 + /* scan for cores */
3326 + BCMINIT(sb_scan)(si);
3327 +
3328 + /* fixup necessary chip/core configurations */
3329 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3330 + if (sb_pci_fixcfg(si)) {
3331 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3332 + return NULL;
3333 + }
3334 + }
3335 +
3336 + /* srom_var_init() depends on sb_scan() info */
3337 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3338 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3339 + return (NULL);
3340 + }
3341 +
3342 + if (cc == NULL) {
3343 + /*
3344 + * The chip revision number is hardwired into all
3345 + * of the pci function config rev fields and is
3346 + * independent from the individual core revision numbers.
3347 + * For example, the "A0" silicon of each chip is chip rev 0.
3348 + */
3349 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3350 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3351 + si->sb.chiprev = w & 0xff;
3352 + } else
3353 + si->sb.chiprev = 0;
3354 + }
3355 +
3356 + /* gpio control core is required */
3357 + if (!GOODIDX(si->gpioidx)) {
3358 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3359 + return NULL;
3360 + }
3361 +
3362 + /* get boardtype and boardrev */
3363 + switch (BUSTYPE(si->sb.bustype)) {
3364 + case PCI_BUS:
3365 + /* do a pci config read to get subsystem id and subvendor id */
3366 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3367 + si->sb.boardvendor = w & 0xffff;
3368 + si->sb.boardtype = (w >> 16) & 0xffff;
3369 + break;
3370 +
3371 + case SB_BUS:
3372 + case JTAG_BUS:
3373 + si->sb.boardvendor = VENDOR_BROADCOM;
3374 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3375 + si->sb.boardtype = 0xffff;
3376 + break;
3377 + }
3378 +
3379 + if (si->sb.boardtype == 0) {
3380 + SB_ERROR(("sb_doattach: unknown board type\n"));
3381 + ASSERT(si->sb.boardtype);
3382 + }
3383 +
3384 + /* setup the GPIO based LED powersave register */
3385 + if (si->sb.ccrev >= 16) {
3386 + w = getintvar(*vars, "gpiotimerval");
3387 + if (!w)
3388 + w = DEFAULT_GPIOTIMERVAL;
3389 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3390 + }
3391 +
3392 +
3393 + return (si);
3394 +}
3395 +
3396 +uint
3397 +sb_coreid(sb_t *sbh)
3398 +{
3399 + sb_info_t *si;
3400 + sbconfig_t *sb;
3401 +
3402 + si = SB_INFO(sbh);
3403 + sb = REGS2SB(si->curmap);
3404 +
3405 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3406 +}
3407 +
3408 +uint
3409 +sb_coreidx(sb_t *sbh)
3410 +{
3411 + sb_info_t *si;
3412 +
3413 + si = SB_INFO(sbh);
3414 + return (si->curidx);
3415 +}
3416 +
3417 +/* return current index of core */
3418 +static uint
3419 +_sb_coreidx(sb_info_t *si)
3420 +{
3421 + sbconfig_t *sb;
3422 + uint32 sbaddr = 0;
3423 +
3424 + ASSERT(si);
3425 +
3426 + switch (BUSTYPE(si->sb.bustype)) {
3427 + case SB_BUS:
3428 + sb = REGS2SB(si->curmap);
3429 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3430 + break;
3431 +
3432 + case PCI_BUS:
3433 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3434 + break;
3435 +
3436 +#ifdef BCMJTAG
3437 + case JTAG_BUS:
3438 + sbaddr = (uint32)si->curmap;
3439 + break;
3440 +#endif /* BCMJTAG */
3441 +
3442 + default:
3443 + ASSERT(0);
3444 + }
3445 +
3446 + if (!GOODCOREADDR(sbaddr))
3447 + return BADIDX;
3448 +
3449 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3450 +}
3451 +
3452 +uint
3453 +sb_corevendor(sb_t *sbh)
3454 +{
3455 + sb_info_t *si;
3456 + sbconfig_t *sb;
3457 +
3458 + si = SB_INFO(sbh);
3459 + sb = REGS2SB(si->curmap);
3460 +
3461 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3462 +}
3463 +
3464 +uint
3465 +sb_corerev(sb_t *sbh)
3466 +{
3467 + sb_info_t *si;
3468 + sbconfig_t *sb;
3469 + uint sbidh;
3470 +
3471 + si = SB_INFO(sbh);
3472 + sb = REGS2SB(si->curmap);
3473 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3474 +
3475 + return (SBCOREREV(sbidh));
3476 +}
3477 +
3478 +void *
3479 +sb_osh(sb_t *sbh)
3480 +{
3481 + sb_info_t *si;
3482 +
3483 + si = SB_INFO(sbh);
3484 + return si->osh;
3485 +}
3486 +
3487 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3488 +
3489 +/* set/clear sbtmstatelow core-specific flags */
3490 +uint32
3491 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3492 +{
3493 + sb_info_t *si;
3494 + sbconfig_t *sb;
3495 + uint32 w;
3496 +
3497 + si = SB_INFO(sbh);
3498 + sb = REGS2SB(si->curmap);
3499 +
3500 + ASSERT((val & ~mask) == 0);
3501 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3502 +
3503 + /* mask and set */
3504 + if (mask || val) {
3505 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3506 + W_SBREG(si, &sb->sbtmstatelow, w);
3507 + }
3508 +
3509 + /* return the new value */
3510 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3511 +}
3512 +
3513 +/* set/clear sbtmstatehigh core-specific flags */
3514 +uint32
3515 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3516 +{
3517 + sb_info_t *si;
3518 + sbconfig_t *sb;
3519 + uint32 w;
3520 +
3521 + si = SB_INFO(sbh);
3522 + sb = REGS2SB(si->curmap);
3523 +
3524 + ASSERT((val & ~mask) == 0);
3525 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3526 +
3527 + /* mask and set */
3528 + if (mask || val) {
3529 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3530 + W_SBREG(si, &sb->sbtmstatehigh, w);
3531 + }
3532 +
3533 + /* return the new value */
3534 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3535 +}
3536 +
3537 +/* caller needs to take care of core-specific bist hazards */
3538 +int
3539 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3540 +{
3541 + uint32 sblo;
3542 + uint coreidx;
3543 + sb_info_t *si;
3544 + int result = 0;
3545 +
3546 + si = SB_INFO(sbh);
3547 +
3548 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3549 + if (!GOODIDX(coreidx))
3550 + result = BCME_ERROR;
3551 + else {
3552 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3553 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3554 +
3555 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3556 +
3557 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3558 + result = BCME_ERROR;
3559 +
3560 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3561 + }
3562 +
3563 + return result;
3564 +}
3565 +
3566 +bool
3567 +sb_iscoreup(sb_t *sbh)
3568 +{
3569 + sb_info_t *si;
3570 + sbconfig_t *sb;
3571 +
3572 + si = SB_INFO(sbh);
3573 + sb = REGS2SB(si->curmap);
3574 +
3575 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3576 +}
3577 +
3578 +/*
3579 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3580 + * switch back to the original core, and return the new value.
3581 + */
3582 +static uint
3583 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3584 +{
3585 + uint origidx;
3586 + uint32 *r;
3587 + uint w;
3588 + uint intr_val = 0;
3589 +
3590 + ASSERT(GOODIDX(coreidx));
3591 + ASSERT(regoff < SB_CORE_SIZE);
3592 + ASSERT((val & ~mask) == 0);
3593 +
3594 + INTR_OFF(si, intr_val);
3595 +
3596 + /* save current core index */
3597 + origidx = sb_coreidx(&si->sb);
3598 +
3599 + /* switch core */
3600 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3601 +
3602 + /* mask and set */
3603 + if (mask || val) {
3604 + if (regoff >= SBCONFIGOFF) {
3605 + w = (R_SBREG(si, r) & ~mask) | val;
3606 + W_SBREG(si, r, w);
3607 + } else {
3608 + w = (R_REG(r) & ~mask) | val;
3609 + W_REG(r, w);
3610 + }
3611 + }
3612 +
3613 + /* readback */
3614 + if (regoff >= SBCONFIGOFF)
3615 + w = R_SBREG(si, r);
3616 + else
3617 + w = R_REG(r);
3618 +
3619 + /* restore core index */
3620 + if (origidx != coreidx)
3621 + sb_setcoreidx(&si->sb, origidx);
3622 +
3623 + INTR_RESTORE(si, intr_val);
3624 + return (w);
3625 +}
3626 +
3627 +#define DWORD_ALIGN(x) (x & ~(0x03))
3628 +#define BYTE_POS(x) (x & 0x3)
3629 +#define WORD_POS(x) (x & 0x1)
3630 +
3631 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3632 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3633 +
3634 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3635 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3636 +
3637 +#define read_pci_cfg_byte(a) \
3638 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3639 +
3640 +#define read_pci_cfg_write(a) \
3641 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3642 +
3643 +
3644 +/* scan the sb enumerated space to identify all cores */
3645 +static void
3646 +BCMINITFN(sb_scan)(sb_info_t *si)
3647 +{
3648 + uint origidx;
3649 + uint i;
3650 + bool pci;
3651 + uint pciidx;
3652 + uint pcirev;
3653 +
3654 +
3655 +
3656 + /* numcores should already be set */
3657 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3658 +
3659 + /* save current core index */
3660 + origidx = sb_coreidx(&si->sb);
3661 +
3662 + si->sb.buscorerev = NOREV;
3663 + si->sb.buscoreidx = BADIDX;
3664 +
3665 + si->gpioidx = BADIDX;
3666 +
3667 + pci = FALSE;
3668 + pcirev = NOREV;
3669 + pciidx = BADIDX;
3670 +
3671 + for (i = 0; i < si->numcores; i++) {
3672 + sb_setcoreidx(&si->sb, i);
3673 + si->coreid[i] = sb_coreid(&si->sb);
3674 +
3675 + if (si->coreid[i] == SB_PCI) {
3676 + pciidx = i;
3677 + pcirev = sb_corerev(&si->sb);
3678 + pci = TRUE;
3679 + }
3680 + }
3681 + if (pci) {
3682 + si->sb.buscoretype = SB_PCI;
3683 + si->sb.buscorerev = pcirev;
3684 + si->sb.buscoreidx = pciidx;
3685 + }
3686 +
3687 + /*
3688 + * Find the gpio "controlling core" type and index.
3689 + * Precedence:
3690 + * - if there's a chip common core - use that
3691 + * - else if there's a pci core (rev >= 2) - use that
3692 + * - else there had better be an extif core (4710 only)
3693 + */
3694 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3695 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3696 + si->gpioid = SB_CC;
3697 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3698 + si->gpioidx = si->sb.buscoreidx;
3699 + si->gpioid = SB_PCI;
3700 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3701 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3702 + si->gpioid = SB_EXTIF;
3703 + } else
3704 + ASSERT(si->gpioidx != BADIDX);
3705 +
3706 + /* return to original core index */
3707 + sb_setcoreidx(&si->sb, origidx);
3708 +}
3709 +
3710 +/* may be called with core in reset */
3711 +void
3712 +sb_detach(sb_t *sbh)
3713 +{
3714 + sb_info_t *si;
3715 + uint idx;
3716 +
3717 + si = SB_INFO(sbh);
3718 +
3719 + if (si == NULL)
3720 + return;
3721 +
3722 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3723 + for (idx = 0; idx < SB_MAXCORES; idx++)
3724 + if (si->regs[idx]) {
3725 + REG_UNMAP(si->regs[idx]);
3726 + si->regs[idx] = NULL;
3727 + }
3728 +
3729 + if (si != &ksi)
3730 + MFREE(si->osh, si, sizeof (sb_info_t));
3731 +}
3732 +
3733 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3734 +static uint
3735 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3736 +{
3737 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3738 + return (BCM4710_DEVICE_ID);
3739 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3740 + return (BCM4402_DEVICE_ID);
3741 + if (pcidev == BCM4401_ENET_ID)
3742 + return (BCM4402_DEVICE_ID);
3743 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3744 + return (BCM4307_DEVICE_ID);
3745 + if (pcidev == BCM4301_DEVICE_ID)
3746 + return (BCM4301_DEVICE_ID);
3747 +
3748 + return (0);
3749 +}
3750 +
3751 +/* convert chip number to number of i/o cores */
3752 +static uint
3753 +BCMINITFN(sb_chip2numcores)(uint chip)
3754 +{
3755 + if (chip == BCM4710_DEVICE_ID)
3756 + return (9);
3757 + if (chip == BCM4402_DEVICE_ID)
3758 + return (3);
3759 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3760 + return (5);
3761 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3762 + return (6);
3763 + if (chip == BCM4704_DEVICE_ID)
3764 + return (9);
3765 + if (chip == BCM5365_DEVICE_ID)
3766 + return (7);
3767 +
3768 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3769 + ASSERT(0);
3770 + return (1);
3771 +}
3772 +
3773 +/* return index of coreid or BADIDX if not found */
3774 +static uint
3775 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3776 +{
3777 + uint found;
3778 + uint i;
3779 +
3780 + found = 0;
3781 +
3782 + for (i = 0; i < si->numcores; i++)
3783 + if (si->coreid[i] == coreid) {
3784 + if (found == coreunit)
3785 + return (i);
3786 + found++;
3787 + }
3788 +
3789 + return (BADIDX);
3790 +}
3791 +
3792 +/*
3793 + * this function changes logical "focus" to the indiciated core,
3794 + * must be called with interrupt off.
3795 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3796 + */
3797 +void*
3798 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3799 +{
3800 + sb_info_t *si;
3801 + uint32 sbaddr;
3802 +
3803 + si = SB_INFO(sbh);
3804 +
3805 + if (coreidx >= si->numcores)
3806 + return (NULL);
3807 +
3808 + /*
3809 + * If the user has provided an interrupt mask enabled function,
3810 + * then assert interrupts are disabled before switching the core.
3811 + */
3812 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3813 +
3814 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3815 +
3816 + switch (BUSTYPE(si->sb.bustype)) {
3817 + case SB_BUS:
3818 + /* map new one */
3819 + if (!si->regs[coreidx]) {
3820 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3821 + ASSERT(GOODREGS(si->regs[coreidx]));
3822 + }
3823 + si->curmap = si->regs[coreidx];
3824 + break;
3825 +
3826 + case PCI_BUS:
3827 + /* point bar0 window */
3828 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3829 + break;
3830 +
3831 +#ifdef BCMJTAG
3832 + case JTAG_BUS:
3833 + /* map new one */
3834 + if (!si->regs[coreidx]) {
3835 + si->regs[coreidx] = (void *)sbaddr;
3836 + ASSERT(GOODREGS(si->regs[coreidx]));
3837 + }
3838 + si->curmap = si->regs[coreidx];
3839 + break;
3840 +#endif /* BCMJTAG */
3841 + }
3842 +
3843 + si->curidx = coreidx;
3844 +
3845 + return (si->curmap);
3846 +}
3847 +
3848 +/*
3849 + * this function changes logical "focus" to the indiciated core,
3850 + * must be called with interrupt off.
3851 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3852 + */
3853 +void*
3854 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3855 +{
3856 + sb_info_t *si;
3857 + uint idx;
3858 +
3859 + si = SB_INFO(sbh);
3860 + idx = sb_findcoreidx(si, coreid, coreunit);
3861 + if (!GOODIDX(idx))
3862 + return (NULL);
3863 +
3864 + return (sb_setcoreidx(sbh, idx));
3865 +}
3866 +
3867 +/* return chip number */
3868 +uint
3869 +BCMINITFN(sb_chip)(sb_t *sbh)
3870 +{
3871 + sb_info_t *si;
3872 +
3873 + si = SB_INFO(sbh);
3874 + return (si->sb.chip);
3875 +}
3876 +
3877 +/* return chip revision number */
3878 +uint
3879 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3880 +{
3881 + sb_info_t *si;
3882 +
3883 + si = SB_INFO(sbh);
3884 + return (si->sb.chiprev);
3885 +}
3886 +
3887 +/* return chip common revision number */
3888 +uint
3889 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3890 +{
3891 + sb_info_t *si;
3892 +
3893 + si = SB_INFO(sbh);
3894 + return (si->sb.ccrev);
3895 +}
3896 +
3897 +/* return chip package option */
3898 +uint
3899 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3900 +{
3901 + sb_info_t *si;
3902 +
3903 + si = SB_INFO(sbh);
3904 + return (si->sb.chippkg);
3905 +}
3906 +
3907 +/* return PCI core rev. */
3908 +uint
3909 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3910 +{
3911 + sb_info_t *si;
3912 +
3913 + si = SB_INFO(sbh);
3914 + return (si->sb.buscorerev);
3915 +}
3916 +
3917 +bool
3918 +BCMINITFN(sb_war16165)(sb_t *sbh)
3919 +{
3920 + sb_info_t *si;
3921 +
3922 + si = SB_INFO(sbh);
3923 +
3924 + return (PCI(si) && (si->sb.buscorerev <= 10));
3925 +}
3926 +
3927 +/* return board vendor id */
3928 +uint
3929 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3930 +{
3931 + sb_info_t *si;
3932 +
3933 + si = SB_INFO(sbh);
3934 + return (si->sb.boardvendor);
3935 +}
3936 +
3937 +/* return boardtype */
3938 +uint
3939 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3940 +{
3941 + sb_info_t *si;
3942 + char *var;
3943 +
3944 + si = SB_INFO(sbh);
3945 +
3946 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3947 + /* boardtype format is a hex string */
3948 + si->sb.boardtype = getintvar(NULL, "boardtype");
3949 +
3950 + /* backward compatibility for older boardtype string format */
3951 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3952 + if (!strcmp(var, "bcm94710dev"))
3953 + si->sb.boardtype = BCM94710D_BOARD;
3954 + else if (!strcmp(var, "bcm94710ap"))
3955 + si->sb.boardtype = BCM94710AP_BOARD;
3956 + else if (!strcmp(var, "bu4710"))
3957 + si->sb.boardtype = BU4710_BOARD;
3958 + else if (!strcmp(var, "bcm94702mn"))
3959 + si->sb.boardtype = BCM94702MN_BOARD;
3960 + else if (!strcmp(var, "bcm94710r1"))
3961 + si->sb.boardtype = BCM94710R1_BOARD;
3962 + else if (!strcmp(var, "bcm94710r4"))
3963 + si->sb.boardtype = BCM94710R4_BOARD;
3964 + else if (!strcmp(var, "bcm94702cpci"))
3965 + si->sb.boardtype = BCM94702CPCI_BOARD;
3966 + else if (!strcmp(var, "bcm95380_rr"))
3967 + si->sb.boardtype = BCM95380RR_BOARD;
3968 + }
3969 + }
3970 +
3971 + return (si->sb.boardtype);
3972 +}
3973 +
3974 +/* return bus type of sbh device */
3975 +uint
3976 +sb_bus(sb_t *sbh)
3977 +{
3978 + sb_info_t *si;
3979 +
3980 + si = SB_INFO(sbh);
3981 + return (si->sb.bustype);
3982 +}
3983 +
3984 +/* return bus core type */
3985 +uint
3986 +sb_buscoretype(sb_t *sbh)
3987 +{
3988 + sb_info_t *si;
3989 +
3990 + si = SB_INFO(sbh);
3991 +
3992 + return (si->sb.buscoretype);
3993 +}
3994 +
3995 +/* return bus core revision */
3996 +uint
3997 +sb_buscorerev(sb_t *sbh)
3998 +{
3999 + sb_info_t *si;
4000 + si = SB_INFO(sbh);
4001 +
4002 + return (si->sb.buscorerev);
4003 +}
4004 +
4005 +/* return list of found cores */
4006 +uint
4007 +sb_corelist(sb_t *sbh, uint coreid[])
4008 +{
4009 + sb_info_t *si;
4010 +
4011 + si = SB_INFO(sbh);
4012 +
4013 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
4014 + return (si->numcores);
4015 +}
4016 +
4017 +/* return current register mapping */
4018 +void *
4019 +sb_coreregs(sb_t *sbh)
4020 +{
4021 + sb_info_t *si;
4022 +
4023 + si = SB_INFO(sbh);
4024 + ASSERT(GOODREGS(si->curmap));
4025 +
4026 + return (si->curmap);
4027 +}
4028 +
4029 +
4030 +/* do buffered registers update */
4031 +void
4032 +sb_commit(sb_t *sbh)
4033 +{
4034 + sb_info_t *si;
4035 + uint origidx;
4036 + uint intr_val = 0;
4037 +
4038 + si = SB_INFO(sbh);
4039 +
4040 + origidx = si->curidx;
4041 + ASSERT(GOODIDX(origidx));
4042 +
4043 + INTR_OFF(si, intr_val);
4044 +
4045 + /* switch over to chipcommon core if there is one, else use pci */
4046 + if (si->sb.ccrev != NOREV) {
4047 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4048 +
4049 + /* do the buffer registers update */
4050 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4051 + W_REG(&ccregs->broadcastdata, 0x0);
4052 + } else if (PCI(si)) {
4053 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4054 +
4055 + /* do the buffer registers update */
4056 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4057 + W_REG(&pciregs->bcastdata, 0x0);
4058 + } else
4059 + ASSERT(0);
4060 +
4061 + /* restore core index */
4062 + sb_setcoreidx(sbh, origidx);
4063 + INTR_RESTORE(si, intr_val);
4064 +}
4065 +
4066 +/* reset and re-enable a core */
4067 +void
4068 +sb_core_reset(sb_t *sbh, uint32 bits)
4069 +{
4070 + sb_info_t *si;
4071 + sbconfig_t *sb;
4072 + volatile uint32 dummy;
4073 +
4074 + si = SB_INFO(sbh);
4075 + ASSERT(GOODREGS(si->curmap));
4076 + sb = REGS2SB(si->curmap);
4077 +
4078 + /*
4079 + * Must do the disable sequence first to work for arbitrary current core state.
4080 + */
4081 + sb_core_disable(sbh, bits);
4082 +
4083 + /*
4084 + * Now do the initialization sequence.
4085 + */
4086 +
4087 + /* set reset while enabling the clock and forcing them on throughout the core */
4088 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4089 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4090 + OSL_DELAY(1);
4091 +
4092 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4093 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4094 + }
4095 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4096 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4097 + }
4098 +
4099 + /* clear reset and allow it to propagate throughout the core */
4100 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4101 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4102 + OSL_DELAY(1);
4103 +
4104 + /* leave clock enabled */
4105 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4106 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4107 + OSL_DELAY(1);
4108 +}
4109 +
4110 +void
4111 +sb_core_tofixup(sb_t *sbh)
4112 +{
4113 + sb_info_t *si;
4114 + sbconfig_t *sb;
4115 +
4116 + si = SB_INFO(sbh);
4117 +
4118 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4119 + return;
4120 +
4121 + ASSERT(GOODREGS(si->curmap));
4122 + sb = REGS2SB(si->curmap);
4123 +
4124 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4125 + SET_SBREG(si, &sb->sbimconfiglow,
4126 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4127 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4128 + } else {
4129 + if (sb_coreid(sbh) == SB_PCI) {
4130 + SET_SBREG(si, &sb->sbimconfiglow,
4131 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4132 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4133 + } else {
4134 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4135 + }
4136 + }
4137 +
4138 + sb_commit(sbh);
4139 +}
4140 +
4141 +/*
4142 + * Set the initiator timeout for the "master core".
4143 + * The master core is defined to be the core in control
4144 + * of the chip and so it issues accesses to non-memory
4145 + * locations (Because of dma *any* core can access memeory).
4146 + *
4147 + * The routine uses the bus to decide who is the master:
4148 + * SB_BUS => mips
4149 + * JTAG_BUS => chipc
4150 + * PCI_BUS => pci
4151 + *
4152 + * This routine exists so callers can disable initiator
4153 + * timeouts so accesses to very slow devices like otp
4154 + * won't cause an abort. The routine allows arbitrary
4155 + * settings of the service and request timeouts, though.
4156 + *
4157 + * Returns the timeout state before changing it or -1
4158 + * on error.
4159 + */
4160 +
4161 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4162 +
4163 +uint32
4164 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4165 +{
4166 + sb_info_t *si;
4167 + uint origidx, idx;
4168 + uint intr_val = 0;
4169 + uint32 tmp, ret = 0xffffffff;
4170 + sbconfig_t *sb;
4171 +
4172 + si = SB_INFO(sbh);
4173 +
4174 + if ((to & ~TO_MASK) != 0)
4175 + return ret;
4176 +
4177 + /* Figure out the master core */
4178 + idx = BADIDX;
4179 + switch (BUSTYPE(si->sb.bustype)) {
4180 + case PCI_BUS:
4181 + idx = si->sb.buscoreidx;
4182 + break;
4183 + case JTAG_BUS:
4184 + idx = SB_CC_IDX;
4185 + break;
4186 + case SB_BUS:
4187 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4188 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4189 + break;
4190 + default:
4191 + ASSERT(0);
4192 + }
4193 + if (idx == BADIDX)
4194 + return ret;
4195 +
4196 + INTR_OFF(si, intr_val);
4197 + origidx = sb_coreidx(sbh);
4198 +
4199 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4200 +
4201 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4202 + ret = tmp & TO_MASK;
4203 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4204 +
4205 + sb_commit(sbh);
4206 + sb_setcoreidx(sbh, origidx);
4207 + INTR_RESTORE(si, intr_val);
4208 + return ret;
4209 +}
4210 +
4211 +void
4212 +sb_core_disable(sb_t *sbh, uint32 bits)
4213 +{
4214 + sb_info_t *si;
4215 + volatile uint32 dummy;
4216 + uint32 rej;
4217 + sbconfig_t *sb;
4218 +
4219 + si = SB_INFO(sbh);
4220 +
4221 + ASSERT(GOODREGS(si->curmap));
4222 + sb = REGS2SB(si->curmap);
4223 +
4224 + /* if core is already in reset, just return */
4225 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4226 + return;
4227 +
4228 + /* reject value changed between sonics 2.2 and 2.3 */
4229 + if (si->sb.sonicsrev == SONICS_2_2)
4230 + rej = (1 << SBTML_REJ_SHIFT);
4231 + else
4232 + rej = (2 << SBTML_REJ_SHIFT);
4233 +
4234 + /* if clocks are not enabled, put into reset and return */
4235 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4236 + goto disable;
4237 +
4238 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4239 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4240 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4241 + OSL_DELAY(1);
4242 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4243 +
4244 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4245 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4246 + dummy = R_SBREG(si, &sb->sbimstate);
4247 + OSL_DELAY(1);
4248 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4249 + }
4250 +
4251 + /* set reset and reject while enabling the clocks */
4252 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4253 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4254 + OSL_DELAY(10);
4255 +
4256 + /* don't forget to clear the initiator reject bit */
4257 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4258 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4259 +
4260 +disable:
4261 + /* leave reset and reject asserted */
4262 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4263 + OSL_DELAY(1);
4264 +}
4265 +
4266 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4267 +void
4268 +sb_watchdog(sb_t *sbh, uint ticks)
4269 +{
4270 + sb_info_t *si = SB_INFO(sbh);
4271 +
4272 + /* instant NMI */
4273 + switch (si->gpioid) {
4274 + case SB_CC:
4275 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4276 + break;
4277 + case SB_EXTIF:
4278 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4279 + break;
4280 + }
4281 +}
4282 +
4283 +
4284 +/*
4285 + * Configure the pci core for pci client (NIC) action
4286 + * coremask is the bitvec of cores by index to be enabled.
4287 + */
4288 +void
4289 +sb_pci_setup(sb_t *sbh, uint coremask)
4290 +{
4291 + sb_info_t *si;
4292 + sbconfig_t *sb;
4293 + sbpciregs_t *pciregs;
4294 + uint32 sbflag;
4295 + uint32 w;
4296 + uint idx;
4297 +
4298 + si = SB_INFO(sbh);
4299 +
4300 + /* if not pci bus, we're done */
4301 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4302 + return;
4303 +
4304 + ASSERT(PCI(si));
4305 + ASSERT(si->sb.buscoreidx != BADIDX);
4306 +
4307 + /* get current core index */
4308 + idx = si->curidx;
4309 +
4310 + /* we interrupt on this backplane flag number */
4311 + ASSERT(GOODREGS(si->curmap));
4312 + sb = REGS2SB(si->curmap);
4313 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4314 +
4315 + /* switch over to pci core */
4316 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4317 + sb = REGS2SB(pciregs);
4318 +
4319 + /*
4320 + * Enable sb->pci interrupts. Assume
4321 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4322 + */
4323 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4324 + /* pci config write to set this core bit in PCIIntMask */
4325 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4326 + w |= (coremask << PCI_SBIM_SHIFT);
4327 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4328 + } else {
4329 + /* set sbintvec bit for our flag number */
4330 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4331 + }
4332 +
4333 + if (PCI(si)) {
4334 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4335 + if (si->sb.buscorerev >= 11)
4336 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4337 + if (si->sb.buscorerev < 5) {
4338 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4339 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4340 + sb_commit(sbh);
4341 + }
4342 + }
4343 +
4344 + /* switch back to previous core */
4345 + sb_setcoreidx(sbh, idx);
4346 +}
4347 +
4348 +uint32
4349 +sb_base(uint32 admatch)
4350 +{
4351 + uint32 base;
4352 + uint type;
4353 +
4354 + type = admatch & SBAM_TYPE_MASK;
4355 + ASSERT(type < 3);
4356 +
4357 + base = 0;
4358 +
4359 + if (type == 0) {
4360 + base = admatch & SBAM_BASE0_MASK;
4361 + } else if (type == 1) {
4362 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4363 + base = admatch & SBAM_BASE1_MASK;
4364 + } else if (type == 2) {
4365 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4366 + base = admatch & SBAM_BASE2_MASK;
4367 + }
4368 +
4369 + return (base);
4370 +}
4371 +
4372 +uint32
4373 +sb_size(uint32 admatch)
4374 +{
4375 + uint32 size;
4376 + uint type;
4377 +
4378 + type = admatch & SBAM_TYPE_MASK;
4379 + ASSERT(type < 3);
4380 +
4381 + size = 0;
4382 +
4383 + if (type == 0) {
4384 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4385 + } else if (type == 1) {
4386 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4387 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4388 + } else if (type == 2) {
4389 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4390 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4391 + }
4392 +
4393 + return (size);
4394 +}
4395 +
4396 +/* return the core-type instantiation # of the current core */
4397 +uint
4398 +sb_coreunit(sb_t *sbh)
4399 +{
4400 + sb_info_t *si;
4401 + uint idx;
4402 + uint coreid;
4403 + uint coreunit;
4404 + uint i;
4405 +
4406 + si = SB_INFO(sbh);
4407 + coreunit = 0;
4408 +
4409 + idx = si->curidx;
4410 +
4411 + ASSERT(GOODREGS(si->curmap));
4412 + coreid = sb_coreid(sbh);
4413 +
4414 + /* count the cores of our type */
4415 + for (i = 0; i < idx; i++)
4416 + if (si->coreid[i] == coreid)
4417 + coreunit++;
4418 +
4419 + return (coreunit);
4420 +}
4421 +
4422 +static INLINE uint32
4423 +factor6(uint32 x)
4424 +{
4425 + switch (x) {
4426 + case CC_F6_2: return 2;
4427 + case CC_F6_3: return 3;
4428 + case CC_F6_4: return 4;
4429 + case CC_F6_5: return 5;
4430 + case CC_F6_6: return 6;
4431 + case CC_F6_7: return 7;
4432 + default: return 0;
4433 + }
4434 +}
4435 +
4436 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4437 +uint32
4438 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4439 +{
4440 + uint32 n1, n2, clock, m1, m2, m3, mc;
4441 +
4442 + n1 = n & CN_N1_MASK;
4443 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4444 +
4445 + if (pll_type == PLL_TYPE6) {
4446 + if (m & CC_T6_MMASK)
4447 + return CC_T6_M1;
4448 + else
4449 + return CC_T6_M0;
4450 + } else if ((pll_type == PLL_TYPE1) ||
4451 + (pll_type == PLL_TYPE3) ||
4452 + (pll_type == PLL_TYPE4) ||
4453 + (pll_type == PLL_TYPE7)) {
4454 + n1 = factor6(n1);
4455 + n2 += CC_F5_BIAS;
4456 + } else if (pll_type == PLL_TYPE2) {
4457 + n1 += CC_T2_BIAS;
4458 + n2 += CC_T2_BIAS;
4459 + ASSERT((n1 >= 2) && (n1 <= 7));
4460 + ASSERT((n2 >= 5) && (n2 <= 23));
4461 + } else if (pll_type == PLL_TYPE5) {
4462 + return (100000000);
4463 + } else
4464 + ASSERT(0);
4465 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4466 + if ((pll_type == PLL_TYPE3) ||
4467 + (pll_type == PLL_TYPE7)) {
4468 + clock = CC_CLOCK_BASE2 * n1 * n2;
4469 + }
4470 + else
4471 + clock = CC_CLOCK_BASE1 * n1 * n2;
4472 +
4473 + if (clock == 0)
4474 + return 0;
4475 +
4476 + m1 = m & CC_M1_MASK;
4477 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4478 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4479 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4480 +
4481 + if ((pll_type == PLL_TYPE1) ||
4482 + (pll_type == PLL_TYPE3) ||
4483 + (pll_type == PLL_TYPE4) ||
4484 + (pll_type == PLL_TYPE7)) {
4485 + m1 = factor6(m1);
4486 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4487 + m2 += CC_F5_BIAS;
4488 + else
4489 + m2 = factor6(m2);
4490 + m3 = factor6(m3);
4491 +
4492 + switch (mc) {
4493 + case CC_MC_BYPASS: return (clock);
4494 + case CC_MC_M1: return (clock / m1);
4495 + case CC_MC_M1M2: return (clock / (m1 * m2));
4496 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4497 + case CC_MC_M1M3: return (clock / (m1 * m3));
4498 + default: return (0);
4499 + }
4500 + } else {
4501 + ASSERT(pll_type == PLL_TYPE2);
4502 +
4503 + m1 += CC_T2_BIAS;
4504 + m2 += CC_T2M2_BIAS;
4505 + m3 += CC_T2_BIAS;
4506 + ASSERT((m1 >= 2) && (m1 <= 7));
4507 + ASSERT((m2 >= 3) && (m2 <= 10));
4508 + ASSERT((m3 >= 2) && (m3 <= 7));
4509 +
4510 + if ((mc & CC_T2MC_M1BYP) == 0)
4511 + clock /= m1;
4512 + if ((mc & CC_T2MC_M2BYP) == 0)
4513 + clock /= m2;
4514 + if ((mc & CC_T2MC_M3BYP) == 0)
4515 + clock /= m3;
4516 +
4517 + return(clock);
4518 + }
4519 +}
4520 +
4521 +/* returns the current speed the SB is running at */
4522 +uint32
4523 +sb_clock(sb_t *sbh)
4524 +{
4525 + sb_info_t *si;
4526 + extifregs_t *eir;
4527 + chipcregs_t *cc;
4528 + uint32 n, m;
4529 + uint idx;
4530 + uint32 pll_type, rate;
4531 + uint intr_val = 0;
4532 +
4533 + si = SB_INFO(sbh);
4534 + idx = si->curidx;
4535 + pll_type = PLL_TYPE1;
4536 +
4537 + INTR_OFF(si, intr_val);
4538 +
4539 + /* switch to extif or chipc core */
4540 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4541 + n = R_REG(&eir->clockcontrol_n);
4542 + m = R_REG(&eir->clockcontrol_sb);
4543 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4544 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4545 + n = R_REG(&cc->clockcontrol_n);
4546 + if (pll_type == PLL_TYPE6)
4547 + m = R_REG(&cc->clockcontrol_mips);
4548 + else if (pll_type == PLL_TYPE3)
4549 + {
4550 + // Added by Chen-I for 5365
4551 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4552 + m = R_REG(&cc->clockcontrol_sb);
4553 + else
4554 + m = R_REG(&cc->clockcontrol_m2);
4555 + }
4556 + else
4557 + m = R_REG(&cc->clockcontrol_sb);
4558 + } else {
4559 + INTR_RESTORE(si, intr_val);
4560 + return 0;
4561 + }
4562 +
4563 + // Added by Chen-I for 5365
4564 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4565 + {
4566 + rate = 100000000;
4567 + }
4568 + else
4569 + {
4570 + /* calculate rate */
4571 + rate = sb_clock_rate(pll_type, n, m);
4572 + if (pll_type == PLL_TYPE3)
4573 + rate = rate / 2;
4574 + }
4575 +
4576 + /* switch back to previous core */
4577 + sb_setcoreidx(sbh, idx);
4578 +
4579 + INTR_RESTORE(si, intr_val);
4580 +
4581 + return rate;
4582 +}
4583 +
4584 +/* change logical "focus" to the gpio core for optimized access */
4585 +void*
4586 +sb_gpiosetcore(sb_t *sbh)
4587 +{
4588 + sb_info_t *si;
4589 +
4590 + si = SB_INFO(sbh);
4591 +
4592 + return (sb_setcoreidx(sbh, si->gpioidx));
4593 +}
4594 +
4595 +/* mask&set gpiocontrol bits */
4596 +uint32
4597 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4598 +{
4599 + sb_info_t *si;
4600 + uint regoff;
4601 +
4602 + si = SB_INFO(sbh);
4603 + regoff = 0;
4604 +
4605 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4606 +
4607 + /* gpios could be shared on router platforms */
4608 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4609 + mask = priority ? (sb_gpioreservation & mask) :
4610 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4611 + val &= mask;
4612 + }
4613 +
4614 + switch (si->gpioid) {
4615 + case SB_CC:
4616 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4617 + break;
4618 +
4619 + case SB_PCI:
4620 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4621 + break;
4622 +
4623 + case SB_EXTIF:
4624 + return (0);
4625 + }
4626 +
4627 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4628 +}
4629 +
4630 +/* mask&set gpio output enable bits */
4631 +uint32
4632 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4633 +{
4634 + sb_info_t *si;
4635 + uint regoff;
4636 +
4637 + si = SB_INFO(sbh);
4638 + regoff = 0;
4639 +
4640 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4641 +
4642 + /* gpios could be shared on router platforms */
4643 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4644 + mask = priority ? (sb_gpioreservation & mask) :
4645 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4646 + val &= mask;
4647 + }
4648 +
4649 + switch (si->gpioid) {
4650 + case SB_CC:
4651 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4652 + break;
4653 +
4654 + case SB_PCI:
4655 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4656 + break;
4657 +
4658 + case SB_EXTIF:
4659 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4660 + break;
4661 + }
4662 +
4663 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4664 +}
4665 +
4666 +/* mask&set gpio output bits */
4667 +uint32
4668 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4669 +{
4670 + sb_info_t *si;
4671 + uint regoff;
4672 +
4673 + si = SB_INFO(sbh);
4674 + regoff = 0;
4675 +
4676 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4677 +
4678 + /* gpios could be shared on router platforms */
4679 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4680 + mask = priority ? (sb_gpioreservation & mask) :
4681 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4682 + val &= mask;
4683 + }
4684 +
4685 + switch (si->gpioid) {
4686 + case SB_CC:
4687 + regoff = OFFSETOF(chipcregs_t, gpioout);
4688 + break;
4689 +
4690 + case SB_PCI:
4691 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4692 + break;
4693 +
4694 + case SB_EXTIF:
4695 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4696 + break;
4697 + }
4698 +
4699 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4700 +}
4701 +
4702 +/* reserve one gpio */
4703 +uint32
4704 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4705 +{
4706 + sb_info_t *si;
4707 +
4708 + si = SB_INFO(sbh);
4709 +
4710 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4711 +
4712 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4713 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4714 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4715 + return -1;
4716 + }
4717 + /* make sure only one bit is set */
4718 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4719 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4720 + return -1;
4721 + }
4722 +
4723 + /* already reserved */
4724 + if (sb_gpioreservation & gpio_bitmask)
4725 + return -1;
4726 + /* set reservation */
4727 + sb_gpioreservation |= gpio_bitmask;
4728 +
4729 + return sb_gpioreservation;
4730 +}
4731 +
4732 +/* release one gpio */
4733 +/*
4734 + * releasing the gpio doesn't change the current value on the GPIO last write value
4735 + * persists till some one overwrites it
4736 +*/
4737 +
4738 +uint32
4739 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4740 +{
4741 + sb_info_t *si;
4742 +
4743 + si = SB_INFO(sbh);
4744 +
4745 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4746 +
4747 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4748 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4749 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4750 + return -1;
4751 + }
4752 + /* make sure only one bit is set */
4753 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4754 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4755 + return -1;
4756 + }
4757 +
4758 + /* already released */
4759 + if (!(sb_gpioreservation & gpio_bitmask))
4760 + return -1;
4761 +
4762 + /* clear reservation */
4763 + sb_gpioreservation &= ~gpio_bitmask;
4764 +
4765 + return sb_gpioreservation;
4766 +}
4767 +
4768 +/* return the current gpioin register value */
4769 +uint32
4770 +sb_gpioin(sb_t *sbh)
4771 +{
4772 + sb_info_t *si;
4773 + uint regoff;
4774 +
4775 + si = SB_INFO(sbh);
4776 + regoff = 0;
4777 +
4778 + switch (si->gpioid) {
4779 + case SB_CC:
4780 + regoff = OFFSETOF(chipcregs_t, gpioin);
4781 + break;
4782 +
4783 + case SB_PCI:
4784 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4785 + break;
4786 +
4787 + case SB_EXTIF:
4788 + regoff = OFFSETOF(extifregs_t, gpioin);
4789 + break;
4790 + }
4791 +
4792 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4793 +}
4794 +
4795 +/* mask&set gpio interrupt polarity bits */
4796 +uint32
4797 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4798 +{
4799 + sb_info_t *si;
4800 + uint regoff;
4801 +
4802 + si = SB_INFO(sbh);
4803 + regoff = 0;
4804 +
4805 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4806 +
4807 + /* gpios could be shared on router platforms */
4808 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4809 + mask = priority ? (sb_gpioreservation & mask) :
4810 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4811 + val &= mask;
4812 + }
4813 +
4814 + switch (si->gpioid) {
4815 + case SB_CC:
4816 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4817 + break;
4818 +
4819 + case SB_PCI:
4820 + /* pci gpio implementation does not support interrupt polarity */
4821 + ASSERT(0);
4822 + break;
4823 +
4824 + case SB_EXTIF:
4825 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4826 + break;
4827 + }
4828 +
4829 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4830 +}
4831 +
4832 +/* mask&set gpio interrupt mask bits */
4833 +uint32
4834 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4835 +{
4836 + sb_info_t *si;
4837 + uint regoff;
4838 +
4839 + si = SB_INFO(sbh);
4840 + regoff = 0;
4841 +
4842 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4843 +
4844 + /* gpios could be shared on router platforms */
4845 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4846 + mask = priority ? (sb_gpioreservation & mask) :
4847 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4848 + val &= mask;
4849 + }
4850 +
4851 + switch (si->gpioid) {
4852 + case SB_CC:
4853 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4854 + break;
4855 +
4856 + case SB_PCI:
4857 + /* pci gpio implementation does not support interrupt mask */
4858 + ASSERT(0);
4859 + break;
4860 +
4861 + case SB_EXTIF:
4862 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4863 + break;
4864 + }
4865 +
4866 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4867 +}
4868 +
4869 +/* assign the gpio to an led */
4870 +uint32
4871 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4872 +{
4873 + sb_info_t *si;
4874 +
4875 + si = SB_INFO(sbh);
4876 + if (si->sb.ccrev < 16)
4877 + return -1;
4878 +
4879 + /* gpio led powersave reg */
4880 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4881 +}
4882 +
4883 +/* mask&set gpio timer val */
4884 +uint32
4885 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4886 +{
4887 + sb_info_t *si;
4888 + si = SB_INFO(sbh);
4889 +
4890 + if (si->sb.ccrev < 16)
4891 + return -1;
4892 +
4893 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4894 +}
4895 +
4896 +
4897 +/* return the slow clock source - LPO, XTAL, or PCI */
4898 +static uint
4899 +sb_slowclk_src(sb_info_t *si)
4900 +{
4901 + chipcregs_t *cc;
4902 +
4903 +
4904 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4905 +
4906 + if (si->sb.ccrev < 6) {
4907 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4908 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4909 + return (SCC_SS_PCI);
4910 + else
4911 + return (SCC_SS_XTAL);
4912 + } else if (si->sb.ccrev < 10) {
4913 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4914 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4915 + } else /* Insta-clock */
4916 + return (SCC_SS_XTAL);
4917 +}
4918 +
4919 +/* return the ILP (slowclock) min or max frequency */
4920 +static uint
4921 +sb_slowclk_freq(sb_info_t *si, bool max)
4922 +{
4923 + chipcregs_t *cc;
4924 + uint32 slowclk;
4925 + uint div;
4926 +
4927 +
4928 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4929 +
4930 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4931 +
4932 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4933 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4934 +
4935 + slowclk = sb_slowclk_src(si);
4936 + if (si->sb.ccrev < 6) {
4937 + if (slowclk == SCC_SS_PCI)
4938 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4939 + else
4940 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4941 + } else if (si->sb.ccrev < 10) {
4942 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4943 + if (slowclk == SCC_SS_LPO)
4944 + return (max? LPOMAXFREQ : LPOMINFREQ);
4945 + else if (slowclk == SCC_SS_XTAL)
4946 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4947 + else if (slowclk == SCC_SS_PCI)
4948 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4949 + else
4950 + ASSERT(0);
4951 + } else {
4952 + /* Chipc rev 10 is InstaClock */
4953 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4954 + div = 4 * (div + 1);
4955 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4956 + }
4957 + return (0);
4958 +}
4959 +
4960 +static void
4961 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4962 +{
4963 + chipcregs_t * cc;
4964 + uint slowmaxfreq, pll_delay, slowclk;
4965 + uint pll_on_delay, fref_sel_delay;
4966 +
4967 + pll_delay = PLL_DELAY;
4968 +
4969 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4970 + * since the xtal will also be powered down by dynamic clk control logic.
4971 + */
4972 + slowclk = sb_slowclk_src(si);
4973 + if (slowclk != SCC_SS_XTAL)
4974 + pll_delay += XTAL_ON_DELAY;
4975 +
4976 + /* Starting with 4318 it is ILP that is used for the delays */
4977 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4978 +
4979 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4980 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4981 +
4982 + cc = (chipcregs_t *)chipcregs;
4983 + W_REG(&cc->pll_on_delay, pll_on_delay);
4984 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4985 +}
4986 +
4987 +int
4988 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4989 +{
4990 + sb_info_t *si;
4991 + uint origidx;
4992 + chipcregs_t *cc;
4993 + uint intr_val = 0;
4994 + uint err = 0;
4995 +
4996 + si = SB_INFO(sbh);
4997 +
4998 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4999 + if (si->sb.ccrev < 6)
5000 + return 1;
5001 +
5002 + /* chipcommon cores rev10 are a whole new ball game */
5003 + if (si->sb.ccrev >= 10)
5004 + return 1;
5005 +
5006 + if (set && ((*div % 4) || (*div < 4)))
5007 + return 2;
5008 +
5009 + INTR_OFF(si, intr_val);
5010 + origidx = si->curidx;
5011 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5012 + ASSERT(cc != NULL);
5013 +
5014 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
5015 + err = 3;
5016 + goto done;
5017 + }
5018 +
5019 + if (set) {
5020 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
5021 + sb_clkctl_setdelay(sbh, (void *)cc);
5022 + } else
5023 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
5024 +
5025 +done:
5026 + sb_setcoreidx(sbh, origidx);
5027 + INTR_RESTORE(si, intr_val);
5028 + return err;
5029 +}
5030 +
5031 +/* initialize power control delay registers */
5032 +void sb_clkctl_init(sb_t *sbh)
5033 +{
5034 + sb_info_t *si;
5035 + uint origidx;
5036 + chipcregs_t *cc;
5037 +
5038 + si = SB_INFO(sbh);
5039 +
5040 + origidx = si->curidx;
5041 +
5042 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5043 + return;
5044 +
5045 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5046 + goto done;
5047 +
5048 + /* set all Instaclk chip ILP to 1 MHz */
5049 + if (si->sb.ccrev >= 10)
5050 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5051 +
5052 + sb_clkctl_setdelay(si, (void *)cc);
5053 +
5054 +done:
5055 + sb_setcoreidx(sbh, origidx);
5056 +}
5057 +void sb_pwrctl_init(sb_t *sbh)
5058 +{
5059 +sb_clkctl_init(sbh);
5060 +}
5061 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5062 +uint16
5063 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5064 +{
5065 + sb_info_t *si;
5066 + uint origidx;
5067 + chipcregs_t *cc;
5068 + uint slowminfreq;
5069 + uint16 fpdelay;
5070 + uint intr_val = 0;
5071 +
5072 + si = SB_INFO(sbh);
5073 + fpdelay = 0;
5074 + origidx = si->curidx;
5075 +
5076 + INTR_OFF(si, intr_val);
5077 +
5078 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5079 + goto done;
5080 +
5081 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5082 + goto done;
5083 +
5084 + slowminfreq = sb_slowclk_freq(si, FALSE);
5085 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5086 +
5087 +done:
5088 + sb_setcoreidx(sbh, origidx);
5089 + INTR_RESTORE(si, intr_val);
5090 + return (fpdelay);
5091 +}
5092 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5093 +{
5094 +return sb_clkctl_fast_pwrup_delay(sbh);
5095 +}
5096 +/* turn primary xtal and/or pll off/on */
5097 +int
5098 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5099 +{
5100 + sb_info_t *si;
5101 + uint32 in, out, outen;
5102 +
5103 + si = SB_INFO(sbh);
5104 +
5105 + switch (BUSTYPE(si->sb.bustype)) {
5106 + case PCI_BUS:
5107 +
5108 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5109 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5110 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5111 +
5112 + /*
5113 + * Avoid glitching the clock if GPRS is already using it.
5114 + * We can't actually read the state of the PLLPD so we infer it
5115 + * by the value of XTAL_PU which *is* readable via gpioin.
5116 + */
5117 + if (on && (in & PCI_CFG_GPIO_XTAL))
5118 + return (0);
5119 +
5120 + if (what & XTAL)
5121 + outen |= PCI_CFG_GPIO_XTAL;
5122 + if (what & PLL)
5123 + outen |= PCI_CFG_GPIO_PLL;
5124 +
5125 + if (on) {
5126 + /* turn primary xtal on */
5127 + if (what & XTAL) {
5128 + out |= PCI_CFG_GPIO_XTAL;
5129 + if (what & PLL)
5130 + out |= PCI_CFG_GPIO_PLL;
5131 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5132 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5133 + OSL_DELAY(XTAL_ON_DELAY);
5134 + }
5135 +
5136 + /* turn pll on */
5137 + if (what & PLL) {
5138 + out &= ~PCI_CFG_GPIO_PLL;
5139 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5140 + OSL_DELAY(2000);
5141 + }
5142 + } else {
5143 + if (what & XTAL)
5144 + out &= ~PCI_CFG_GPIO_XTAL;
5145 + if (what & PLL)
5146 + out |= PCI_CFG_GPIO_PLL;
5147 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5148 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5149 + }
5150 +
5151 + default:
5152 + return (-1);
5153 + }
5154 +
5155 + return (0);
5156 +}
5157 +
5158 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5159 +{
5160 +return sb_clkctl_xtal(sbh,what,on);
5161 +}
5162 +
5163 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5164 +/* returns true if ignore pll off is set and false if it is not */
5165 +bool
5166 +sb_clkctl_clk(sb_t *sbh, uint mode)
5167 +{
5168 + sb_info_t *si;
5169 + uint origidx;
5170 + chipcregs_t *cc;
5171 + uint32 scc;
5172 + bool forcefastclk=FALSE;
5173 + uint intr_val = 0;
5174 +
5175 + si = SB_INFO(sbh);
5176 +
5177 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5178 + if (si->sb.ccrev < 6)
5179 + return (FALSE);
5180 +
5181 + /* chipcommon cores rev10 are a whole new ball game */
5182 + if (si->sb.ccrev >= 10)
5183 + return (FALSE);
5184 +
5185 + INTR_OFF(si, intr_val);
5186 +
5187 + origidx = si->curidx;
5188 +
5189 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5190 + ASSERT(cc != NULL);
5191 +
5192 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5193 + goto done;
5194 +
5195 + switch (mode) {
5196 + case CLK_FAST: /* force fast (pll) clock */
5197 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5198 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5199 +
5200 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5201 + break;
5202 +
5203 + case CLK_DYNAMIC: /* enable dynamic clock control */
5204 + scc = R_REG(&cc->slow_clk_ctl);
5205 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5206 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5207 + scc |= SCC_XC;
5208 + W_REG(&cc->slow_clk_ctl, scc);
5209 +
5210 + /* for dynamic control, we have to release our xtal_pu "force on" */
5211 + if (scc & SCC_XC)
5212 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5213 + break;
5214 +
5215 + default:
5216 + ASSERT(0);
5217 + }
5218 +
5219 + /* Is the h/w forcing the use of the fast clk */
5220 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5221 +
5222 +done:
5223 + sb_setcoreidx(sbh, origidx);
5224 + INTR_RESTORE(si, intr_val);
5225 + return (forcefastclk);
5226 +}
5227 +
5228 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5229 +{
5230 +return sb_clkctl_clk(sbh, mode);
5231 +}
5232 +/* register driver interrupt disabling and restoring callback functions */
5233 +void
5234 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5235 +{
5236 + sb_info_t *si;
5237 +
5238 + si = SB_INFO(sbh);
5239 + si->intr_arg = intr_arg;
5240 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5241 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5242 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5243 + /* save current core id. when this function called, the current core
5244 + * must be the core which provides driver functions(il, et, wl, etc.)
5245 + */
5246 + si->dev_coreid = si->coreid[si->curidx];
5247 +}
5248 +
5249 +
5250 +void
5251 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5252 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5253 +{
5254 + uint vendor, core, unit;
5255 + uint chip, chippkg;
5256 + char varname[8];
5257 + uint8 class, subclass, progif;
5258 +
5259 + vendor = sb_corevendor(sbh);
5260 + core = sb_coreid(sbh);
5261 + unit = sb_coreunit(sbh);
5262 +
5263 + chip = BCMINIT(sb_chip)(sbh);
5264 + chippkg = BCMINIT(sb_chippkg)(sbh);
5265 +
5266 + progif = 0;
5267 +
5268 + /* Known vendor translations */
5269 + switch (vendor) {
5270 + case SB_VEND_BCM:
5271 + vendor = VENDOR_BROADCOM;
5272 + break;
5273 + }
5274 +
5275 + /* Determine class based on known core codes */
5276 + switch (core) {
5277 + case SB_ILINE20:
5278 + class = PCI_CLASS_NET;
5279 + subclass = PCI_NET_ETHER;
5280 + core = BCM47XX_ILINE_ID;
5281 + break;
5282 + case SB_ENET:
5283 + class = PCI_CLASS_NET;
5284 + subclass = PCI_NET_ETHER;
5285 + core = BCM47XX_ENET_ID;
5286 + break;
5287 + case SB_SDRAM:
5288 + case SB_MEMC:
5289 + class = PCI_CLASS_MEMORY;
5290 + subclass = PCI_MEMORY_RAM;
5291 + break;
5292 + case SB_PCI:
5293 + class = PCI_CLASS_BRIDGE;
5294 + subclass = PCI_BRIDGE_PCI;
5295 + break;
5296 + case SB_MIPS:
5297 + case SB_MIPS33:
5298 + class = PCI_CLASS_CPU;
5299 + subclass = PCI_CPU_MIPS;
5300 + break;
5301 + case SB_CODEC:
5302 + class = PCI_CLASS_COMM;
5303 + subclass = PCI_COMM_MODEM;
5304 + core = BCM47XX_V90_ID;
5305 + break;
5306 + case SB_USB:
5307 + class = PCI_CLASS_SERIAL;
5308 + subclass = PCI_SERIAL_USB;
5309 + progif = 0x10; /* OHCI */
5310 + core = BCM47XX_USB_ID;
5311 + break;
5312 + case SB_USB11H:
5313 + class = PCI_CLASS_SERIAL;
5314 + subclass = PCI_SERIAL_USB;
5315 + progif = 0x10; /* OHCI */
5316 + core = BCM47XX_USBH_ID;
5317 + break;
5318 + case SB_USB11D:
5319 + class = PCI_CLASS_SERIAL;
5320 + subclass = PCI_SERIAL_USB;
5321 + core = BCM47XX_USBD_ID;
5322 + break;
5323 + case SB_IPSEC:
5324 + class = PCI_CLASS_CRYPT;
5325 + subclass = PCI_CRYPT_NETWORK;
5326 + core = BCM47XX_IPSEC_ID;
5327 + break;
5328 + case SB_ROBO:
5329 + class = PCI_CLASS_NET;
5330 + subclass = PCI_NET_OTHER;
5331 + core = BCM47XX_ROBO_ID;
5332 + break;
5333 + case SB_EXTIF:
5334 + case SB_CC:
5335 + class = PCI_CLASS_MEMORY;
5336 + subclass = PCI_MEMORY_FLASH;
5337 + break;
5338 + case SB_D11:
5339 + class = PCI_CLASS_NET;
5340 + subclass = PCI_NET_OTHER;
5341 + /* Let an nvram variable override this */
5342 + sprintf(varname, "wl%did", unit);
5343 + if ((core = getintvar(NULL, varname)) == 0) {
5344 + if (chip == BCM4712_DEVICE_ID) {
5345 + if (chippkg == BCM4712SMALL_PKG_ID)
5346 + core = BCM4306_D11G_ID;
5347 + else
5348 + core = BCM4306_D11DUAL_ID;
5349 + }
5350 + }
5351 + break;
5352 +
5353 + default:
5354 + class = subclass = progif = 0xff;
5355 + break;
5356 + }
5357 +
5358 + *pcivendor = (uint16)vendor;
5359 + *pcidevice = (uint16)core;
5360 + *pciclass = class;
5361 + *pcisubclass = subclass;
5362 + *pciprogif = progif;
5363 +}
5364 +
5365 +/* Fix chip's configuration. The current core may be changed upon return */
5366 +static int
5367 +sb_pci_fixcfg(sb_info_t *si)
5368 +{
5369 + uint origidx, pciidx;
5370 + sbpciregs_t *pciregs;
5371 + uint16 val16, *reg16;
5372 +
5373 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5374 +
5375 + /* Fix PCI(e) SROM shadow area */
5376 + /* save the current index */
5377 + origidx = sb_coreidx(&si->sb);
5378 +
5379 + if (si->sb.buscoretype == SB_PCI) {
5380 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5381 + ASSERT(pciregs);
5382 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5383 + }
5384 + else {
5385 + ASSERT(0);
5386 + return -1;
5387 + }
5388 + pciidx = sb_coreidx(&si->sb);
5389 + val16 = R_REG(reg16);
5390 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5391 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5392 + W_REG(reg16, val16);
5393 + }
5394 +
5395 + /* restore the original index */
5396 + sb_setcoreidx(&si->sb, origidx);
5397 +
5398 + return 0;
5399 +}
5400 +
5401 +EXPORT_SYMBOL(sb_boardtype);
5402 +EXPORT_SYMBOL(sb_boardvendor);
5403 +EXPORT_SYMBOL(sb_gpiocontrol);
5404 +EXPORT_SYMBOL(sb_gpioin);
5405 +EXPORT_SYMBOL(sb_gpiointmask);
5406 +EXPORT_SYMBOL(sb_gpiointpolarity);
5407 +EXPORT_SYMBOL(sb_gpioled);
5408 +EXPORT_SYMBOL(sb_gpioout);
5409 +EXPORT_SYMBOL(sb_gpioouten);
5410 +EXPORT_SYMBOL(sb_gpiorelease);
5411 +EXPORT_SYMBOL(sb_gpioreserve);
5412 +EXPORT_SYMBOL(sb_gpiosetcore);
5413 +EXPORT_SYMBOL(sb_gpiotimerval);
5414 +EXPORT_SYMBOL(sb_watchdog);
5415 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5416 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5417 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2006-01-12 00:20:30.725131750 +0100
5418 @@ -0,0 +1,418 @@
5419 +/*
5420 + * Broadcom SiliconBackplane chipcommon serial flash interface
5421 + *
5422 + * Copyright 2005, Broadcom Corporation
5423 + * All Rights Reserved.
5424 + *
5425 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5426 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5427 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5428 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5429 + *
5430 + * $Id$
5431 + */
5432 +
5433 +#include <osl.h>
5434 +#include <typedefs.h>
5435 +#include <sbconfig.h>
5436 +#include <sbchipc.h>
5437 +#include <mipsinc.h>
5438 +#include <bcmutils.h>
5439 +#include <bcmdevs.h>
5440 +#include <sflash.h>
5441 +
5442 +/* Private global state */
5443 +static struct sflash sflash;
5444 +
5445 +/* Issue a serial flash command */
5446 +static INLINE void
5447 +sflash_cmd(chipcregs_t *cc, uint opcode)
5448 +{
5449 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5450 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5451 +}
5452 +
5453 +/* Initialize serial flash access */
5454 +struct sflash *
5455 +sflash_init(chipcregs_t *cc)
5456 +{
5457 + uint32 id, id2;
5458 +
5459 + bzero(&sflash, sizeof(sflash));
5460 +
5461 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5462 +
5463 + switch (sflash.type) {
5464 + case SFLASH_ST:
5465 + /* Probe for ST chips */
5466 + sflash_cmd(cc, SFLASH_ST_DP);
5467 + sflash_cmd(cc, SFLASH_ST_RES);
5468 + id = R_REG(&cc->flashdata);
5469 + switch (id) {
5470 + case 0x11:
5471 + /* ST M25P20 2 Mbit Serial Flash */
5472 + sflash.blocksize = 64 * 1024;
5473 + sflash.numblocks = 4;
5474 + break;
5475 + case 0x12:
5476 + /* ST M25P40 4 Mbit Serial Flash */
5477 + sflash.blocksize = 64 * 1024;
5478 + sflash.numblocks = 8;
5479 + break;
5480 + case 0x13:
5481 + /* ST M25P80 8 Mbit Serial Flash */
5482 + sflash.blocksize = 64 * 1024;
5483 + sflash.numblocks = 16;
5484 + break;
5485 + case 0x14:
5486 + /* ST M25P16 16 Mbit Serial Flash */
5487 + sflash.blocksize = 64 * 1024;
5488 + sflash.numblocks = 32;
5489 + break;
5490 + case 0x15:
5491 + /* ST M25P32 32 Mbit Serial Flash */
5492 + sflash.blocksize = 64 * 1024;
5493 + sflash.numblocks = 64;
5494 + break;
5495 + case 0xbf:
5496 + W_REG(&cc->flashaddress, 1);
5497 + sflash_cmd(cc, SFLASH_ST_RES);
5498 + id2 = R_REG(&cc->flashdata);
5499 + if (id2 == 0x44) {
5500 + /* SST M25VF80 4 Mbit Serial Flash */
5501 + sflash.blocksize = 64 * 1024;
5502 + sflash.numblocks = 8;
5503 + }
5504 + break;
5505 + }
5506 + break;
5507 +
5508 + case SFLASH_AT:
5509 + /* Probe for Atmel chips */
5510 + sflash_cmd(cc, SFLASH_AT_STATUS);
5511 + id = R_REG(&cc->flashdata) & 0x3c;
5512 + switch (id) {
5513 + case 0xc:
5514 + /* Atmel AT45DB011 1Mbit Serial Flash */
5515 + sflash.blocksize = 256;
5516 + sflash.numblocks = 512;
5517 + break;
5518 + case 0x14:
5519 + /* Atmel AT45DB021 2Mbit Serial Flash */
5520 + sflash.blocksize = 256;
5521 + sflash.numblocks = 1024;
5522 + break;
5523 + case 0x1c:
5524 + /* Atmel AT45DB041 4Mbit Serial Flash */
5525 + sflash.blocksize = 256;
5526 + sflash.numblocks = 2048;
5527 + break;
5528 + case 0x24:
5529 + /* Atmel AT45DB081 8Mbit Serial Flash */
5530 + sflash.blocksize = 256;
5531 + sflash.numblocks = 4096;
5532 + break;
5533 + case 0x2c:
5534 + /* Atmel AT45DB161 16Mbit Serial Flash */
5535 + sflash.blocksize = 512;
5536 + sflash.numblocks = 4096;
5537 + break;
5538 + case 0x34:
5539 + /* Atmel AT45DB321 32Mbit Serial Flash */
5540 + sflash.blocksize = 512;
5541 + sflash.numblocks = 8192;
5542 + break;
5543 + case 0x3c:
5544 + /* Atmel AT45DB642 64Mbit Serial Flash */
5545 + sflash.blocksize = 1024;
5546 + sflash.numblocks = 8192;
5547 + break;
5548 + }
5549 + break;
5550 + }
5551 +
5552 + sflash.size = sflash.blocksize * sflash.numblocks;
5553 + return sflash.size ? &sflash : NULL;
5554 +}
5555 +
5556 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5557 +int
5558 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5559 +{
5560 + int cnt;
5561 + uint32 *from, *to;
5562 +
5563 + if (!len)
5564 + return 0;
5565 +
5566 + if ((offset + len) > sflash.size)
5567 + return -22;
5568 +
5569 + if ((len >= 4) && (offset & 3))
5570 + cnt = 4 - (offset & 3);
5571 + else if ((len >= 4) && ((uint32)buf & 3))
5572 + cnt = 4 - ((uint32)buf & 3);
5573 + else
5574 + cnt = len;
5575 +
5576 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5577 + to = (uint32 *)buf;
5578 +
5579 + if (cnt < 4) {
5580 + bcopy(from, to, cnt);
5581 + return cnt;
5582 + }
5583 +
5584 + while (cnt >= 4) {
5585 + *to++ = *from++;
5586 + cnt -= 4;
5587 + }
5588 +
5589 + return (len - cnt);
5590 +}
5591 +
5592 +/* Poll for command completion. Returns zero when complete. */
5593 +int
5594 +sflash_poll(chipcregs_t *cc, uint offset)
5595 +{
5596 + if (offset >= sflash.size)
5597 + return -22;
5598 +
5599 + switch (sflash.type) {
5600 + case SFLASH_ST:
5601 + /* Check for ST Write In Progress bit */
5602 + sflash_cmd(cc, SFLASH_ST_RDSR);
5603 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5604 + case SFLASH_AT:
5605 + /* Check for Atmel Ready bit */
5606 + sflash_cmd(cc, SFLASH_AT_STATUS);
5607 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5608 + }
5609 +
5610 + return 0;
5611 +}
5612 +
5613 +/* Write len bytes starting at offset into buf. Returns number of bytes
5614 + * written. Caller should poll for completion.
5615 + */
5616 +int
5617 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5618 +{
5619 + struct sflash *sfl;
5620 + int ret = 0;
5621 + bool is4712b0;
5622 + uint32 page, byte, mask;
5623 +
5624 + if (!len)
5625 + return 0;
5626 +
5627 + if ((offset + len) > sflash.size)
5628 + return -22;
5629 +
5630 + sfl = &sflash;
5631 + switch (sfl->type) {
5632 + case SFLASH_ST:
5633 + mask = R_REG(&cc->chipid);
5634 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5635 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5636 + /* Enable writes */
5637 + sflash_cmd(cc, SFLASH_ST_WREN);
5638 + if (is4712b0) {
5639 + mask = 1 << 14;
5640 + W_REG(&cc->flashaddress, offset);
5641 + W_REG(&cc->flashdata, *buf++);
5642 + /* Set chip select */
5643 + OR_REG(&cc->gpioout, mask);
5644 + /* Issue a page program with the first byte */
5645 + sflash_cmd(cc, SFLASH_ST_PP);
5646 + ret = 1;
5647 + offset++;
5648 + len--;
5649 + while (len > 0) {
5650 + if ((offset & 255) == 0) {
5651 + /* Page boundary, drop cs and return */
5652 + AND_REG(&cc->gpioout, ~mask);
5653 + if (!sflash_poll(cc, offset)) {
5654 + /* Flash rejected command */
5655 + return -11;
5656 + }
5657 + return ret;
5658 + } else {
5659 + /* Write single byte */
5660 + sflash_cmd(cc, *buf++);
5661 + }
5662 + ret++;
5663 + offset++;
5664 + len--;
5665 + }
5666 + /* All done, drop cs if needed */
5667 + if ((offset & 255) != 1) {
5668 + /* Drop cs */
5669 + AND_REG(&cc->gpioout, ~mask);
5670 + if (!sflash_poll(cc, offset)) {
5671 + /* Flash rejected command */
5672 + return -12;
5673 + }
5674 + }
5675 + } else {
5676 + ret = 1;
5677 + W_REG(&cc->flashaddress, offset);
5678 + W_REG(&cc->flashdata, *buf);
5679 + /* Page program */
5680 + sflash_cmd(cc, SFLASH_ST_PP);
5681 + }
5682 + break;
5683 + case SFLASH_AT:
5684 + mask = sfl->blocksize - 1;
5685 + page = (offset & ~mask) << 1;
5686 + byte = offset & mask;
5687 + /* Read main memory page into buffer 1 */
5688 + if (byte || len < sfl->blocksize) {
5689 + W_REG(&cc->flashaddress, page);
5690 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5691 + /* 250 us for AT45DB321B */
5692 + SPINWAIT(sflash_poll(cc, offset), 1000);
5693 + ASSERT(!sflash_poll(cc, offset));
5694 + }
5695 + /* Write into buffer 1 */
5696 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5697 + W_REG(&cc->flashaddress, byte++);
5698 + W_REG(&cc->flashdata, *buf++);
5699 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5700 + }
5701 + /* Write buffer 1 into main memory page */
5702 + W_REG(&cc->flashaddress, page);
5703 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5704 + break;
5705 + }
5706 +
5707 + return ret;
5708 +}
5709 +
5710 +/* Erase a region. Returns number of bytes scheduled for erasure.
5711 + * Caller should poll for completion.
5712 + */
5713 +int
5714 +sflash_erase(chipcregs_t *cc, uint offset)
5715 +{
5716 + struct sflash *sfl;
5717 +
5718 + if (offset >= sflash.size)
5719 + return -22;
5720 +
5721 + sfl = &sflash;
5722 + switch (sfl->type) {
5723 + case SFLASH_ST:
5724 + sflash_cmd(cc, SFLASH_ST_WREN);
5725 + W_REG(&cc->flashaddress, offset);
5726 + sflash_cmd(cc, SFLASH_ST_SE);
5727 + return sfl->blocksize;
5728 + case SFLASH_AT:
5729 + W_REG(&cc->flashaddress, offset << 1);
5730 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5731 + return sfl->blocksize;
5732 + }
5733 +
5734 + return 0;
5735 +}
5736 +
5737 +/*
5738 + * writes the appropriate range of flash, a NULL buf simply erases
5739 + * the region of flash
5740 + */
5741 +int
5742 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5743 +{
5744 + struct sflash *sfl;
5745 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5746 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5747 + uint blk_offset, blk_len, copied;
5748 + int bytes, ret = 0;
5749 +
5750 + /* Check address range */
5751 + if (len <= 0)
5752 + return 0;
5753 +
5754 + sfl = &sflash;
5755 + if ((offset + len) > sfl->size)
5756 + return -1;
5757 +
5758 + blocksize = sfl->blocksize;
5759 + mask = blocksize - 1;
5760 +
5761 + /* Allocate a block of mem */
5762 + if (!(block = MALLOC(NULL, blocksize)))
5763 + return -1;
5764 +
5765 + while (len) {
5766 + /* Align offset */
5767 + cur_offset = offset & ~mask;
5768 + cur_length = blocksize;
5769 + cur_ptr = block;
5770 +
5771 + remainder = blocksize - (offset & mask);
5772 + if (len < remainder)
5773 + cur_retlen = len;
5774 + else
5775 + cur_retlen = remainder;
5776 +
5777 + /* buf == NULL means erase only */
5778 + if (buf) {
5779 + /* Copy existing data into holding block if necessary */
5780 + if ((offset & mask) || (len < blocksize)) {
5781 + blk_offset = cur_offset;
5782 + blk_len = cur_length;
5783 + blk_ptr = cur_ptr;
5784 +
5785 + /* Copy entire block */
5786 + while(blk_len) {
5787 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5788 + blk_offset += copied;
5789 + blk_len -= copied;
5790 + blk_ptr += copied;
5791 + }
5792 + }
5793 +
5794 + /* Copy input data into holding block */
5795 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5796 + }
5797 +
5798 + /* Erase block */
5799 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5800 + goto done;
5801 + while (sflash_poll(cc, (uint) cur_offset));
5802 +
5803 + /* buf == NULL means erase only */
5804 + if (!buf) {
5805 + offset += cur_retlen;
5806 + len -= cur_retlen;
5807 + continue;
5808 + }
5809 +
5810 + /* Write holding block */
5811 + while (cur_length > 0) {
5812 + if ((bytes = sflash_write(cc,
5813 + (uint) cur_offset,
5814 + (uint) cur_length,
5815 + (uchar *) cur_ptr)) < 0) {
5816 + ret = bytes;
5817 + goto done;
5818 + }
5819 + while (sflash_poll(cc, (uint) cur_offset));
5820 + cur_offset += bytes;
5821 + cur_length -= bytes;
5822 + cur_ptr += bytes;
5823 + }
5824 +
5825 + offset += cur_retlen;
5826 + len -= cur_retlen;
5827 + buf += cur_retlen;
5828 + }
5829 +
5830 + ret = len;
5831 +done:
5832 + if (block)
5833 + MFREE(NULL, block, blocksize);
5834 + return ret;
5835 +}
5836 +
5837 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5838 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5839 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-01-12 00:20:30.725131750 +0100
5840 @@ -0,0 +1,391 @@
5841 +/*
5842 + * Broadcom device-specific manifest constants.
5843 + *
5844 + * Copyright 2005, Broadcom Corporation
5845 + * All Rights Reserved.
5846 + *
5847 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5848 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5849 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5850 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5851 + * $Id$
5852 + */
5853 +
5854 +#ifndef _BCMDEVS_H
5855 +#define _BCMDEVS_H
5856 +
5857 +
5858 +/* Known PCI vendor Id's */
5859 +#define VENDOR_EPIGRAM 0xfeda
5860 +#define VENDOR_BROADCOM 0x14e4
5861 +#define VENDOR_3COM 0x10b7
5862 +#define VENDOR_NETGEAR 0x1385
5863 +#define VENDOR_DIAMOND 0x1092
5864 +#define VENDOR_DELL 0x1028
5865 +#define VENDOR_HP 0x0e11
5866 +#define VENDOR_APPLE 0x106b
5867 +
5868 +/* PCI Device Id's */
5869 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5870 +#define BCM4211_DEVICE_ID 0x4211
5871 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5872 +#define BCM4231_DEVICE_ID 0x4231
5873 +
5874 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5875 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5876 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5877 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5878 +
5879 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5880 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5881 +
5882 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5883 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5884 +
5885 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5886 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5887 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5888 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5889 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5890 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5891 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5892 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5893 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5894 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5895 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5896 +
5897 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5898 +
5899 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5900 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5901 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5902 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5903 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5904 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5905 +
5906 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5907 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5908 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5909 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5910 +
5911 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5912 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5913 +
5914 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5915 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5916 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5917 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5918 +
5919 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5920 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5921 +#define BCM4306_D11G_ID2 0x4325
5922 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5923 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5924 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5925 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5926 +
5927 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5928 +
5929 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5930 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5931 +
5932 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5933 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5934 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5935 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5936 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5937 +
5938 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5939 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5940 +
5941 +
5942 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5943 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5944 +
5945 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5946 +
5947 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5948 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5949 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5950 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5951 +
5952 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5953 +
5954 +/* Address map */
5955 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5956 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5957 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5958 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5959 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5960 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5961 +
5962 +/* Core register space */
5963 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5964 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5965 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5966 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5967 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5968 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5969 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5970 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5971 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5972 +
5973 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5974 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5975 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5976 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5977 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5978 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5979 +
5980 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5981 +
5982 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5983 +
5984 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5985 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5986 +
5987 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5988 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5989 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5990 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5991 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5992 +
5993 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5994 +
5995 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5996 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5997 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5998 +
5999 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
6000 +
6001 +/* PCMCIA vendor Id's */
6002 +
6003 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
6004 +
6005 +/* SDIO vendor Id's */
6006 +#define VENDOR_BROADCOM_SDIO 0x00BF
6007 +
6008 +
6009 +/* boardflags */
6010 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
6011 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
6012 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
6013 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
6014 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
6015 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
6016 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
6017 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
6018 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
6019 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
6020 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
6021 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
6022 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
6023 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
6024 +
6025 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6026 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6027 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
6028 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
6029 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6030 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6031 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6032 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6033 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6034 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6035 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6036 +
6037 +/* Bus types */
6038 +#define SB_BUS 0 /* Silicon Backplane */
6039 +#define PCI_BUS 1 /* PCI target */
6040 +#define PCMCIA_BUS 2 /* PCMCIA target */
6041 +#define SDIO_BUS 3 /* SDIO target */
6042 +#define JTAG_BUS 4 /* JTAG */
6043 +
6044 +/* Allows optimization for single-bus support */
6045 +#ifdef BCMBUSTYPE
6046 +#define BUSTYPE(bus) (BCMBUSTYPE)
6047 +#else
6048 +#define BUSTYPE(bus) (bus)
6049 +#endif
6050 +
6051 +/* power control defines */
6052 +#define PLL_DELAY 150 /* us pll on delay */
6053 +#define FREF_DELAY 200 /* us fref change delay */
6054 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6055 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6056 +
6057 +/* Reference Board Types */
6058 +
6059 +#define BU4710_BOARD 0x0400
6060 +#define VSIM4710_BOARD 0x0401
6061 +#define QT4710_BOARD 0x0402
6062 +
6063 +#define BU4610_BOARD 0x0403
6064 +#define VSIM4610_BOARD 0x0404
6065 +
6066 +#define BU4307_BOARD 0x0405
6067 +#define BCM94301CB_BOARD 0x0406
6068 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6069 +#define BCM94301MP_BOARD 0x0407
6070 +#define BCM94307MP_BOARD 0x0408
6071 +#define BCMAP4307_BOARD 0x0409
6072 +
6073 +#define BU4309_BOARD 0x040a
6074 +#define BCM94309CB_BOARD 0x040b
6075 +#define BCM94309MP_BOARD 0x040c
6076 +#define BCM4309AP_BOARD 0x040d
6077 +
6078 +#define BCM94302MP_BOARD 0x040e
6079 +
6080 +#define VSIM4310_BOARD 0x040f
6081 +#define BU4711_BOARD 0x0410
6082 +#define BCM94310U_BOARD 0x0411
6083 +#define BCM94310AP_BOARD 0x0412
6084 +#define BCM94310MP_BOARD 0x0414
6085 +
6086 +#define BU4306_BOARD 0x0416
6087 +#define BCM94306CB_BOARD 0x0417
6088 +#define BCM94306MP_BOARD 0x0418
6089 +
6090 +#define BCM94710D_BOARD 0x041a
6091 +#define BCM94710R1_BOARD 0x041b
6092 +#define BCM94710R4_BOARD 0x041c
6093 +#define BCM94710AP_BOARD 0x041d
6094 +
6095 +
6096 +#define BU2050_BOARD 0x041f
6097 +
6098 +
6099 +#define BCM94309G_BOARD 0x0421
6100 +
6101 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6102 +
6103 +#define BU4704_BOARD 0x0423
6104 +#define BU4702_BOARD 0x0424
6105 +
6106 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6107 +
6108 +#define BU4317_BOARD 0x0426
6109 +
6110 +
6111 +#define BCM94702MN_BOARD 0x0428
6112 +
6113 +/* BCM4702 1U CompactPCI Board */
6114 +#define BCM94702CPCI_BOARD 0x0429
6115 +
6116 +/* BCM4702 with BCM95380 VLAN Router */
6117 +#define BCM95380RR_BOARD 0x042a
6118 +
6119 +/* cb4306 with SiGe PA */
6120 +#define BCM94306CBSG_BOARD 0x042b
6121 +
6122 +/* mp4301 with 2050 radio */
6123 +#define BCM94301MPL_BOARD 0x042c
6124 +
6125 +/* cb4306 with SiGe PA */
6126 +#define PCSG94306_BOARD 0x042d
6127 +
6128 +/* bu4704 with sdram */
6129 +#define BU4704SD_BOARD 0x042e
6130 +
6131 +/* Dual 11a/11g Router */
6132 +#define BCM94704AGR_BOARD 0x042f
6133 +
6134 +/* 11a-only minipci */
6135 +#define BCM94308MP_BOARD 0x0430
6136 +
6137 +
6138 +
6139 +/* BCM94317 boards */
6140 +#define BCM94317CB_BOARD 0x0440
6141 +#define BCM94317MP_BOARD 0x0441
6142 +#define BCM94317PCMCIA_BOARD 0x0442
6143 +#define BCM94317SDIO_BOARD 0x0443
6144 +
6145 +#define BU4712_BOARD 0x0444
6146 +#define BU4712SD_BOARD 0x045d
6147 +#define BU4712L_BOARD 0x045f
6148 +
6149 +/* BCM4712 boards */
6150 +#define BCM94712AP_BOARD 0x0445
6151 +#define BCM94712P_BOARD 0x0446
6152 +
6153 +/* BCM4318 boards */
6154 +#define BU4318_BOARD 0x0447
6155 +#define CB4318_BOARD 0x0448
6156 +#define MPG4318_BOARD 0x0449
6157 +#define MP4318_BOARD 0x044a
6158 +#define SD4318_BOARD 0x044b
6159 +
6160 +/* BCM63XX boards */
6161 +#define BCM96338_BOARD 0x6338
6162 +#define BCM96345_BOARD 0x6345
6163 +#define BCM96348_BOARD 0x6348
6164 +
6165 +/* Another mp4306 with SiGe */
6166 +#define BCM94306P_BOARD 0x044c
6167 +
6168 +/* CF-like 4317 modules */
6169 +#define BCM94317CF_BOARD 0x044d
6170 +
6171 +/* mp4303 */
6172 +#define BCM94303MP_BOARD 0x044e
6173 +
6174 +/* mpsgh4306 */
6175 +#define BCM94306MPSGH_BOARD 0x044f
6176 +
6177 +/* BRCM 4306 w/ Front End Modules */
6178 +#define BCM94306MPM 0x0450
6179 +#define BCM94306MPL 0x0453
6180 +
6181 +/* 4712agr */
6182 +#define BCM94712AGR_BOARD 0x0451
6183 +
6184 +/* The real CF 4317 board */
6185 +#define CFI4317_BOARD 0x0452
6186 +
6187 +/* pcmcia 4303 */
6188 +#define PC4303_BOARD 0x0454
6189 +
6190 +/* 5350K */
6191 +#define BCM95350K_BOARD 0x0455
6192 +
6193 +/* 5350R */
6194 +#define BCM95350R_BOARD 0x0456
6195 +
6196 +/* 4306mplna */
6197 +#define BCM94306MPLNA_BOARD 0x0457
6198 +
6199 +/* 4320 boards */
6200 +#define BU4320_BOARD 0x0458
6201 +#define BU4320S_BOARD 0x0459
6202 +#define BCM94320PH_BOARD 0x045a
6203 +
6204 +/* 4306mph */
6205 +#define BCM94306MPH_BOARD 0x045b
6206 +
6207 +/* 4306pciv */
6208 +#define BCM94306PCIV_BOARD 0x045c
6209 +
6210 +#define BU4712SD_BOARD 0x045d
6211 +
6212 +#define BCM94320PFLSH_BOARD 0x045e
6213 +
6214 +#define BU4712L_BOARD 0x045f
6215 +#define BCM94712LGR_BOARD 0x0460
6216 +#define BCM94320R_BOARD 0x0461
6217 +
6218 +#define BU5352_BOARD 0x0462
6219 +
6220 +#define BCM94318MPGH_BOARD 0x0463
6221 +
6222 +
6223 +#define BCM95352GR_BOARD 0x0467
6224 +
6225 +/* bcm95351agr */
6226 +#define BCM95351AGR_BOARD 0x0470
6227 +
6228 +/* # of GPIO pins */
6229 +#define GPIO_NUMPINS 16
6230 +
6231 +#endif /* _BCMDEVS_H */
6232 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6233 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6234 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-01-12 00:20:30.725131750 +0100
6235 @@ -0,0 +1,152 @@
6236 +/*
6237 + * local version of endian.h - byte order defines
6238 + *
6239 + * Copyright 2005, Broadcom Corporation
6240 + * All Rights Reserved.
6241 + *
6242 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6243 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6244 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6245 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6246 + *
6247 + * $Id$
6248 +*/
6249 +
6250 +#ifndef _BCMENDIAN_H_
6251 +#define _BCMENDIAN_H_
6252 +
6253 +#include <typedefs.h>
6254 +
6255 +/* Byte swap a 16 bit value */
6256 +#define BCMSWAP16(val) \
6257 + ((uint16)( \
6258 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6259 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6260 +
6261 +/* Byte swap a 32 bit value */
6262 +#define BCMSWAP32(val) \
6263 + ((uint32)( \
6264 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6265 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6266 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6267 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6268 +
6269 +/* 2 Byte swap a 32 bit value */
6270 +#define BCMSWAP32BY16(val) \
6271 + ((uint32)( \
6272 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6273 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6274 +
6275 +
6276 +static INLINE uint16
6277 +bcmswap16(uint16 val)
6278 +{
6279 + return BCMSWAP16(val);
6280 +}
6281 +
6282 +static INLINE uint32
6283 +bcmswap32(uint32 val)
6284 +{
6285 + return BCMSWAP32(val);
6286 +}
6287 +
6288 +static INLINE uint32
6289 +bcmswap32by16(uint32 val)
6290 +{
6291 + return BCMSWAP32BY16(val);
6292 +}
6293 +
6294 +/* buf - start of buffer of shorts to swap */
6295 +/* len - byte length of buffer */
6296 +static INLINE void
6297 +bcmswap16_buf(uint16 *buf, uint len)
6298 +{
6299 + len = len/2;
6300 +
6301 + while(len--){
6302 + *buf = bcmswap16(*buf);
6303 + buf++;
6304 + }
6305 +}
6306 +
6307 +#ifndef hton16
6308 +#ifndef IL_BIGENDIAN
6309 +#define HTON16(i) BCMSWAP16(i)
6310 +#define hton16(i) bcmswap16(i)
6311 +#define hton32(i) bcmswap32(i)
6312 +#define ntoh16(i) bcmswap16(i)
6313 +#define ntoh32(i) bcmswap32(i)
6314 +#define ltoh16(i) (i)
6315 +#define ltoh32(i) (i)
6316 +#define htol16(i) (i)
6317 +#define htol32(i) (i)
6318 +#else
6319 +#define HTON16(i) (i)
6320 +#define hton16(i) (i)
6321 +#define hton32(i) (i)
6322 +#define ntoh16(i) (i)
6323 +#define ntoh32(i) (i)
6324 +#define ltoh16(i) bcmswap16(i)
6325 +#define ltoh32(i) bcmswap32(i)
6326 +#define htol16(i) bcmswap16(i)
6327 +#define htol32(i) bcmswap32(i)
6328 +#endif
6329 +#endif
6330 +
6331 +#ifndef IL_BIGENDIAN
6332 +#define ltoh16_buf(buf, i)
6333 +#define htol16_buf(buf, i)
6334 +#else
6335 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6336 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6337 +#endif
6338 +
6339 +/*
6340 +* load 16-bit value from unaligned little endian byte array.
6341 +*/
6342 +static INLINE uint16
6343 +ltoh16_ua(uint8 *bytes)
6344 +{
6345 + return (bytes[1]<<8)+bytes[0];
6346 +}
6347 +
6348 +/*
6349 +* load 32-bit value from unaligned little endian byte array.
6350 +*/
6351 +static INLINE uint32
6352 +ltoh32_ua(uint8 *bytes)
6353 +{
6354 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6355 +}
6356 +
6357 +/*
6358 +* load 16-bit value from unaligned big(network) endian byte array.
6359 +*/
6360 +static INLINE uint16
6361 +ntoh16_ua(uint8 *bytes)
6362 +{
6363 + return (bytes[0]<<8)+bytes[1];
6364 +}
6365 +
6366 +/*
6367 +* load 32-bit value from unaligned big(network) endian byte array.
6368 +*/
6369 +static INLINE uint32
6370 +ntoh32_ua(uint8 *bytes)
6371 +{
6372 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6373 +}
6374 +
6375 +#define ltoh_ua(ptr) ( \
6376 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6377 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6378 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6379 +)
6380 +
6381 +#define ntoh_ua(ptr) ( \
6382 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6383 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6384 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6385 +)
6386 +
6387 +#endif /* _BCMENDIAN_H_ */
6388 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6389 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6390 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-01-12 00:20:30.725131750 +0100
6391 @@ -0,0 +1,95 @@
6392 +/*
6393 + * NVRAM variable manipulation
6394 + *
6395 + * Copyright 2005, Broadcom Corporation
6396 + * All Rights Reserved.
6397 + *
6398 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6399 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6400 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6401 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6402 + *
6403 + * $Id$
6404 + */
6405 +
6406 +#ifndef _bcmnvram_h_
6407 +#define _bcmnvram_h_
6408 +
6409 +#ifndef _LANGUAGE_ASSEMBLY
6410 +
6411 +#include <typedefs.h>
6412 +
6413 +struct nvram_header {
6414 + uint32 magic;
6415 + uint32 len;
6416 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6417 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6418 + uint32 config_ncdl; /* ncdl values for memc */
6419 +};
6420 +
6421 +struct nvram_tuple {
6422 + char *name;
6423 + char *value;
6424 + struct nvram_tuple *next;
6425 +};
6426 +
6427 +/*
6428 + * Get the value of an NVRAM variable. The pointer returned may be
6429 + * invalid after a set.
6430 + * @param name name of variable to get
6431 + * @return value of variable or NULL if undefined
6432 + */
6433 +extern char * __init early_nvram_get(const char *name);
6434 +
6435 +/*
6436 + * Get the value of an NVRAM variable. The pointer returned may be
6437 + * invalid after a set.
6438 + * @param name name of variable to get
6439 + * @return value of variable or NULL if undefined
6440 + */
6441 +extern char *nvram_get(const char *name);
6442 +
6443 +/*
6444 + * Get the value of an NVRAM variable.
6445 + * @param name name of variable to get
6446 + * @return value of variable or NUL if undefined
6447 + */
6448 +#define nvram_safe_get(name) (BCMINIT(early_nvram_get)(name) ? : "")
6449 +
6450 +/*
6451 + * Match an NVRAM variable.
6452 + * @param name name of variable to match
6453 + * @param match value to compare against value of variable
6454 + * @return TRUE if variable is defined and its value is string equal
6455 + * to match or FALSE otherwise
6456 + */
6457 +static inline int
6458 +nvram_match(char *name, char *match) {
6459 + const char *value = BCMINIT(early_nvram_get)(name);
6460 + return (value && !strcmp(value, match));
6461 +}
6462 +
6463 +/*
6464 + * Inversely match an NVRAM variable.
6465 + * @param name name of variable to match
6466 + * @param match value to compare against value of variable
6467 + * @return TRUE if variable is defined and its value is not string
6468 + * equal to invmatch or FALSE otherwise
6469 + */
6470 +static inline int
6471 +nvram_invmatch(char *name, char *invmatch) {
6472 + const char *value = BCMINIT(early_nvram_get)(name);
6473 + return (value && strcmp(value, invmatch));
6474 +}
6475 +
6476 +#endif /* _LANGUAGE_ASSEMBLY */
6477 +
6478 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6479 +#define NVRAM_VERSION 1
6480 +#define NVRAM_HEADER_SIZE 20
6481 +#define NVRAM_SPACE 0x8000
6482 +
6483 +#define NVRAM_MAX_VALUE_LEN 255
6484 +#define NVRAM_MAX_PARAM_LEN 64
6485 +
6486 +#endif /* _bcmnvram_h_ */
6487 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6488 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6489 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-01-12 00:20:30.725131750 +0100
6490 @@ -0,0 +1,23 @@
6491 +/*
6492 + * Misc useful routines to access NIC local SROM/OTP .
6493 + *
6494 + * Copyright 2005, Broadcom Corporation
6495 + * All Rights Reserved.
6496 + *
6497 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6498 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6499 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6500 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6501 + *
6502 + * $Id$
6503 + */
6504 +
6505 +#ifndef _bcmsrom_h_
6506 +#define _bcmsrom_h_
6507 +
6508 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6509 +
6510 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6511 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6512 +
6513 +#endif /* _bcmsrom_h_ */
6514 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6515 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6516 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-01-12 00:20:30.725131750 +0100
6517 @@ -0,0 +1,308 @@
6518 +/*
6519 + * Misc useful os-independent macros and functions.
6520 + *
6521 + * Copyright 2005, Broadcom Corporation
6522 + * All Rights Reserved.
6523 + *
6524 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6525 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6526 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6527 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6528 + * $Id$
6529 + */
6530 +
6531 +#ifndef _bcmutils_h_
6532 +#define _bcmutils_h_
6533 +
6534 +/*** driver-only section ***/
6535 +#include <osl.h>
6536 +
6537 +#define _BCM_U 0x01 /* upper */
6538 +#define _BCM_L 0x02 /* lower */
6539 +#define _BCM_D 0x04 /* digit */
6540 +#define _BCM_C 0x08 /* cntrl */
6541 +#define _BCM_P 0x10 /* punct */
6542 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6543 +#define _BCM_X 0x40 /* hex digit */
6544 +#define _BCM_SP 0x80 /* hard space (0x20) */
6545 +
6546 +#define GPIO_PIN_NOTDEFINED 0x20
6547 +
6548 +extern unsigned char bcm_ctype[];
6549 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6550 +
6551 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6552 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6553 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6554 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6555 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6556 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6557 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6558 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6559 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6560 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6561 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6562 +
6563 +/*
6564 + * Spin at most 'us' microseconds while 'exp' is true.
6565 + * Caller should explicitly test 'exp' when this completes
6566 + * and take appropriate error action if 'exp' is still true.
6567 + */
6568 +#define SPINWAIT(exp, us) { \
6569 + uint countdown = (us) + 9; \
6570 + while ((exp) && (countdown >= 10)) {\
6571 + OSL_DELAY(10); \
6572 + countdown -= 10; \
6573 + } \
6574 +}
6575 +
6576 +/* generic osl packet queue */
6577 +struct pktq {
6578 + void *head; /* first packet to dequeue */
6579 + void *tail; /* last packet to dequeue */
6580 + uint len; /* number of queued packets */
6581 + uint maxlen; /* maximum number of queued packets */
6582 + bool priority; /* enqueue by packet priority */
6583 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6584 +};
6585 +#define DEFAULT_QLEN 128
6586 +
6587 +#define pktq_len(q) ((q)->len)
6588 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6589 +#define pktq_head(q) ((q)->head)
6590 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6591 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6592 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6593 +
6594 +/* externs */
6595 +/* packet */
6596 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6597 +extern uint pkttotlen(osl_t *osh, void *);
6598 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6599 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6600 +extern void *pktdeq(struct pktq *q);
6601 +extern void *pktdeqtail(struct pktq *q);
6602 +/* string */
6603 +extern uint bcm_atoi(char *s);
6604 +extern uchar bcm_toupper(uchar c);
6605 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6606 +extern char *bcmstrstr(char *haystack, char *needle);
6607 +extern char *bcmstrcat(char *dest, const char *src);
6608 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6609 +/* ethernet address */
6610 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6611 +extern int bcm_ether_atoe(char *p, char *ea);
6612 +/* delay */
6613 +extern void bcm_mdelay(uint ms);
6614 +/* variable access */
6615 +extern char *getvar(char *vars, char *name);
6616 +extern int getintvar(char *vars, char *name);
6617 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6618 +#define bcmlog(fmt, a1, a2)
6619 +#define bcmdumplog(buf, size) *buf = '\0'
6620 +#define bcmdumplogent(buf, idx) -1
6621 +
6622 +/*** driver/apps-shared section ***/
6623 +
6624 +#define BCME_STRLEN 64
6625 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6626 +
6627 +
6628 +/*
6629 + * error codes could be added but the defined ones shouldn't be changed/deleted
6630 + * these error codes are exposed to the user code
6631 + * when ever a new error code is added to this list
6632 + * please update errorstring table with the related error string and
6633 + * update osl files with os specific errorcode map
6634 +*/
6635 +
6636 +#define BCME_ERROR -1 /* Error generic */
6637 +#define BCME_BADARG -2 /* Bad Argument */
6638 +#define BCME_BADOPTION -3 /* Bad option */
6639 +#define BCME_NOTUP -4 /* Not up */
6640 +#define BCME_NOTDOWN -5 /* Not down */
6641 +#define BCME_NOTAP -6 /* Not AP */
6642 +#define BCME_NOTSTA -7 /* Not STA */
6643 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6644 +#define BCME_RADIOOFF -9 /* Radio Off */
6645 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6646 +#define BCME_NOCLK -11 /* No Clock*/
6647 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6648 +#define BCME_BADBAND -13 /* BAD Band */
6649 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6650 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6651 +#define BCME_BUSY -16 /* Busy*/
6652 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6653 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6654 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6655 +#define BCME_BADCHAN -20 /* BAD Channel */
6656 +#define BCME_BADADDR -21 /* BAD Address*/
6657 +#define BCME_NORESOURCE -22 /* No resources*/
6658 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6659 +#define BCME_BADLEN -24 /* Bad Length*/
6660 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6661 +#define BCME_EPERM -26 /* Not Permitted */
6662 +#define BCME_NOMEM -27 /* No Memory */
6663 +#define BCME_ASSOCIATED -28 /* Associated */
6664 +#define BCME_RANGE -29 /* Range Error*/
6665 +#define BCME_NOTFOUND -30 /* Not found */
6666 +#define BCME_LAST BCME_NOTFOUND
6667 +
6668 +#ifndef ABS
6669 +#define ABS(a) (((a)<0)?-(a):(a))
6670 +#endif
6671 +
6672 +#ifndef MIN
6673 +#define MIN(a, b) (((a)<(b))?(a):(b))
6674 +#endif
6675 +
6676 +#ifndef MAX
6677 +#define MAX(a, b) (((a)>(b))?(a):(b))
6678 +#endif
6679 +
6680 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6681 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6682 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6683 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6684 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6685 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6686 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6687 +
6688 +/* bit map related macros */
6689 +#ifndef setbit
6690 +#define NBBY 8 /* 8 bits per byte */
6691 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6692 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6693 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6694 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6695 +#endif
6696 +
6697 +#define NBITS(type) (sizeof(type) * 8)
6698 +#define NBITVAL(bits) (1 << (bits))
6699 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6700 +
6701 +/* crc defines */
6702 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6703 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6704 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6705 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6706 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6707 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6708 +
6709 +/* bcm_format_flags() bit description structure */
6710 +typedef struct bcm_bit_desc {
6711 + uint32 bit;
6712 + char* name;
6713 +} bcm_bit_desc_t;
6714 +
6715 +/* tag_ID/length/value_buffer tuple */
6716 +typedef struct bcm_tlv {
6717 + uint8 id;
6718 + uint8 len;
6719 + uint8 data[1];
6720 +} bcm_tlv_t;
6721 +
6722 +/* Check that bcm_tlv_t fits into the given buflen */
6723 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6724 +
6725 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6726 +#define ETHER_ADDR_STR_LEN 18
6727 +
6728 +/* unaligned load and store macros */
6729 +#ifdef IL_BIGENDIAN
6730 +static INLINE uint32
6731 +load32_ua(uint8 *a)
6732 +{
6733 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6734 +}
6735 +
6736 +static INLINE void
6737 +store32_ua(uint8 *a, uint32 v)
6738 +{
6739 + a[0] = (v >> 24) & 0xff;
6740 + a[1] = (v >> 16) & 0xff;
6741 + a[2] = (v >> 8) & 0xff;
6742 + a[3] = v & 0xff;
6743 +}
6744 +
6745 +static INLINE uint16
6746 +load16_ua(uint8 *a)
6747 +{
6748 + return ((a[0] << 8) | a[1]);
6749 +}
6750 +
6751 +static INLINE void
6752 +store16_ua(uint8 *a, uint16 v)
6753 +{
6754 + a[0] = (v >> 8) & 0xff;
6755 + a[1] = v & 0xff;
6756 +}
6757 +
6758 +#else
6759 +
6760 +static INLINE uint32
6761 +load32_ua(uint8 *a)
6762 +{
6763 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6764 +}
6765 +
6766 +static INLINE void
6767 +store32_ua(uint8 *a, uint32 v)
6768 +{
6769 + a[3] = (v >> 24) & 0xff;
6770 + a[2] = (v >> 16) & 0xff;
6771 + a[1] = (v >> 8) & 0xff;
6772 + a[0] = v & 0xff;
6773 +}
6774 +
6775 +static INLINE uint16
6776 +load16_ua(uint8 *a)
6777 +{
6778 + return ((a[1] << 8) | a[0]);
6779 +}
6780 +
6781 +static INLINE void
6782 +store16_ua(uint8 *a, uint16 v)
6783 +{
6784 + a[1] = (v >> 8) & 0xff;
6785 + a[0] = v & 0xff;
6786 +}
6787 +
6788 +#endif
6789 +
6790 +/* externs */
6791 +/* crc */
6792 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6793 +/* format/print */
6794 +/* IE parsing */
6795 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6796 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6797 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6798 +
6799 +/* bcmerror*/
6800 +extern const char *bcmerrorstr(int bcmerror);
6801 +
6802 +/* multi-bool data type: set of bools, mbool is true if any is set */
6803 +typedef uint32 mbool;
6804 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6805 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6806 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6807 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6808 +
6809 +/* power conversion */
6810 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6811 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6812 +
6813 +/* generic datastruct to help dump routines */
6814 +struct fielddesc {
6815 + char *nameandfmt;
6816 + uint32 offset;
6817 + uint32 len;
6818 +};
6819 +
6820 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6821 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6822 +
6823 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6824 +
6825 +#endif /* _bcmutils_h_ */
6826 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6827 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6828 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2006-01-12 00:20:30.729132000 +0100
6829 @@ -0,0 +1,85 @@
6830 +/*
6831 + * bit manipulation utility functions
6832 + *
6833 + * Copyright 2005, Broadcom Corporation
6834 + * All Rights Reserved.
6835 + *
6836 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6837 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6838 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6839 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6840 + * $Id$
6841 + */
6842 +
6843 +#ifndef _BITFUNCS_H
6844 +#define _BITFUNCS_H
6845 +
6846 +#include <typedefs.h>
6847 +
6848 +/* local prototypes */
6849 +static INLINE uint32 find_msbit(uint32 x);
6850 +
6851 +
6852 +/*
6853 + * find_msbit: returns index of most significant set bit in x, with index
6854 + * range defined as 0-31. NOTE: returns zero if input is zero.
6855 + */
6856 +
6857 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6858 +
6859 +/*
6860 + * Implementation for Pentium processors and gcc. Note that this
6861 + * instruction is actually very slow on some processors (e.g., family 5,
6862 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6863 + * implementation instead.
6864 + */
6865 +static INLINE uint32 find_msbit(uint32 x)
6866 +{
6867 + uint msbit;
6868 + __asm__("bsrl %1,%0"
6869 + :"=r" (msbit)
6870 + :"r" (x));
6871 + return msbit;
6872 +}
6873 +
6874 +#else
6875 +
6876 +/*
6877 + * Generic Implementation
6878 + */
6879 +
6880 +#define DB_POW_MASK16 0xffff0000
6881 +#define DB_POW_MASK8 0x0000ff00
6882 +#define DB_POW_MASK4 0x000000f0
6883 +#define DB_POW_MASK2 0x0000000c
6884 +#define DB_POW_MASK1 0x00000002
6885 +
6886 +static INLINE uint32 find_msbit(uint32 x)
6887 +{
6888 + uint32 temp_x = x;
6889 + uint msbit = 0;
6890 + if (temp_x & DB_POW_MASK16) {
6891 + temp_x >>= 16;
6892 + msbit = 16;
6893 + }
6894 + if (temp_x & DB_POW_MASK8) {
6895 + temp_x >>= 8;
6896 + msbit += 8;
6897 + }
6898 + if (temp_x & DB_POW_MASK4) {
6899 + temp_x >>= 4;
6900 + msbit += 4;
6901 + }
6902 + if (temp_x & DB_POW_MASK2) {
6903 + temp_x >>= 2;
6904 + msbit += 2;
6905 + }
6906 + if (temp_x & DB_POW_MASK1) {
6907 + msbit += 1;
6908 + }
6909 + return(msbit);
6910 +}
6911 +
6912 +#endif
6913 +
6914 +#endif /* _BITFUNCS_H */
6915 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6916 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6917 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2006-01-12 00:20:30.729132000 +0100
6918 @@ -0,0 +1,188 @@
6919 +/*
6920 + * flash.h: Common definitions for flash access.
6921 + *
6922 + * Copyright 2005, Broadcom Corporation
6923 + * All Rights Reserved.
6924 + *
6925 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6926 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6927 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6928 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6929 + *
6930 + * $Id$
6931 + */
6932 +
6933 +/* Types of flashes we know about */
6934 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6935 +
6936 +/* Commands to write/erase the flases */
6937 +typedef struct _flash_cmds{
6938 + flash_type_t type;
6939 + bool need_unlock;
6940 + uint16 pre_erase;
6941 + uint16 erase_block;
6942 + uint16 erase_chip;
6943 + uint16 write_word;
6944 + uint16 write_buf;
6945 + uint16 clear_csr;
6946 + uint16 read_csr;
6947 + uint16 read_id;
6948 + uint16 confirm;
6949 + uint16 read_array;
6950 +} flash_cmds_t;
6951 +
6952 +#define UNLOCK_CMD_WORDS 2
6953 +
6954 +typedef struct _unlock_cmd {
6955 + uint addr[UNLOCK_CMD_WORDS];
6956 + uint16 cmd[UNLOCK_CMD_WORDS];
6957 +} unlock_cmd_t;
6958 +
6959 +/* Flash descriptors */
6960 +typedef struct _flash_desc {
6961 + uint16 mfgid; /* Manufacturer Id */
6962 + uint16 devid; /* Device Id */
6963 + uint size; /* Total size in bytes */
6964 + uint width; /* Device width in bytes */
6965 + flash_type_t type; /* Device type old, S, J */
6966 + uint bsize; /* Block size */
6967 + uint nb; /* Number of blocks */
6968 + uint ff; /* First full block */
6969 + uint lf; /* Last full block */
6970 + uint nsub; /* Number of subblocks */
6971 + uint *subblocks; /* Offsets for subblocks */
6972 + char *desc; /* Description */
6973 +} flash_desc_t;
6974 +
6975 +
6976 +#ifdef DECLARE_FLASHES
6977 +flash_cmds_t sflash_cmd_t =
6978 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6979 +
6980 +flash_cmds_t flash_cmds[] = {
6981 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6982 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6983 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6984 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6985 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6986 + { 0 }
6987 +};
6988 +
6989 +unlock_cmd_t unlock_cmd_amd = {
6990 +#ifdef MIPSEB
6991 +/* addr: */ { 0x0aa8, 0x0556},
6992 +#else
6993 +/* addr: */ { 0x0aaa, 0x0554},
6994 +#endif
6995 +/* data: */ { 0xaa, 0x55}
6996 +};
6997 +
6998 +unlock_cmd_t unlock_cmd_sst = {
6999 +#ifdef MIPSEB
7000 +/* addr: */ { 0xaaa8, 0x5556},
7001 +#else
7002 +/* addr: */ { 0xaaaa, 0x5554},
7003 +#endif
7004 +/* data: */ { 0xaa, 0x55}
7005 +};
7006 +
7007 +#define AMD_CMD 0xaaa
7008 +#define SST_CMD 0xaaaa
7009 +
7010 +/* intel unlock block cmds */
7011 +#define INTEL_UNLOCK1 0x60
7012 +#define INTEL_UNLOCK2 0xD0
7013 +
7014 +/* Just eight blocks of 8KB byte each */
7015 +
7016 +uint blk8x8k[] = { 0x00000000,
7017 + 0x00002000,
7018 + 0x00004000,
7019 + 0x00006000,
7020 + 0x00008000,
7021 + 0x0000a000,
7022 + 0x0000c000,
7023 + 0x0000e000,
7024 + 0x00010000
7025 +};
7026 +
7027 +/* Funky AMD arrangement for 29xx800's */
7028 +uint amd800[] = { 0x00000000, /* 16KB */
7029 + 0x00004000, /* 32KB */
7030 + 0x0000c000, /* 8KB */
7031 + 0x0000e000, /* 8KB */
7032 + 0x00010000, /* 8KB */
7033 + 0x00012000, /* 8KB */
7034 + 0x00014000, /* 32KB */
7035 + 0x0001c000, /* 16KB */
7036 + 0x00020000
7037 +};
7038 +
7039 +/* AMD arrangement for 29xx160's */
7040 +uint amd4112[] = { 0x00000000, /* 32KB */
7041 + 0x00008000, /* 8KB */
7042 + 0x0000a000, /* 8KB */
7043 + 0x0000c000, /* 16KB */
7044 + 0x00010000
7045 +};
7046 +uint amd2114[] = { 0x00000000, /* 16KB */
7047 + 0x00004000, /* 8KB */
7048 + 0x00006000, /* 8KB */
7049 + 0x00008000, /* 32KB */
7050 + 0x00010000
7051 +};
7052 +
7053 +
7054 +flash_desc_t sflash_desc =
7055 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7056 +
7057 +flash_desc_t flashes[] = {
7058 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7059 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7060 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7061 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7062 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7063 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7064 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7065 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7066 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7067 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7068 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7069 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7070 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7071 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7072 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7073 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7074 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7075 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7076 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7077 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7078 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7079 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7080 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7081 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7082 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7083 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7084 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7085 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7086 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7087 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7088 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7089 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7090 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7091 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7092 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7093 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7094 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7095 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7096 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7097 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7098 +};
7099 +
7100 +#else
7101 +
7102 +extern flash_cmds_t flash_cmds[];
7103 +extern unlock_cmd_t unlock_cmd;
7104 +extern flash_desc_t flashes[];
7105 +
7106 +#endif
7107 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7108 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7109 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2006-01-12 00:20:30.729132000 +0100
7110 @@ -0,0 +1,27 @@
7111 +/*
7112 + * BCM47XX FLASH driver interface
7113 + *
7114 + * Copyright 2005, Broadcom Corporation
7115 + * All Rights Reserved.
7116 + *
7117 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7118 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7119 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7120 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7121 + * $Id$
7122 + */
7123 +
7124 +#ifndef _flashutl_h_
7125 +#define _flashutl_h_
7126 +
7127 +
7128 +#ifndef _LANGUAGE_ASSEMBLY
7129 +
7130 +int sysFlashInit(char *flash_str);
7131 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7132 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7133 +void nvWrite(unsigned short *data, unsigned int len);
7134 +
7135 +#endif /* _LANGUAGE_ASSEMBLY */
7136 +
7137 +#endif /* _flashutl_h_ */
7138 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7139 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7140 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-01-12 00:20:30.729132000 +0100
7141 @@ -0,0 +1,16 @@
7142 +/*
7143 + * Alternate include file for HND sbmips.h since CFE also ships with
7144 + * a sbmips.h.
7145 + *
7146 + * Copyright 2005, Broadcom Corporation
7147 + * All Rights Reserved.
7148 + *
7149 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7150 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7151 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7152 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7153 + *
7154 + * $Id$
7155 + */
7156 +
7157 +#include "sbmips.h"
7158 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7159 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7160 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2006-01-12 00:20:30.729132000 +0100
7161 @@ -0,0 +1,331 @@
7162 +/*
7163 + * Linux OS Independent Layer
7164 + *
7165 + * Copyright 2005, Broadcom Corporation
7166 + * All Rights Reserved.
7167 + *
7168 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7169 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7170 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7171 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7172 + *
7173 + * $Id$
7174 + */
7175 +
7176 +#ifndef _linux_osl_h_
7177 +#define _linux_osl_h_
7178 +
7179 +#include <typedefs.h>
7180 +
7181 +/* use current 2.4.x calling conventions */
7182 +#include <linuxver.h>
7183 +
7184 +/* assert and panic */
7185 +#ifdef __GNUC__
7186 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7187 +#if GCC_VERSION > 30100
7188 +#define ASSERT(exp) do {} while (0)
7189 +#else
7190 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7191 +#define ASSERT(exp)
7192 +#endif
7193 +#endif
7194 +
7195 +/* microsecond delay */
7196 +#define OSL_DELAY(usec) osl_delay(usec)
7197 +extern void osl_delay(uint usec);
7198 +
7199 +/* PCI configuration space access macros */
7200 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7201 + osl_pci_read_config((osh), (offset), (size))
7202 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7203 + osl_pci_write_config((osh), (offset), (size), (val))
7204 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7205 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7206 +
7207 +/* PCI device bus # and slot # */
7208 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7209 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7210 +extern uint osl_pci_bus(osl_t *osh);
7211 +extern uint osl_pci_slot(osl_t *osh);
7212 +
7213 +/* OSL initialization */
7214 +extern osl_t *osl_attach(void *pdev);
7215 +extern void osl_detach(osl_t *osh);
7216 +
7217 +/* host/bus architecture-specific byte swap */
7218 +#define BUS_SWAP32(v) (v)
7219 +
7220 +/* general purpose memory allocation */
7221 +
7222 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7223 +#define MFREE(osh, addr, size) kfree(addr);
7224 +
7225 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7226 +
7227 +extern void *osl_malloc(osl_t *osh, uint size);
7228 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7229 +extern uint osl_malloced(osl_t *osh);
7230 +extern uint osl_malloc_failed(osl_t *osh);
7231 +
7232 +/* allocate/free shared (dma-able) consistent memory */
7233 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7234 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7235 + osl_dma_alloc_consistent((osh), (size), (pap))
7236 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7237 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7238 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7239 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7240 +
7241 +/* map/unmap direction */
7242 +#define DMA_TX 1
7243 +#define DMA_RX 2
7244 +
7245 +/* register access macros */
7246 +#if defined(BCMJTAG)
7247 +#include <bcmjtag.h>
7248 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7249 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7250 +#endif
7251 +
7252 +/*
7253 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7254 + * Macros expand to calls to functions defined in linux_osl.c .
7255 + */
7256 +#ifndef BINOSL
7257 +
7258 +/* string library, kernel mode */
7259 +#define printf(fmt, args...) printk(fmt, ## args)
7260 +#include <linux/kernel.h>
7261 +#include <linux/string.h>
7262 +
7263 +/* register access macros */
7264 +#if !defined(BCMJTAG)
7265 +#ifndef IL_BIGENDIAN
7266 +#define R_REG(r) ( \
7267 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7268 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7269 + readl((volatile uint32*)(r)) \
7270 +)
7271 +#define W_REG(r, v) do { \
7272 + switch (sizeof(*(r))) { \
7273 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7274 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7275 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7276 + } \
7277 +} while (0)
7278 +#else /* IL_BIGENDIAN */
7279 +#define R_REG(r) ({ \
7280 + __typeof(*(r)) __osl_v; \
7281 + switch (sizeof(*(r))) { \
7282 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7283 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7284 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7285 + } \
7286 + __osl_v; \
7287 +})
7288 +#define W_REG(r, v) do { \
7289 + switch (sizeof(*(r))) { \
7290 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7291 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7292 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7293 + } \
7294 +} while (0)
7295 +#endif
7296 +#endif
7297 +
7298 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7299 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7300 +
7301 +/* bcopy, bcmp, and bzero */
7302 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7303 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7304 +#define bzero(b, len) memset((b), '\0', (len))
7305 +
7306 +/* uncached virtual address */
7307 +#ifdef mips
7308 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7309 +#include <asm/addrspace.h>
7310 +#else
7311 +#define OSL_UNCACHED(va) (va)
7312 +#endif
7313 +
7314 +/* get processor cycle count */
7315 +#if defined(mips)
7316 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7317 +#elif defined(__i386__)
7318 +#define OSL_GETCYCLES(x) rdtscl((x))
7319 +#else
7320 +#define OSL_GETCYCLES(x) ((x) = 0)
7321 +#endif
7322 +
7323 +/* dereference an address that may cause a bus exception */
7324 +#ifdef mips
7325 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7326 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7327 +#else
7328 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7329 +#include <asm/paccess.h>
7330 +#endif
7331 +#else
7332 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7333 +#endif
7334 +
7335 +/* map/unmap physical to virtual I/O */
7336 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7337 +#define REG_UNMAP(va) iounmap((void *)(va))
7338 +
7339 +/* shared (dma-able) memory access macros */
7340 +#define R_SM(r) *(r)
7341 +#define W_SM(r, v) (*(r) = (v))
7342 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7343 +
7344 +/* packet primitives */
7345 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7346 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7347 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7348 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7349 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7350 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7351 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7352 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7353 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7354 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7355 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7356 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7357 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7358 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7359 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7360 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7361 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7362 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7363 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7364 +extern void osl_pktfree(void *skb);
7365 +
7366 +#else /* BINOSL */
7367 +
7368 +/* string library */
7369 +#ifndef LINUX_OSL
7370 +#undef printf
7371 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7372 +#undef sprintf
7373 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7374 +#undef strcmp
7375 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7376 +#undef strncmp
7377 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7378 +#undef strlen
7379 +#define strlen(s) osl_strlen((s))
7380 +#undef strcpy
7381 +#define strcpy(d, s) osl_strcpy((d), (s))
7382 +#undef strncpy
7383 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7384 +#endif
7385 +extern int osl_printf(const char *format, ...);
7386 +extern int osl_sprintf(char *buf, const char *format, ...);
7387 +extern int osl_strcmp(const char *s1, const char *s2);
7388 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7389 +extern int osl_strlen(const char *s);
7390 +extern char* osl_strcpy(char *d, const char *s);
7391 +extern char* osl_strncpy(char *d, const char *s, uint n);
7392 +
7393 +/* register access macros */
7394 +#if !defined(BCMJTAG)
7395 +#define R_REG(r) ( \
7396 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7397 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7398 + osl_readl((volatile uint32*)(r)) \
7399 +)
7400 +#define W_REG(r, v) do { \
7401 + switch (sizeof(*(r))) { \
7402 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7403 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7404 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7405 + } \
7406 +} while (0)
7407 +#endif
7408 +
7409 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7410 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7411 +extern uint8 osl_readb(volatile uint8 *r);
7412 +extern uint16 osl_readw(volatile uint16 *r);
7413 +extern uint32 osl_readl(volatile uint32 *r);
7414 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7415 +extern void osl_writew(uint16 v, volatile uint16 *r);
7416 +extern void osl_writel(uint32 v, volatile uint32 *r);
7417 +
7418 +/* bcopy, bcmp, and bzero */
7419 +extern void bcopy(const void *src, void *dst, int len);
7420 +extern int bcmp(const void *b1, const void *b2, int len);
7421 +extern void bzero(void *b, int len);
7422 +
7423 +/* uncached virtual address */
7424 +#define OSL_UNCACHED(va) osl_uncached((va))
7425 +extern void *osl_uncached(void *va);
7426 +
7427 +/* get processor cycle count */
7428 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7429 +extern uint osl_getcycles(void);
7430 +
7431 +/* dereference an address that may target abort */
7432 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7433 +extern int osl_busprobe(uint32 *val, uint32 addr);
7434 +
7435 +/* map/unmap physical to virtual */
7436 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7437 +#define REG_UNMAP(va) osl_reg_unmap((va))
7438 +extern void *osl_reg_map(uint32 pa, uint size);
7439 +extern void osl_reg_unmap(void *va);
7440 +
7441 +/* shared (dma-able) memory access macros */
7442 +#define R_SM(r) *(r)
7443 +#define W_SM(r, v) (*(r) = (v))
7444 +#define BZERO_SM(r, len) bzero((r), (len))
7445 +
7446 +/* packet primitives */
7447 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7448 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7449 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7450 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7451 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7452 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7453 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7454 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7455 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7456 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7457 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7458 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7459 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7460 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7461 +#define PKTLINK(skb) osl_pktlink((skb))
7462 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7463 +#define PKTPRIO(skb) osl_pktprio((skb))
7464 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7465 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7466 +extern void osl_pktfree(void *skb);
7467 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7468 +extern uint osl_pktlen(osl_t *osh, void *skb);
7469 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7470 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7471 +extern void *osl_pktnext(osl_t *osh, void *skb);
7472 +extern void osl_pktsetnext(void *skb, void *x);
7473 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7474 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7475 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7476 +extern void *osl_pktdup(osl_t *osh, void *skb);
7477 +extern void *osl_pktcookie(void *skb);
7478 +extern void osl_pktsetcookie(void *skb, void *x);
7479 +extern void *osl_pktlink(void *skb);
7480 +extern void osl_pktsetlink(void *skb, void *x);
7481 +extern uint osl_pktprio(void *skb);
7482 +extern void osl_pktsetprio(void *skb, uint x);
7483 +
7484 +#endif /* BINOSL */
7485 +
7486 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7487 +extern int osl_error(int bcmerror);
7488 +
7489 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7490 +#define PKTBUFSZ 2048
7491 +
7492 +#endif /* _linux_osl_h_ */
7493 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7494 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7495 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-01-12 00:20:30.729132000 +0100
7496 @@ -0,0 +1,389 @@
7497 +/*
7498 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7499 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7500 + *
7501 + * Copyright 2005, Broadcom Corporation
7502 + * All Rights Reserved.
7503 + *
7504 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7505 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7506 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7507 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7508 + *
7509 + * $Id$
7510 + */
7511 +
7512 +#ifndef _linuxver_h_
7513 +#define _linuxver_h_
7514 +
7515 +#include <linux/config.h>
7516 +#include <linux/version.h>
7517 +
7518 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7519 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7520 +#ifdef __UNDEF_NO_VERSION__
7521 +#undef __NO_VERSION__
7522 +#else
7523 +#define __NO_VERSION__
7524 +#endif
7525 +#endif
7526 +
7527 +#if defined(MODULE) && defined(MODVERSIONS)
7528 +#include <linux/modversions.h>
7529 +#endif
7530 +
7531 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7532 +#include <linux/moduleparam.h>
7533 +#endif
7534 +
7535 +
7536 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7537 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7538 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7539 +#endif
7540 +
7541 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7542 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7543 +#include <linux/malloc.h>
7544 +#else
7545 +#include <linux/slab.h>
7546 +#endif
7547 +
7548 +#include <linux/types.h>
7549 +#include <linux/init.h>
7550 +#include <linux/mm.h>
7551 +#include <linux/string.h>
7552 +#include <linux/pci.h>
7553 +#include <linux/interrupt.h>
7554 +#include <linux/netdevice.h>
7555 +#include <asm/io.h>
7556 +
7557 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7558 +#include <linux/workqueue.h>
7559 +#else
7560 +#include <linux/tqueue.h>
7561 +#ifndef work_struct
7562 +#define work_struct tq_struct
7563 +#endif
7564 +#ifndef INIT_WORK
7565 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7566 +#endif
7567 +#ifndef schedule_work
7568 +#define schedule_work(_work) schedule_task((_work))
7569 +#endif
7570 +#ifndef flush_scheduled_work
7571 +#define flush_scheduled_work() flush_scheduled_tasks()
7572 +#endif
7573 +#endif
7574 +
7575 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7576 +/* Some distributions have their own 2.6.x compatibility layers */
7577 +#ifndef IRQ_NONE
7578 +typedef void irqreturn_t;
7579 +#define IRQ_NONE
7580 +#define IRQ_HANDLED
7581 +#define IRQ_RETVAL(x)
7582 +#endif
7583 +#else
7584 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7585 +#endif
7586 +
7587 +#ifndef __exit
7588 +#define __exit
7589 +#endif
7590 +#ifndef __devexit
7591 +#define __devexit
7592 +#endif
7593 +#ifndef __devinit
7594 +#define __devinit __init
7595 +#endif
7596 +#ifndef __devinitdata
7597 +#define __devinitdata
7598 +#endif
7599 +#ifndef __devexit_p
7600 +#define __devexit_p(x) x
7601 +#endif
7602 +
7603 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7604 +
7605 +#define pci_get_drvdata(dev) (dev)->sysdata
7606 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7607 +
7608 +/*
7609 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7610 + */
7611 +
7612 +struct pci_device_id {
7613 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7614 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7615 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7616 + unsigned long driver_data; /* Data private to the driver */
7617 +};
7618 +
7619 +struct pci_driver {
7620 + struct list_head node;
7621 + char *name;
7622 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7623 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7624 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7625 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7626 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7627 +};
7628 +
7629 +#define MODULE_DEVICE_TABLE(type, name)
7630 +#define PCI_ANY_ID (~0)
7631 +
7632 +/* compatpci.c */
7633 +#define pci_module_init pci_register_driver
7634 +extern int pci_register_driver(struct pci_driver *drv);
7635 +extern void pci_unregister_driver(struct pci_driver *drv);
7636 +
7637 +#endif /* PCI registration */
7638 +
7639 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7640 +#ifdef MODULE
7641 +#define module_init(x) int init_module(void) { return x(); }
7642 +#define module_exit(x) void cleanup_module(void) { x(); }
7643 +#else
7644 +#define module_init(x) __initcall(x);
7645 +#define module_exit(x) __exitcall(x);
7646 +#endif
7647 +#endif
7648 +
7649 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7650 +#define list_for_each(pos, head) \
7651 + for (pos = (head)->next; pos != (head); pos = pos->next)
7652 +#endif
7653 +
7654 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7655 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7656 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7657 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7658 +#endif
7659 +
7660 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7661 +#define pci_enable_device(dev) do { } while (0)
7662 +#endif
7663 +
7664 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7665 +#define net_device device
7666 +#endif
7667 +
7668 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7669 +
7670 +/*
7671 + * DMA mapping
7672 + *
7673 + * See linux/Documentation/DMA-mapping.txt
7674 + */
7675 +
7676 +#ifndef PCI_DMA_TODEVICE
7677 +#define PCI_DMA_TODEVICE 1
7678 +#define PCI_DMA_FROMDEVICE 2
7679 +#endif
7680 +
7681 +typedef u32 dma_addr_t;
7682 +
7683 +/* Pure 2^n version of get_order */
7684 +static inline int get_order(unsigned long size)
7685 +{
7686 + int order;
7687 +
7688 + size = (size-1) >> (PAGE_SHIFT-1);
7689 + order = -1;
7690 + do {
7691 + size >>= 1;
7692 + order++;
7693 + } while (size);
7694 + return order;
7695 +}
7696 +
7697 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7698 + dma_addr_t *dma_handle)
7699 +{
7700 + void *ret;
7701 + int gfp = GFP_ATOMIC | GFP_DMA;
7702 +
7703 + ret = (void *)__get_free_pages(gfp, get_order(size));
7704 +
7705 + if (ret != NULL) {
7706 + memset(ret, 0, size);
7707 + *dma_handle = virt_to_bus(ret);
7708 + }
7709 + return ret;
7710 +}
7711 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7712 + void *vaddr, dma_addr_t dma_handle)
7713 +{
7714 + free_pages((unsigned long)vaddr, get_order(size));
7715 +}
7716 +#ifdef ILSIM
7717 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7718 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7719 +#else
7720 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7721 +#define pci_unmap_single(cookie, address, size, dir)
7722 +#endif
7723 +
7724 +#endif /* DMA mapping */
7725 +
7726 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7727 +
7728 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7729 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7730 +
7731 +/* pcmcia-cs provides its own netdevice compatibility layer */
7732 +#ifndef _COMPAT_NETDEVICE_H
7733 +
7734 +/*
7735 + * SoftNet
7736 + *
7737 + * For pre-softnet kernels we need to tell the upper layer not to
7738 + * re-enter start_xmit() while we are in there. However softnet
7739 + * guarantees not to enter while we are in there so there is no need
7740 + * to do the netif_stop_queue() dance unless the transmit queue really
7741 + * gets stuck. This should also improve performance according to tests
7742 + * done by Aman Singla.
7743 + */
7744 +
7745 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7746 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7747 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7748 +
7749 +static inline void netif_start_queue(struct net_device *dev)
7750 +{
7751 + dev->tbusy = 0;
7752 + dev->interrupt = 0;
7753 + dev->start = 1;
7754 +}
7755 +
7756 +#define netif_queue_stopped(dev) (dev)->tbusy
7757 +#define netif_running(dev) (dev)->start
7758 +
7759 +#endif /* _COMPAT_NETDEVICE_H */
7760 +
7761 +#define netif_device_attach(dev) netif_start_queue(dev)
7762 +#define netif_device_detach(dev) netif_stop_queue(dev)
7763 +
7764 +/* 2.4.x renamed bottom halves to tasklets */
7765 +#define tasklet_struct tq_struct
7766 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7767 +{
7768 + queue_task(tasklet, &tq_immediate);
7769 + mark_bh(IMMEDIATE_BH);
7770 +}
7771 +
7772 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7773 + void (*func)(unsigned long),
7774 + unsigned long data)
7775 +{
7776 + tasklet->next = NULL;
7777 + tasklet->sync = 0;
7778 + tasklet->routine = (void (*)(void *))func;
7779 + tasklet->data = (void *)data;
7780 +}
7781 +#define tasklet_kill(tasklet) {do{} while(0);}
7782 +
7783 +/* 2.4.x introduced del_timer_sync() */
7784 +#define del_timer_sync(timer) del_timer(timer)
7785 +
7786 +#else
7787 +
7788 +#define netif_down(dev)
7789 +
7790 +#endif /* SoftNet */
7791 +
7792 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7793 +
7794 +/*
7795 + * Emit code to initialise a tq_struct's routine and data pointers
7796 + */
7797 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7798 + do { \
7799 + (_tq)->routine = _routine; \
7800 + (_tq)->data = _data; \
7801 + } while (0)
7802 +
7803 +/*
7804 + * Emit code to initialise all of a tq_struct
7805 + */
7806 +#define INIT_TQUEUE(_tq, _routine, _data) \
7807 + do { \
7808 + INIT_LIST_HEAD(&(_tq)->list); \
7809 + (_tq)->sync = 0; \
7810 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7811 + } while (0)
7812 +
7813 +#endif
7814 +
7815 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7816 +
7817 +/* Power management related routines */
7818 +
7819 +static inline int
7820 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7821 +{
7822 + int i;
7823 + if (buffer) {
7824 + for (i = 0; i < 16; i++)
7825 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7826 + }
7827 + return 0;
7828 +}
7829 +
7830 +static inline int
7831 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7832 +{
7833 + int i;
7834 +
7835 + if (buffer) {
7836 + for (i = 0; i < 16; i++)
7837 + pci_write_config_dword(dev,i * 4, buffer[i]);
7838 + }
7839 + /*
7840 + * otherwise, write the context information we know from bootup.
7841 + * This works around a problem where warm-booting from Windows
7842 + * combined with a D3(hot)->D0 transition causes PCI config
7843 + * header data to be forgotten.
7844 + */
7845 + else {
7846 + for (i = 0; i < 6; i ++)
7847 + pci_write_config_dword(dev,
7848 + PCI_BASE_ADDRESS_0 + (i * 4),
7849 + pci_resource_start(dev, i));
7850 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7851 + }
7852 + return 0;
7853 +}
7854 +
7855 +#endif /* PCI power management */
7856 +
7857 +/* Old cp0 access macros deprecated in 2.4.19 */
7858 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7859 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7860 +#endif
7861 +
7862 +/* Module refcount handled internally in 2.6.x */
7863 +#ifndef SET_MODULE_OWNER
7864 +#define SET_MODULE_OWNER(dev) do {} while (0)
7865 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7866 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7867 +#else
7868 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7869 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7870 +#endif
7871 +
7872 +#ifndef SET_NETDEV_DEV
7873 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7874 +#endif
7875 +
7876 +#ifndef HAVE_FREE_NETDEV
7877 +#define free_netdev(dev) kfree(dev)
7878 +#endif
7879 +
7880 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7881 +/* struct packet_type redefined in 2.6.x */
7882 +#define af_packet_priv data
7883 +#endif
7884 +
7885 +#endif /* _linuxver_h_ */
7886 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7887 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7888 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-01-12 00:20:30.733132250 +0100
7889 @@ -0,0 +1,552 @@
7890 +/*
7891 + * HND Run Time Environment for standalone MIPS programs.
7892 + *
7893 + * Copyright 2005, Broadcom Corporation
7894 + * All Rights Reserved.
7895 + *
7896 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7897 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7898 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7899 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7900 + *
7901 + * $Id$
7902 + */
7903 +
7904 +#ifndef _MISPINC_H
7905 +#define _MISPINC_H
7906 +
7907 +
7908 +/* MIPS defines */
7909 +
7910 +#ifdef _LANGUAGE_ASSEMBLY
7911 +
7912 +/*
7913 + * Symbolic register names for 32 bit ABI
7914 + */
7915 +#define zero $0 /* wired zero */
7916 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7917 +#define v0 $2 /* return value */
7918 +#define v1 $3
7919 +#define a0 $4 /* argument registers */
7920 +#define a1 $5
7921 +#define a2 $6
7922 +#define a3 $7
7923 +#define t0 $8 /* caller saved */
7924 +#define t1 $9
7925 +#define t2 $10
7926 +#define t3 $11
7927 +#define t4 $12
7928 +#define t5 $13
7929 +#define t6 $14
7930 +#define t7 $15
7931 +#define s0 $16 /* callee saved */
7932 +#define s1 $17
7933 +#define s2 $18
7934 +#define s3 $19
7935 +#define s4 $20
7936 +#define s5 $21
7937 +#define s6 $22
7938 +#define s7 $23
7939 +#define t8 $24 /* caller saved */
7940 +#define t9 $25
7941 +#define jp $25 /* PIC jump register */
7942 +#define k0 $26 /* kernel scratch */
7943 +#define k1 $27
7944 +#define gp $28 /* global pointer */
7945 +#define sp $29 /* stack pointer */
7946 +#define fp $30 /* frame pointer */
7947 +#define s8 $30 /* same like fp! */
7948 +#define ra $31 /* return address */
7949 +
7950 +
7951 +/*
7952 + * CP0 Registers
7953 + */
7954 +
7955 +#define C0_INX $0
7956 +#define C0_RAND $1
7957 +#define C0_TLBLO0 $2
7958 +#define C0_TLBLO C0_TLBLO0
7959 +#define C0_TLBLO1 $3
7960 +#define C0_CTEXT $4
7961 +#define C0_PGMASK $5
7962 +#define C0_WIRED $6
7963 +#define C0_BADVADDR $8
7964 +#define C0_COUNT $9
7965 +#define C0_TLBHI $10
7966 +#define C0_COMPARE $11
7967 +#define C0_SR $12
7968 +#define C0_STATUS C0_SR
7969 +#define C0_CAUSE $13
7970 +#define C0_EPC $14
7971 +#define C0_PRID $15
7972 +#define C0_CONFIG $16
7973 +#define C0_LLADDR $17
7974 +#define C0_WATCHLO $18
7975 +#define C0_WATCHHI $19
7976 +#define C0_XCTEXT $20
7977 +#define C0_DIAGNOSTIC $22
7978 +#define C0_BROADCOM C0_DIAGNOSTIC
7979 +#define C0_PERFORMANCE $25
7980 +#define C0_ECC $26
7981 +#define C0_CACHEERR $27
7982 +#define C0_TAGLO $28
7983 +#define C0_TAGHI $29
7984 +#define C0_ERREPC $30
7985 +#define C0_DESAVE $31
7986 +
7987 +/*
7988 + * LEAF - declare leaf routine
7989 + */
7990 +#define LEAF(symbol) \
7991 + .globl symbol; \
7992 + .align 2; \
7993 + .type symbol,@function; \
7994 + .ent symbol,0; \
7995 +symbol: .frame sp,0,ra
7996 +
7997 +/*
7998 + * END - mark end of function
7999 + */
8000 +#define END(function) \
8001 + .end function; \
8002 + .size function,.-function
8003 +
8004 +#define _ULCAST_
8005 +
8006 +#else
8007 +
8008 +/*
8009 + * The following macros are especially useful for __asm__
8010 + * inline assembler.
8011 + */
8012 +#ifndef __STR
8013 +#define __STR(x) #x
8014 +#endif
8015 +#ifndef STR
8016 +#define STR(x) __STR(x)
8017 +#endif
8018 +
8019 +#define _ULCAST_ (unsigned long)
8020 +
8021 +
8022 +/*
8023 + * CP0 Registers
8024 + */
8025 +
8026 +#define C0_INX 0 /* CP0: TLB Index */
8027 +#define C0_RAND 1 /* CP0: TLB Random */
8028 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
8029 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
8030 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
8031 +#define C0_CTEXT 4 /* CP0: Context */
8032 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
8033 +#define C0_WIRED 6 /* CP0: TLB Wired */
8034 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
8035 +#define C0_COUNT 9 /* CP0: Count */
8036 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
8037 +#define C0_COMPARE 11 /* CP0: Compare */
8038 +#define C0_SR 12 /* CP0: Processor Status */
8039 +#define C0_STATUS C0_SR /* CP0: Processor Status */
8040 +#define C0_CAUSE 13 /* CP0: Exception Cause */
8041 +#define C0_EPC 14 /* CP0: Exception PC */
8042 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
8043 +#define C0_CONFIG 16 /* CP0: Config */
8044 +#define C0_LLADDR 17 /* CP0: LLAddr */
8045 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
8046 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
8047 +#define C0_XCTEXT 20 /* CP0: XContext */
8048 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
8049 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
8050 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
8051 +#define C0_ECC 26 /* CP0: ECC */
8052 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8053 +#define C0_TAGLO 28 /* CP0: TagLo */
8054 +#define C0_TAGHI 29 /* CP0: TagHi */
8055 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8056 +#define C0_DESAVE 31 /* CP0: DebugSave */
8057 +
8058 +#endif /* _LANGUAGE_ASSEMBLY */
8059 +
8060 +/*
8061 + * Memory segments (32bit kernel mode addresses)
8062 + */
8063 +#undef KUSEG
8064 +#undef KSEG0
8065 +#undef KSEG1
8066 +#undef KSEG2
8067 +#undef KSEG3
8068 +#define KUSEG 0x00000000
8069 +#define KSEG0 0x80000000
8070 +#define KSEG1 0xa0000000
8071 +#define KSEG2 0xc0000000
8072 +#define KSEG3 0xe0000000
8073 +#define PHYSADDR_MASK 0x1fffffff
8074 +
8075 +/*
8076 + * Map an address to a certain kernel segment
8077 + */
8078 +#undef PHYSADDR
8079 +#undef KSEG0ADDR
8080 +#undef KSEG1ADDR
8081 +#undef KSEG2ADDR
8082 +#undef KSEG3ADDR
8083 +
8084 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8085 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8086 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8087 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8088 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8089 +
8090 +
8091 +#ifndef Index_Invalidate_I
8092 +/*
8093 + * Cache Operations
8094 + */
8095 +#define Index_Invalidate_I 0x00
8096 +#define Index_Writeback_Inv_D 0x01
8097 +#define Index_Invalidate_SI 0x02
8098 +#define Index_Writeback_Inv_SD 0x03
8099 +#define Index_Load_Tag_I 0x04
8100 +#define Index_Load_Tag_D 0x05
8101 +#define Index_Load_Tag_SI 0x06
8102 +#define Index_Load_Tag_SD 0x07
8103 +#define Index_Store_Tag_I 0x08
8104 +#define Index_Store_Tag_D 0x09
8105 +#define Index_Store_Tag_SI 0x0A
8106 +#define Index_Store_Tag_SD 0x0B
8107 +#define Create_Dirty_Excl_D 0x0d
8108 +#define Create_Dirty_Excl_SD 0x0f
8109 +#define Hit_Invalidate_I 0x10
8110 +#define Hit_Invalidate_D 0x11
8111 +#define Hit_Invalidate_SI 0x12
8112 +#define Hit_Invalidate_SD 0x13
8113 +#define Fill_I 0x14
8114 +#define Hit_Writeback_Inv_D 0x15
8115 + /* 0x16 is unused */
8116 +#define Hit_Writeback_Inv_SD 0x17
8117 +#define R5K_Page_Invalidate_S 0x17
8118 +#define Hit_Writeback_I 0x18
8119 +#define Hit_Writeback_D 0x19
8120 + /* 0x1a is unused */
8121 +#define Hit_Writeback_SD 0x1b
8122 + /* 0x1c is unused */
8123 + /* 0x1e is unused */
8124 +#define Hit_Set_Virtual_SI 0x1e
8125 +#define Hit_Set_Virtual_SD 0x1f
8126 +#endif
8127 +
8128 +
8129 +/*
8130 + * R4x00 interrupt enable / cause bits
8131 + */
8132 +#define IE_SW0 (_ULCAST_(1) << 8)
8133 +#define IE_SW1 (_ULCAST_(1) << 9)
8134 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8135 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8136 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8137 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8138 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8139 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8140 +
8141 +#ifndef ST0_UM
8142 +/*
8143 + * Bitfields in the mips32 cp0 status register
8144 + */
8145 +#define ST0_IE 0x00000001
8146 +#define ST0_EXL 0x00000002
8147 +#define ST0_ERL 0x00000004
8148 +#define ST0_UM 0x00000010
8149 +#define ST0_SWINT0 0x00000100
8150 +#define ST0_SWINT1 0x00000200
8151 +#define ST0_HWINT0 0x00000400
8152 +#define ST0_HWINT1 0x00000800
8153 +#define ST0_HWINT2 0x00001000
8154 +#define ST0_HWINT3 0x00002000
8155 +#define ST0_HWINT4 0x00004000
8156 +#define ST0_HWINT5 0x00008000
8157 +#define ST0_IM 0x0000ff00
8158 +#define ST0_NMI 0x00080000
8159 +#define ST0_SR 0x00100000
8160 +#define ST0_TS 0x00200000
8161 +#define ST0_BEV 0x00400000
8162 +#define ST0_RE 0x02000000
8163 +#define ST0_RP 0x08000000
8164 +#define ST0_CU 0xf0000000
8165 +#define ST0_CU0 0x10000000
8166 +#define ST0_CU1 0x20000000
8167 +#define ST0_CU2 0x40000000
8168 +#define ST0_CU3 0x80000000
8169 +#endif
8170 +
8171 +
8172 +/*
8173 + * Bitfields in the mips32 cp0 cause register
8174 + */
8175 +#define C_EXC 0x0000007c
8176 +#define C_EXC_SHIFT 2
8177 +#define C_INT 0x0000ff00
8178 +#define C_INT_SHIFT 8
8179 +#define C_SW0 (_ULCAST_(1) << 8)
8180 +#define C_SW1 (_ULCAST_(1) << 9)
8181 +#define C_IRQ0 (_ULCAST_(1) << 10)
8182 +#define C_IRQ1 (_ULCAST_(1) << 11)
8183 +#define C_IRQ2 (_ULCAST_(1) << 12)
8184 +#define C_IRQ3 (_ULCAST_(1) << 13)
8185 +#define C_IRQ4 (_ULCAST_(1) << 14)
8186 +#define C_IRQ5 (_ULCAST_(1) << 15)
8187 +#define C_WP 0x00400000
8188 +#define C_IV 0x00800000
8189 +#define C_CE 0x30000000
8190 +#define C_CE_SHIFT 28
8191 +#define C_BD 0x80000000
8192 +
8193 +/* Values in C_EXC */
8194 +#define EXC_INT 0
8195 +#define EXC_TLBM 1
8196 +#define EXC_TLBL 2
8197 +#define EXC_TLBS 3
8198 +#define EXC_AEL 4
8199 +#define EXC_AES 5
8200 +#define EXC_IBE 6
8201 +#define EXC_DBE 7
8202 +#define EXC_SYS 8
8203 +#define EXC_BPT 9
8204 +#define EXC_RI 10
8205 +#define EXC_CU 11
8206 +#define EXC_OV 12
8207 +#define EXC_TR 13
8208 +#define EXC_WATCH 23
8209 +#define EXC_MCHK 24
8210 +
8211 +
8212 +/*
8213 + * Bits in the cp0 config register.
8214 + */
8215 +#define CONF_CM_CACHABLE_NO_WA 0
8216 +#define CONF_CM_CACHABLE_WA 1
8217 +#define CONF_CM_UNCACHED 2
8218 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8219 +#define CONF_CM_CACHABLE_CE 4
8220 +#define CONF_CM_CACHABLE_COW 5
8221 +#define CONF_CM_CACHABLE_CUW 6
8222 +#define CONF_CM_CACHABLE_ACCELERATED 7
8223 +#define CONF_CM_CMASK 7
8224 +#define CONF_CU (_ULCAST_(1) << 3)
8225 +#define CONF_DB (_ULCAST_(1) << 4)
8226 +#define CONF_IB (_ULCAST_(1) << 5)
8227 +#define CONF_SE (_ULCAST_(1) << 12)
8228 +#define CONF_SC (_ULCAST_(1) << 17)
8229 +#define CONF_AC (_ULCAST_(1) << 23)
8230 +#define CONF_HALT (_ULCAST_(1) << 25)
8231 +
8232 +
8233 +/*
8234 + * Bits in the cp0 config register select 1.
8235 + */
8236 +#define CONF1_FP 0x00000001 /* FPU present */
8237 +#define CONF1_EP 0x00000002 /* EJTAG present */
8238 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8239 +#define CONF1_WR 0x00000008 /* Watch registers present */
8240 +#define CONF1_PC 0x00000010 /* Performance counters present */
8241 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8242 +#define CONF1_DA_MASK 0x00000380
8243 +#define CONF1_DA_BASE 1
8244 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8245 +#define CONF1_DL_MASK 0x00001c00
8246 +#define CONF1_DL_BASE 2
8247 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8248 +#define CONF1_DS_MASK 0x0000e000
8249 +#define CONF1_DS_BASE 64
8250 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8251 +#define CONF1_IA_MASK 0x00070000
8252 +#define CONF1_IA_BASE 1
8253 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8254 +#define CONF1_IL_MASK 0x00380000
8255 +#define CONF1_IL_BASE 2
8256 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8257 +#define CONF1_IS_MASK 0x01c00000
8258 +#define CONF1_IS_BASE 64
8259 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8260 +#define CONF1_MS_SHIFT 25
8261 +
8262 +/* PRID register */
8263 +#define PRID_COPT_MASK 0xff000000
8264 +#define PRID_COMP_MASK 0x00ff0000
8265 +#define PRID_IMP_MASK 0x0000ff00
8266 +#define PRID_REV_MASK 0x000000ff
8267 +
8268 +#define PRID_COMP_LEGACY 0x000000
8269 +#define PRID_COMP_MIPS 0x010000
8270 +#define PRID_COMP_BROADCOM 0x020000
8271 +#define PRID_COMP_ALCHEMY 0x030000
8272 +#define PRID_COMP_SIBYTE 0x040000
8273 +#define PRID_IMP_BCM4710 0x4000
8274 +#define PRID_IMP_BCM3302 0x9000
8275 +#define PRID_IMP_BCM3303 0x9100
8276 +
8277 +#define PRID_IMP_UNKNOWN 0xff00
8278 +
8279 +#define BCM330X(id) \
8280 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8281 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8282 +
8283 +/* Bits in C0_BROADCOM */
8284 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8285 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8286 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8287 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8288 +
8289 +/* PreFetch Cache aka Read Ahead Cache */
8290 +
8291 +#define PFC_CR0 0xff400000 /* control reg 0 */
8292 +#define PFC_CR1 0xff400004 /* control reg 1 */
8293 +
8294 +/* PFC operations */
8295 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8296 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8297 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8298 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8299 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8300 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8301 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8302 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8303 +#define PFC_BRR 0x40000000 /* Bus error indication */
8304 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8305 +
8306 +/* Handy defaults */
8307 +#define PFC_DISABLED 0
8308 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8309 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8310 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8311 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8312 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8313 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8314 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8315 +
8316 +
8317 +/*
8318 + * These are the UART port assignments, expressed as offsets from the base
8319 + * register. These assignments should hold for any serial port based on
8320 + * a 8250, 16450, or 16550(A).
8321 + */
8322 +
8323 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8324 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8325 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8326 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8327 +#define UART_LCR 3 /* Out: Line Control Register */
8328 +#define UART_MCR 4 /* Out: Modem Control Register */
8329 +#define UART_LSR 5 /* In: Line Status Register */
8330 +#define UART_MSR 6 /* In: Modem Status Register */
8331 +#define UART_SCR 7 /* I/O: Scratch Register */
8332 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8333 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8334 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8335 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8336 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8337 +
8338 +
8339 +#ifndef _LANGUAGE_ASSEMBLY
8340 +
8341 +/*
8342 + * Macros to access the system control coprocessor
8343 + */
8344 +
8345 +#define MFC0(source, sel) \
8346 +({ \
8347 + int __res; \
8348 + __asm__ __volatile__( \
8349 + ".set\tnoreorder\n\t" \
8350 + ".set\tnoat\n\t" \
8351 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8352 + "move\t%0,$1\n\t" \
8353 + ".set\tat\n\t" \
8354 + ".set\treorder" \
8355 + :"=r" (__res) \
8356 + : \
8357 + :"$1"); \
8358 + __res; \
8359 +})
8360 +
8361 +#define MTC0(source, sel, value) \
8362 +do { \
8363 + __asm__ __volatile__( \
8364 + ".set\tnoreorder\n\t" \
8365 + ".set\tnoat\n\t" \
8366 + "move\t$1,%z0\n\t" \
8367 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8368 + ".set\tat\n\t" \
8369 + ".set\treorder" \
8370 + : \
8371 + :"jr" (value) \
8372 + :"$1"); \
8373 +} while (0)
8374 +
8375 +#define get_c0_count() \
8376 +({ \
8377 + int __res; \
8378 + __asm__ __volatile__( \
8379 + ".set\tnoreorder\n\t" \
8380 + ".set\tnoat\n\t" \
8381 + "mfc0\t%0,$9\n\t" \
8382 + ".set\tat\n\t" \
8383 + ".set\treorder" \
8384 + :"=r" (__res)); \
8385 + __res; \
8386 +})
8387 +
8388 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8389 +{
8390 + uint lsz, sets, ways;
8391 +
8392 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8393 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8394 + lsz = CONF1_IL_BASE << lsz;
8395 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8396 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8397 + *size = lsz * sets * ways;
8398 + *lsize = lsz;
8399 +}
8400 +
8401 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8402 +{
8403 + uint lsz, sets, ways;
8404 +
8405 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8406 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8407 + lsz = CONF1_DL_BASE << lsz;
8408 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8409 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8410 + *size = lsz * sets * ways;
8411 + *lsize = lsz;
8412 +}
8413 +
8414 +#define cache_op(base, op) \
8415 + __asm__ __volatile__(" \
8416 + .set noreorder; \
8417 + .set mips3; \
8418 + cache %1, (%0); \
8419 + .set mips0; \
8420 + .set reorder" \
8421 + : \
8422 + : "r" (base), \
8423 + "i" (op));
8424 +
8425 +#define cache_unroll4(base, delta, op) \
8426 + __asm__ __volatile__(" \
8427 + .set noreorder; \
8428 + .set mips3; \
8429 + cache %1,0(%0); \
8430 + cache %1,delta(%0); \
8431 + cache %1,(2 * delta)(%0); \
8432 + cache %1,(3 * delta)(%0); \
8433 + .set mips0; \
8434 + .set reorder" \
8435 + : \
8436 + : "r" (base), \
8437 + "i" (op));
8438 +
8439 +#endif /* !_LANGUAGE_ASSEMBLY */
8440 +
8441 +#endif /* _MISPINC_H */
8442 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8443 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8444 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-01-12 00:20:30.733132250 +0100
8445 @@ -0,0 +1,42 @@
8446 +/*
8447 + * OS Abstraction Layer
8448 + *
8449 + * Copyright 2005, Broadcom Corporation
8450 + * All Rights Reserved.
8451 + *
8452 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8453 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8454 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8455 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8456 + * $Id$
8457 + */
8458 +
8459 +#ifndef _osl_h_
8460 +#define _osl_h_
8461 +
8462 +/* osl handle type forward declaration */
8463 +typedef struct os_handle osl_t;
8464 +
8465 +#if defined(linux)
8466 +#include <linux_osl.h>
8467 +#elif defined(NDIS)
8468 +#include <ndis_osl.h>
8469 +#elif defined(_CFE_)
8470 +#include <cfe_osl.h>
8471 +#elif defined(_HNDRTE_)
8472 +#include <hndrte_osl.h>
8473 +#elif defined(_MINOSL_)
8474 +#include <min_osl.h>
8475 +#elif PMON
8476 +#include <pmon_osl.h>
8477 +#elif defined(MACOSX)
8478 +#include <macosx_osl.h>
8479 +#else
8480 +#error "Unsupported OSL requested"
8481 +#endif
8482 +
8483 +/* handy */
8484 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8485 +#define MAXPRIO 7 /* 0-7 */
8486 +
8487 +#endif /* _osl_h_ */
8488 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8489 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8490 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-01-12 00:20:30.733132250 +0100
8491 @@ -0,0 +1,398 @@
8492 +/*
8493 + * pcicfg.h: PCI configuration constants and structures.
8494 + *
8495 + * Copyright 2005, Broadcom Corporation
8496 + * All Rights Reserved.
8497 + *
8498 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8499 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8500 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8501 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8502 + *
8503 + * $Id$
8504 + */
8505 +
8506 +#ifndef _h_pci_
8507 +#define _h_pci_
8508 +
8509 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8510 +#ifndef PCI_MAX_BUS
8511 +#define PCI_MAX_BUS 0x100
8512 +#endif
8513 +#ifndef PCI_MAX_DEVICES
8514 +#define PCI_MAX_DEVICES 0x20
8515 +#endif
8516 +#ifndef PCI_MAX_FUNCTION
8517 +#define PCI_MAX_FUNCTION 0x8
8518 +#endif
8519 +
8520 +#ifndef PCI_INVALID_VENDORID
8521 +#define PCI_INVALID_VENDORID 0xffff
8522 +#endif
8523 +#ifndef PCI_INVALID_DEVICEID
8524 +#define PCI_INVALID_DEVICEID 0xffff
8525 +#endif
8526 +
8527 +
8528 +/* Convert between bus-slot-function-register and config addresses */
8529 +
8530 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8531 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8532 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8533 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8534 +
8535 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8536 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8537 +#define PCICFG_FUN_MASK 7 /* Function mask */
8538 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8539 +
8540 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8541 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8542 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8543 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8544 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8545 +
8546 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8547 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8548 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8549 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8550 +
8551 +/* The actual config space */
8552 +
8553 +#define PCI_BAR_MAX 6
8554 +
8555 +#define PCI_ROM_BAR 8
8556 +
8557 +#define PCR_RSVDA_MAX 2
8558 +
8559 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8560 +
8561 +#define PCI_CAPPTR_PRESENT 0x0010
8562 +
8563 +typedef struct _pci_config_regs {
8564 + unsigned short vendor;
8565 + unsigned short device;
8566 + unsigned short command;
8567 + unsigned short status;
8568 + unsigned char rev_id;
8569 + unsigned char prog_if;
8570 + unsigned char sub_class;
8571 + unsigned char base_class;
8572 + unsigned char cache_line_size;
8573 + unsigned char latency_timer;
8574 + unsigned char header_type;
8575 + unsigned char bist;
8576 + unsigned long base[PCI_BAR_MAX];
8577 + unsigned long cardbus_cis;
8578 + unsigned short subsys_vendor;
8579 + unsigned short subsys_id;
8580 + unsigned long baserom;
8581 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8582 + unsigned char int_line;
8583 + unsigned char int_pin;
8584 + unsigned char min_gnt;
8585 + unsigned char max_lat;
8586 + unsigned char dev_dep[192];
8587 +} pci_config_regs;
8588 +
8589 +#define SZPCR (sizeof (pci_config_regs))
8590 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8591 +
8592 +/* A structure for the config registers is nice, but in most
8593 + * systems the config space is not memory mapped, so we need
8594 + * filed offsetts. :-(
8595 + */
8596 +#define PCI_CFG_VID 0
8597 +#define PCI_CFG_DID 2
8598 +#define PCI_CFG_CMD 4
8599 +#define PCI_CFG_STAT 6
8600 +#define PCI_CFG_REV 8
8601 +#define PCI_CFG_PROGIF 9
8602 +#define PCI_CFG_SUBCL 0xa
8603 +#define PCI_CFG_BASECL 0xb
8604 +#define PCI_CFG_CLSZ 0xc
8605 +#define PCI_CFG_LATTIM 0xd
8606 +#define PCI_CFG_HDR 0xe
8607 +#define PCI_CFG_BIST 0xf
8608 +#define PCI_CFG_BAR0 0x10
8609 +#define PCI_CFG_BAR1 0x14
8610 +#define PCI_CFG_BAR2 0x18
8611 +#define PCI_CFG_BAR3 0x1c
8612 +#define PCI_CFG_BAR4 0x20
8613 +#define PCI_CFG_BAR5 0x24
8614 +#define PCI_CFG_CIS 0x28
8615 +#define PCI_CFG_SVID 0x2c
8616 +#define PCI_CFG_SSID 0x2e
8617 +#define PCI_CFG_ROMBAR 0x30
8618 +#define PCI_CFG_CAPPTR 0x34
8619 +#define PCI_CFG_INT 0x3c
8620 +#define PCI_CFG_PIN 0x3d
8621 +#define PCI_CFG_MINGNT 0x3e
8622 +#define PCI_CFG_MAXLAT 0x3f
8623 +
8624 +/* Classes and subclasses */
8625 +
8626 +typedef enum {
8627 + PCI_CLASS_OLD = 0,
8628 + PCI_CLASS_DASDI,
8629 + PCI_CLASS_NET,
8630 + PCI_CLASS_DISPLAY,
8631 + PCI_CLASS_MMEDIA,
8632 + PCI_CLASS_MEMORY,
8633 + PCI_CLASS_BRIDGE,
8634 + PCI_CLASS_COMM,
8635 + PCI_CLASS_BASE,
8636 + PCI_CLASS_INPUT,
8637 + PCI_CLASS_DOCK,
8638 + PCI_CLASS_CPU,
8639 + PCI_CLASS_SERIAL,
8640 + PCI_CLASS_INTELLIGENT = 0xe,
8641 + PCI_CLASS_SATELLITE,
8642 + PCI_CLASS_CRYPT,
8643 + PCI_CLASS_DSP,
8644 + PCI_CLASS_MAX
8645 +} pci_classes;
8646 +
8647 +typedef enum {
8648 + PCI_DASDI_SCSI,
8649 + PCI_DASDI_IDE,
8650 + PCI_DASDI_FLOPPY,
8651 + PCI_DASDI_IPI,
8652 + PCI_DASDI_RAID,
8653 + PCI_DASDI_OTHER = 0x80
8654 +} pci_dasdi_subclasses;
8655 +
8656 +typedef enum {
8657 + PCI_NET_ETHER,
8658 + PCI_NET_TOKEN,
8659 + PCI_NET_FDDI,
8660 + PCI_NET_ATM,
8661 + PCI_NET_OTHER = 0x80
8662 +} pci_net_subclasses;
8663 +
8664 +typedef enum {
8665 + PCI_DISPLAY_VGA,
8666 + PCI_DISPLAY_XGA,
8667 + PCI_DISPLAY_3D,
8668 + PCI_DISPLAY_OTHER = 0x80
8669 +} pci_display_subclasses;
8670 +
8671 +typedef enum {
8672 + PCI_MMEDIA_VIDEO,
8673 + PCI_MMEDIA_AUDIO,
8674 + PCI_MMEDIA_PHONE,
8675 + PCI_MEDIA_OTHER = 0x80
8676 +} pci_mmedia_subclasses;
8677 +
8678 +typedef enum {
8679 + PCI_MEMORY_RAM,
8680 + PCI_MEMORY_FLASH,
8681 + PCI_MEMORY_OTHER = 0x80
8682 +} pci_memory_subclasses;
8683 +
8684 +typedef enum {
8685 + PCI_BRIDGE_HOST,
8686 + PCI_BRIDGE_ISA,
8687 + PCI_BRIDGE_EISA,
8688 + PCI_BRIDGE_MC,
8689 + PCI_BRIDGE_PCI,
8690 + PCI_BRIDGE_PCMCIA,
8691 + PCI_BRIDGE_NUBUS,
8692 + PCI_BRIDGE_CARDBUS,
8693 + PCI_BRIDGE_RACEWAY,
8694 + PCI_BRIDGE_OTHER = 0x80
8695 +} pci_bridge_subclasses;
8696 +
8697 +typedef enum {
8698 + PCI_COMM_UART,
8699 + PCI_COMM_PARALLEL,
8700 + PCI_COMM_MULTIUART,
8701 + PCI_COMM_MODEM,
8702 + PCI_COMM_OTHER = 0x80
8703 +} pci_comm_subclasses;
8704 +
8705 +typedef enum {
8706 + PCI_BASE_PIC,
8707 + PCI_BASE_DMA,
8708 + PCI_BASE_TIMER,
8709 + PCI_BASE_RTC,
8710 + PCI_BASE_PCI_HOTPLUG,
8711 + PCI_BASE_OTHER = 0x80
8712 +} pci_base_subclasses;
8713 +
8714 +typedef enum {
8715 + PCI_INPUT_KBD,
8716 + PCI_INPUT_PEN,
8717 + PCI_INPUT_MOUSE,
8718 + PCI_INPUT_SCANNER,
8719 + PCI_INPUT_GAMEPORT,
8720 + PCI_INPUT_OTHER = 0x80
8721 +} pci_input_subclasses;
8722 +
8723 +typedef enum {
8724 + PCI_DOCK_GENERIC,
8725 + PCI_DOCK_OTHER = 0x80
8726 +} pci_dock_subclasses;
8727 +
8728 +typedef enum {
8729 + PCI_CPU_386,
8730 + PCI_CPU_486,
8731 + PCI_CPU_PENTIUM,
8732 + PCI_CPU_ALPHA = 0x10,
8733 + PCI_CPU_POWERPC = 0x20,
8734 + PCI_CPU_MIPS = 0x30,
8735 + PCI_CPU_COPROC = 0x40,
8736 + PCI_CPU_OTHER = 0x80
8737 +} pci_cpu_subclasses;
8738 +
8739 +typedef enum {
8740 + PCI_SERIAL_IEEE1394,
8741 + PCI_SERIAL_ACCESS,
8742 + PCI_SERIAL_SSA,
8743 + PCI_SERIAL_USB,
8744 + PCI_SERIAL_FIBER,
8745 + PCI_SERIAL_SMBUS,
8746 + PCI_SERIAL_OTHER = 0x80
8747 +} pci_serial_subclasses;
8748 +
8749 +typedef enum {
8750 + PCI_INTELLIGENT_I2O,
8751 +} pci_intelligent_subclasses;
8752 +
8753 +typedef enum {
8754 + PCI_SATELLITE_TV,
8755 + PCI_SATELLITE_AUDIO,
8756 + PCI_SATELLITE_VOICE,
8757 + PCI_SATELLITE_DATA,
8758 + PCI_SATELLITE_OTHER = 0x80
8759 +} pci_satellite_subclasses;
8760 +
8761 +typedef enum {
8762 + PCI_CRYPT_NETWORK,
8763 + PCI_CRYPT_ENTERTAINMENT,
8764 + PCI_CRYPT_OTHER = 0x80
8765 +} pci_crypt_subclasses;
8766 +
8767 +typedef enum {
8768 + PCI_DSP_DPIO,
8769 + PCI_DSP_OTHER = 0x80
8770 +} pci_dsp_subclasses;
8771 +
8772 +/* Header types */
8773 +typedef enum {
8774 + PCI_HEADER_NORMAL,
8775 + PCI_HEADER_BRIDGE,
8776 + PCI_HEADER_CARDBUS
8777 +} pci_header_types;
8778 +
8779 +
8780 +/* Overlay for a PCI-to-PCI bridge */
8781 +
8782 +#define PPB_RSVDA_MAX 2
8783 +#define PPB_RSVDD_MAX 8
8784 +
8785 +typedef struct _ppb_config_regs {
8786 + unsigned short vendor;
8787 + unsigned short device;
8788 + unsigned short command;
8789 + unsigned short status;
8790 + unsigned char rev_id;
8791 + unsigned char prog_if;
8792 + unsigned char sub_class;
8793 + unsigned char base_class;
8794 + unsigned char cache_line_size;
8795 + unsigned char latency_timer;
8796 + unsigned char header_type;
8797 + unsigned char bist;
8798 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8799 + unsigned char prim_bus;
8800 + unsigned char sec_bus;
8801 + unsigned char sub_bus;
8802 + unsigned char sec_lat;
8803 + unsigned char io_base;
8804 + unsigned char io_lim;
8805 + unsigned short sec_status;
8806 + unsigned short mem_base;
8807 + unsigned short mem_lim;
8808 + unsigned short pf_mem_base;
8809 + unsigned short pf_mem_lim;
8810 + unsigned long pf_mem_base_hi;
8811 + unsigned long pf_mem_lim_hi;
8812 + unsigned short io_base_hi;
8813 + unsigned short io_lim_hi;
8814 + unsigned short subsys_vendor;
8815 + unsigned short subsys_id;
8816 + unsigned long rsvd_b;
8817 + unsigned char rsvd_c;
8818 + unsigned char int_pin;
8819 + unsigned short bridge_ctrl;
8820 + unsigned char chip_ctrl;
8821 + unsigned char diag_ctrl;
8822 + unsigned short arb_ctrl;
8823 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8824 + unsigned char dev_dep[192];
8825 +} ppb_config_regs;
8826 +
8827 +
8828 +/* PCI CAPABILITY DEFINES */
8829 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8830 +#define PCI_CAP_MSICAP_ID 0x05
8831 +
8832 +/* Data structure to define the Message Signalled Interrupt facility
8833 + * Valid for PCI and PCIE configurations */
8834 +typedef struct _pciconfig_cap_msi {
8835 + unsigned char capID;
8836 + unsigned char nextptr;
8837 + unsigned short msgctrl;
8838 + unsigned int msgaddr;
8839 +} pciconfig_cap_msi;
8840 +
8841 +/* Data structure to define the Power managment facility
8842 + * Valid for PCI and PCIE configurations */
8843 +typedef struct _pciconfig_cap_pwrmgmt {
8844 + unsigned char capID;
8845 + unsigned char nextptr;
8846 + unsigned short pme_cap;
8847 + unsigned short pme_sts_ctrl;
8848 + unsigned char pme_bridge_ext;
8849 + unsigned char data;
8850 +} pciconfig_cap_pwrmgmt;
8851 +
8852 +/* Everything below is BRCM HND proprietary */
8853 +
8854 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8855 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8856 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8857 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8858 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8859 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8860 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8861 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8862 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8863 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8864 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8865 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8866 +
8867 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8868 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8869 +
8870 +/* PCI_INT_STATUS */
8871 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8872 +
8873 +/* PCI_INT_MASK */
8874 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8875 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8876 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8877 +
8878 +/* PCI_SPROM_CONTROL */
8879 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8880 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8881 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8882 +
8883 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8884 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8885 +
8886 +/* PCI_CFG_CMD_STAT */
8887 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8888 +
8889 +#endif
8890 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8891 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8892 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2006-01-12 00:20:30.733132250 +0100
8893 @@ -0,0 +1,145 @@
8894 +/*******************************************************************************
8895 + * $Id$
8896 + * Copyright 2001-2003, Broadcom Corporation
8897 + * All Rights Reserved.
8898 + *
8899 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8900 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8901 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8902 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8903 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8904 + ******************************************************************************/
8905 +
8906 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8907 +#define _NET_ETHERNET_H_
8908 +
8909 +#ifndef _TYPEDEFS_H_
8910 +#include "typedefs.h"
8911 +#endif
8912 +
8913 +#if defined(__GNUC__)
8914 +#define PACKED __attribute__((packed))
8915 +#else
8916 +#define PACKED
8917 +#endif
8918 +
8919 +/*
8920 + * The number of bytes in an ethernet (MAC) address.
8921 + */
8922 +#define ETHER_ADDR_LEN 6
8923 +
8924 +/*
8925 + * The number of bytes in the type field.
8926 + */
8927 +#define ETHER_TYPE_LEN 2
8928 +
8929 +/*
8930 + * The number of bytes in the trailing CRC field.
8931 + */
8932 +#define ETHER_CRC_LEN 4
8933 +
8934 +/*
8935 + * The length of the combined header.
8936 + */
8937 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8938 +
8939 +/*
8940 + * The minimum packet length.
8941 + */
8942 +#define ETHER_MIN_LEN 64
8943 +
8944 +/*
8945 + * The minimum packet user data length.
8946 + */
8947 +#define ETHER_MIN_DATA 46
8948 +
8949 +/*
8950 + * The maximum packet length.
8951 + */
8952 +#define ETHER_MAX_LEN 1518
8953 +
8954 +/*
8955 + * The maximum packet user data length.
8956 + */
8957 +#define ETHER_MAX_DATA 1500
8958 +
8959 +/*
8960 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8961 + */
8962 +#define VLAN_TAG 0x8100
8963 +
8964 +/*
8965 + * Located after dest & src address in ether header.
8966 + */
8967 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8968 +
8969 +/*
8970 + * 4 bytes of vlan field info.
8971 + */
8972 +#define VLAN_FIELDS_SIZE 4
8973 +
8974 +/* location of pri bits in 16-bit vlan fields */
8975 +#define VLAN_PRI_SHIFT 13
8976 +
8977 +/* 3 bits of priority */
8978 +#define VLAN_PRI_MASK 7
8979 +
8980 +/* 802.1X ethertype */
8981 +#define ETHER_TYPE_802_1X 0x888e
8982 +
8983 +/*
8984 + * A macro to validate a length with
8985 + */
8986 +#define ETHER_IS_VALID_LEN(foo) \
8987 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8988 +
8989 +
8990 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8991 +/*
8992 + * Structure of a 10Mb/s Ethernet header.
8993 + */
8994 +struct ether_header {
8995 + uint8 ether_dhost[ETHER_ADDR_LEN];
8996 + uint8 ether_shost[ETHER_ADDR_LEN];
8997 + uint16 ether_type;
8998 +} PACKED ;
8999 +
9000 +/*
9001 + * Structure of a 48-bit Ethernet address.
9002 + */
9003 +struct ether_addr {
9004 + uint8 octet[ETHER_ADDR_LEN];
9005 +} PACKED ;
9006 +#endif
9007 +
9008 +/*
9009 + * Takes a pointer, returns true if a 48-bit multicast address
9010 + * (including broadcast, since it is all ones)
9011 + */
9012 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
9013 +
9014 +/*
9015 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
9016 + */
9017 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9018 + ((uint8 *)(ea))[1] & \
9019 + ((uint8 *)(ea))[2] & \
9020 + ((uint8 *)(ea))[3] & \
9021 + ((uint8 *)(ea))[4] & \
9022 + ((uint8 *)(ea))[5]) == 0xff)
9023 +
9024 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9025 +
9026 +/*
9027 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9028 + */
9029 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9030 + ((uint8 *)(ea))[1] | \
9031 + ((uint8 *)(ea))[2] | \
9032 + ((uint8 *)(ea))[3] | \
9033 + ((uint8 *)(ea))[4] | \
9034 + ((uint8 *)(ea))[5]) == 0)
9035 +
9036 +#undef PACKED
9037 +
9038 +#endif /* _NET_ETHERNET_H_ */
9039 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
9040 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9041 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2006-01-12 00:20:30.733132250 +0100
9042 @@ -0,0 +1,103 @@
9043 +#ifndef _S5_H_
9044 +#define _S5_H_
9045 +/*
9046 + * Copyright 2003, Broadcom Corporation
9047 + * All Rights Reserved.
9048 + *
9049 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9050 + * and MIPS3301 (R4K) System Address Space
9051 + *
9052 + * This program is free software; you can redistribute it and/or
9053 + * modify it under the terms of the GNU General Public License as
9054 + * published by the Free Software Foundation, located in the file
9055 + * LICENSE.
9056 + *
9057 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9058 + *
9059 + */
9060 +
9061 +/* BCM5365 Address map */
9062 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9063 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9064 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9065 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9066 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9067 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9068 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9069 +
9070 +/* BCM5365 Core register space */
9071 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9072 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9073 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9074 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9075 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9076 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9077 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9078 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9079 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9080 +
9081 +/* COM Ports 1/2 */
9082 +#define BCM5365_UART (BCM5365_REG_UARTS)
9083 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9084 +
9085 +/* Registers common to MIPS33 Core used in 5365 */
9086 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9087 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9088 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9089 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9090 +
9091 +/* Internal Core Sonics Backplane Devices */
9092 +#define INTERNAL_UART_COM1 BCM5365_UART
9093 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9094 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9095 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9096 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9097 +#define SB_REG_USB BCM5365_REG_USB
9098 +#define SB_REG_PCI BCM5365_REG_PCI
9099 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9100 +#define SB_REG_MEMC BCM5365_REG_MEMC
9101 +#define SB_REG_MEMC_OFF 0x6000
9102 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9103 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9104 +
9105 +/*
9106 + * XXX
9107 + * 5365-specific backplane interrupt flag numbers. This should be done
9108 + * dynamically instead.
9109 + */
9110 +#define SBFLAG_PCI 0
9111 +#define SBFLAG_ENET0 1
9112 +#define SBFLAG_ILINE20 2
9113 +#define SBFLAG_CODEC 3
9114 +#define SBFLAG_USB 4
9115 +#define SBFLAG_EXTIF 5
9116 +#define SBFLAG_ENET1 6
9117 +
9118 +/* BCM95365 Local Bus devices */
9119 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9120 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9121 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9122 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9123 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9124 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9125 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9126 +
9127 +/* Write to DLR2416 VFD Display character RAM */
9128 +#define LED_REG(x) \
9129 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9130 +
9131 +#ifdef CONFIG_VSIM
9132 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9133 + } while (0)
9134 +#else
9135 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9136 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9137 + *((int *)0xa0002ff8) = (trval); } while (0)
9138 +#endif
9139 +
9140 +/* BCM9536R Local Bus devices */
9141 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9142 +
9143 +
9144 +
9145 +#endif /*!_S5_H_ */
9146 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9147 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9148 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-01-12 00:20:30.733132250 +0100
9149 @@ -0,0 +1,440 @@
9150 +/*
9151 + * SiliconBackplane Chipcommon core hardware definitions.
9152 + *
9153 + * The chipcommon core provides chip identification, SB control,
9154 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9155 + * gpio interface, extbus, and support for serial and parallel flashes.
9156 + *
9157 + * $Id$
9158 + * Copyright 2005, Broadcom Corporation
9159 + * All Rights Reserved.
9160 + *
9161 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9162 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9163 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9164 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9165 + *
9166 + */
9167 +
9168 +#ifndef _SBCHIPC_H
9169 +#define _SBCHIPC_H
9170 +
9171 +
9172 +#ifndef _LANGUAGE_ASSEMBLY
9173 +
9174 +/* cpp contortions to concatenate w/arg prescan */
9175 +#ifndef PAD
9176 +#define _PADLINE(line) pad ## line
9177 +#define _XSTR(line) _PADLINE(line)
9178 +#define PAD _XSTR(__LINE__)
9179 +#endif /* PAD */
9180 +
9181 +typedef volatile struct {
9182 + uint32 chipid; /* 0x0 */
9183 + uint32 capabilities;
9184 + uint32 corecontrol; /* corerev >= 1 */
9185 + uint32 bist;
9186 +
9187 + /* OTP */
9188 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9189 + uint32 otpcontrol;
9190 + uint32 otpprog;
9191 + uint32 PAD;
9192 +
9193 + /* Interrupt control */
9194 + uint32 intstatus; /* 0x20 */
9195 + uint32 intmask;
9196 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9197 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9198 +
9199 + /* Jtag Master */
9200 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9201 + uint32 jtagir;
9202 + uint32 jtagdr;
9203 + uint32 jtagctrl;
9204 +
9205 + /* serial flash interface registers */
9206 + uint32 flashcontrol; /* 0x40 */
9207 + uint32 flashaddress;
9208 + uint32 flashdata;
9209 + uint32 PAD[1];
9210 +
9211 + /* Silicon backplane configuration broadcast control */
9212 + uint32 broadcastaddress; /* 0x50 */
9213 + uint32 broadcastdata;
9214 + uint32 PAD[2];
9215 +
9216 + /* gpio - cleared only by power-on-reset */
9217 + uint32 gpioin; /* 0x60 */
9218 + uint32 gpioout;
9219 + uint32 gpioouten;
9220 + uint32 gpiocontrol;
9221 + uint32 gpiointpolarity;
9222 + uint32 gpiointmask;
9223 + uint32 PAD[2];
9224 +
9225 + /* Watchdog timer */
9226 + uint32 watchdog; /* 0x80 */
9227 + uint32 PAD[1];
9228 +
9229 + /*GPIO based LED powersave registers corerev >= 16*/
9230 + uint32 gpiotimerval; /*0x88 */
9231 + uint32 gpiotimeroutmask;
9232 +
9233 + /* clock control */
9234 + uint32 clockcontrol_n; /* 0x90 */
9235 + uint32 clockcontrol_sb; /* aka m0 */
9236 + uint32 clockcontrol_pci; /* aka m1 */
9237 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9238 + uint32 clockcontrol_mips; /* aka m3 */
9239 + uint32 clkdiv; /* corerev >= 3 */
9240 + uint32 PAD[2];
9241 +
9242 + /* pll delay registers (corerev >= 4) */
9243 + uint32 pll_on_delay; /* 0xb0 */
9244 + uint32 fref_sel_delay;
9245 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9246 + uint32 PAD[1];
9247 +
9248 + /* Instaclock registers (corerev >= 10) */
9249 + uint32 system_clk_ctl; /* 0xc0 */
9250 + uint32 clkstatestretch;
9251 + uint32 PAD[14];
9252 +
9253 + /* ExtBus control registers (corerev >= 3) */
9254 + uint32 pcmcia_config; /* 0x100 */
9255 + uint32 pcmcia_memwait;
9256 + uint32 pcmcia_attrwait;
9257 + uint32 pcmcia_iowait;
9258 + uint32 ide_config;
9259 + uint32 ide_memwait;
9260 + uint32 ide_attrwait;
9261 + uint32 ide_iowait;
9262 + uint32 prog_config;
9263 + uint32 prog_waitcount;
9264 + uint32 flash_config;
9265 + uint32 flash_waitcount;
9266 + uint32 PAD[116];
9267 +
9268 + /* uarts */
9269 + uint8 uart0data; /* 0x300 */
9270 + uint8 uart0imr;
9271 + uint8 uart0fcr;
9272 + uint8 uart0lcr;
9273 + uint8 uart0mcr;
9274 + uint8 uart0lsr;
9275 + uint8 uart0msr;
9276 + uint8 uart0scratch;
9277 + uint8 PAD[248]; /* corerev >= 1 */
9278 +
9279 + uint8 uart1data; /* 0x400 */
9280 + uint8 uart1imr;
9281 + uint8 uart1fcr;
9282 + uint8 uart1lcr;
9283 + uint8 uart1mcr;
9284 + uint8 uart1lsr;
9285 + uint8 uart1msr;
9286 + uint8 uart1scratch;
9287 +} chipcregs_t;
9288 +
9289 +#endif /* _LANGUAGE_ASSEMBLY */
9290 +
9291 +#define CC_CHIPID 0
9292 +#define CC_CAPABILITIES 4
9293 +#define CC_JTAGCMD 0x30
9294 +#define CC_JTAGIR 0x34
9295 +#define CC_JTAGDR 0x38
9296 +#define CC_JTAGCTRL 0x3c
9297 +#define CC_WATCHDOG 0x80
9298 +#define CC_CLKC_N 0x90
9299 +#define CC_CLKC_M0 0x94
9300 +#define CC_CLKC_M1 0x98
9301 +#define CC_CLKC_M2 0x9c
9302 +#define CC_CLKC_M3 0xa0
9303 +#define CC_CLKDIV 0xa4
9304 +#define CC_SYS_CLK_CTL 0xc0
9305 +#define CC_OTP 0x800
9306 +
9307 +/* chipid */
9308 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9309 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9310 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9311 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9312 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9313 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9314 +#define CID_CC_SHIFT 24
9315 +
9316 +/* capabilities */
9317 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9318 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9319 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9320 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9321 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9322 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9323 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9324 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9325 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9326 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9327 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9328 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9329 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9330 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9331 +
9332 +/* PLL type */
9333 +#define PLL_NONE 0x00000000
9334 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9335 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9336 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9337 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9338 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9339 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9340 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9341 +
9342 +/* corecontrol */
9343 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9344 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9345 +
9346 +/* Fields in the otpstatus register */
9347 +#define OTPS_PROGFAIL 0x80000000
9348 +#define OTPS_PROTECT 0x00000007
9349 +#define OTPS_HW_PROTECT 0x00000001
9350 +#define OTPS_SW_PROTECT 0x00000002
9351 +#define OTPS_CID_PROTECT 0x00000004
9352 +
9353 +/* Fields in the otpcontrol register */
9354 +#define OTPC_RECWAIT 0xff000000
9355 +#define OTPC_PROGWAIT 0x00ffff00
9356 +#define OTPC_PRW_SHIFT 8
9357 +#define OTPC_MAXFAIL 0x00000038
9358 +#define OTPC_VSEL 0x00000006
9359 +#define OTPC_SELVL 0x00000001
9360 +
9361 +/* Fields in otpprog */
9362 +#define OTPP_COL_MASK 0x000000ff
9363 +#define OTPP_ROW_MASK 0x0000ff00
9364 +#define OTPP_ROW_SHIFT 8
9365 +#define OTPP_READERR 0x10000000
9366 +#define OTPP_VALUE 0x20000000
9367 +#define OTPP_VALUE_SHIFT 29
9368 +#define OTPP_READ 0x40000000
9369 +#define OTPP_START 0x80000000
9370 +#define OTPP_BUSY 0x80000000
9371 +
9372 +/* jtagcmd */
9373 +#define JCMD_START 0x80000000
9374 +#define JCMD_BUSY 0x80000000
9375 +#define JCMD_PAUSE 0x40000000
9376 +#define JCMD0_ACC_MASK 0x0000f000
9377 +#define JCMD0_ACC_IRDR 0x00000000
9378 +#define JCMD0_ACC_DR 0x00001000
9379 +#define JCMD0_ACC_IR 0x00002000
9380 +#define JCMD0_ACC_RESET 0x00003000
9381 +#define JCMD0_ACC_IRPDR 0x00004000
9382 +#define JCMD0_ACC_PDR 0x00005000
9383 +#define JCMD0_IRW_MASK 0x00000f00
9384 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9385 +#define JCMD_ACC_IRDR 0x00000000
9386 +#define JCMD_ACC_DR 0x00010000
9387 +#define JCMD_ACC_IR 0x00020000
9388 +#define JCMD_ACC_RESET 0x00030000
9389 +#define JCMD_ACC_IRPDR 0x00040000
9390 +#define JCMD_ACC_PDR 0x00050000
9391 +#define JCMD_IRW_MASK 0x00001f00
9392 +#define JCMD_IRW_SHIFT 8
9393 +#define JCMD_DRW_MASK 0x0000003f
9394 +
9395 +/* jtagctrl */
9396 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9397 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9398 +#define JCTRL_EN 1 /* Enable Jtag master */
9399 +
9400 +/* Fields in clkdiv */
9401 +#define CLKD_SFLASH 0x0f000000
9402 +#define CLKD_SFLASH_SHIFT 24
9403 +#define CLKD_OTP 0x000f0000
9404 +#define CLKD_OTP_SHIFT 16
9405 +#define CLKD_JTAG 0x00000f00
9406 +#define CLKD_JTAG_SHIFT 8
9407 +#define CLKD_UART 0x000000ff
9408 +
9409 +/* intstatus/intmask */
9410 +#define CI_GPIO 0x00000001 /* gpio intr */
9411 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9412 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9413 +
9414 +/* slow_clk_ctl */
9415 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9416 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9417 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9418 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9419 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9420 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9421 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9422 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9423 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9424 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9425 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9426 +#define SCC_CD_SHIFT 16
9427 +
9428 +/* system_clk_ctl */
9429 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9430 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9431 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9432 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9433 +#define SYCC_HR 0x00000010 /* Force HT */
9434 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9435 +#define SYCC_CD_SHIFT 16
9436 +
9437 +/* gpiotimerval*/
9438 +#define GPIO_ONTIME_SHIFT 16
9439 +
9440 +/* clockcontrol_n */
9441 +#define CN_N1_MASK 0x3f /* n1 control */
9442 +#define CN_N2_MASK 0x3f00 /* n2 control */
9443 +#define CN_N2_SHIFT 8
9444 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9445 +#define CN_PLLC_SHIFT 16
9446 +
9447 +/* clockcontrol_sb/pci/uart */
9448 +#define CC_M1_MASK 0x3f /* m1 control */
9449 +#define CC_M2_MASK 0x3f00 /* m2 control */
9450 +#define CC_M2_SHIFT 8
9451 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9452 +#define CC_M3_SHIFT 16
9453 +#define CC_MC_MASK 0x1f000000 /* mux control */
9454 +#define CC_MC_SHIFT 24
9455 +
9456 +/* N3M Clock control magic field values */
9457 +#define CC_F6_2 0x02 /* A factor of 2 in */
9458 +#define CC_F6_3 0x03 /* 6-bit fields like */
9459 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9460 +#define CC_F6_5 0x09
9461 +#define CC_F6_6 0x11
9462 +#define CC_F6_7 0x21
9463 +
9464 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9465 +
9466 +#define CC_MC_BYPASS 0x08
9467 +#define CC_MC_M1 0x04
9468 +#define CC_MC_M1M2 0x02
9469 +#define CC_MC_M1M2M3 0x01
9470 +#define CC_MC_M1M3 0x11
9471 +
9472 +/* Type 2 Clock control magic field values */
9473 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9474 +#define CC_T2M2_BIAS 3 /* m2 bias */
9475 +
9476 +#define CC_T2MC_M1BYP 1
9477 +#define CC_T2MC_M2BYP 2
9478 +#define CC_T2MC_M3BYP 4
9479 +
9480 +/* Type 6 Clock control magic field values */
9481 +#define CC_T6_MMASK 1 /* bits of interest in m */
9482 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9483 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9484 +#define SB2MIPS_T6(sb) (2 * (sb))
9485 +
9486 +/* Common clock base */
9487 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9488 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9489 +
9490 +/* Clock control values for 200Mhz in 5350 */
9491 +#define CLKC_5350_N 0x0311
9492 +#define CLKC_5350_M 0x04020009
9493 +
9494 +/* Flash types in the chipcommon capabilities register */
9495 +#define FLASH_NONE 0x000 /* No flash */
9496 +#define SFLASH_ST 0x100 /* ST serial flash */
9497 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9498 +#define PFLASH 0x700 /* Parallel flash */
9499 +
9500 +/* Bits in the config registers */
9501 +#define CC_CFG_EN 0x0001 /* Enable */
9502 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9503 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9504 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9505 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9506 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9507 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9508 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9509 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9510 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9511 +
9512 +/* Start/busy bit in flashcontrol */
9513 +#define SFLASH_START 0x80000000
9514 +#define SFLASH_BUSY SFLASH_START
9515 +
9516 +/* flashcontrol opcodes for ST flashes */
9517 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9518 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9519 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9520 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9521 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9522 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9523 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9524 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9525 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9526 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9527 +
9528 +/* Status register bits for ST flashes */
9529 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9530 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9531 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9532 +#define SFLASH_ST_BP_SHIFT 2
9533 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9534 +
9535 +/* flashcontrol opcodes for Atmel flashes */
9536 +#define SFLASH_AT_READ 0x07e8
9537 +#define SFLASH_AT_PAGE_READ 0x07d2
9538 +#define SFLASH_AT_BUF1_READ
9539 +#define SFLASH_AT_BUF2_READ
9540 +#define SFLASH_AT_STATUS 0x01d7
9541 +#define SFLASH_AT_BUF1_WRITE 0x0384
9542 +#define SFLASH_AT_BUF2_WRITE 0x0387
9543 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9544 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9545 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9546 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9547 +#define SFLASH_AT_PAGE_ERASE 0x0281
9548 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9549 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9550 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9551 +#define SFLASH_AT_BUF1_LOAD 0x0253
9552 +#define SFLASH_AT_BUF2_LOAD 0x0255
9553 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9554 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9555 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9556 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9557 +
9558 +/* Status register bits for Atmel flashes */
9559 +#define SFLASH_AT_READY 0x80
9560 +#define SFLASH_AT_MISMATCH 0x40
9561 +#define SFLASH_AT_ID_MASK 0x38
9562 +#define SFLASH_AT_ID_SHIFT 3
9563 +
9564 +/* OTP regions */
9565 +#define OTP_HW_REGION OTPS_HW_PROTECT
9566 +#define OTP_SW_REGION OTPS_SW_PROTECT
9567 +#define OTP_CID_REGION OTPS_CID_PROTECT
9568 +
9569 +/* OTP regions (Byte offsets from otp size) */
9570 +#define OTP_SWLIM_OFF (-8)
9571 +#define OTP_CIDBASE_OFF 0
9572 +#define OTP_CIDLIM_OFF 8
9573 +
9574 +/* Predefined OTP words (Word offset from otp size) */
9575 +#define OTP_BOUNDARY_OFF (-4)
9576 +#define OTP_HWSIGN_OFF (-3)
9577 +#define OTP_SWSIGN_OFF (-2)
9578 +#define OTP_CIDSIGN_OFF (-1)
9579 +
9580 +#define OTP_CID_OFF 0
9581 +#define OTP_PKG_OFF 1
9582 +#define OTP_FID_OFF 2
9583 +#define OTP_RSV_OFF 3
9584 +#define OTP_LIM_OFF 4
9585 +
9586 +#define OTP_SIGNATURE 0x578a
9587 +#define OTP_MAGIC 0x4e56
9588 +
9589 +#endif /* _SBCHIPC_H */
9590 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9591 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9592 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-01-12 00:20:30.737132500 +0100
9593 @@ -0,0 +1,342 @@
9594 +/*
9595 + * Broadcom SiliconBackplane hardware register definitions.
9596 + *
9597 + * Copyright 2005, Broadcom Corporation
9598 + * All Rights Reserved.
9599 + *
9600 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9601 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9602 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9603 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9604 + * $Id$
9605 + */
9606 +
9607 +#ifndef _SBCONFIG_H
9608 +#define _SBCONFIG_H
9609 +
9610 +/* cpp contortions to concatenate w/arg prescan */
9611 +#ifndef PAD
9612 +#define _PADLINE(line) pad ## line
9613 +#define _XSTR(line) _PADLINE(line)
9614 +#define PAD _XSTR(__LINE__)
9615 +#endif
9616 +
9617 +/*
9618 + * SiliconBackplane Address Map.
9619 + * All regions may not exist on all chips.
9620 + */
9621 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9622 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9623 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9624 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9625 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9626 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9627 +
9628 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9629 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9630 +
9631 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9632 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9633 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9634 +
9635 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9636 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9637 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9638 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9639 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9640 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9641 +
9642 +
9643 +/* enumeration space related defs */
9644 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9645 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9646 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9647 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9648 +
9649 +/* mips address */
9650 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9651 +
9652 +/*
9653 + * Sonics Configuration Space Registers.
9654 + */
9655 +#define SBIPSFLAG 0x08
9656 +#define SBTPSFLAG 0x18
9657 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9658 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9659 +#define SBADMATCH3 0x60
9660 +#define SBADMATCH2 0x68
9661 +#define SBADMATCH1 0x70
9662 +#define SBIMSTATE 0x90
9663 +#define SBINTVEC 0x94
9664 +#define SBTMSTATELOW 0x98
9665 +#define SBTMSTATEHIGH 0x9c
9666 +#define SBBWA0 0xa0
9667 +#define SBIMCONFIGLOW 0xa8
9668 +#define SBIMCONFIGHIGH 0xac
9669 +#define SBADMATCH0 0xb0
9670 +#define SBTMCONFIGLOW 0xb8
9671 +#define SBTMCONFIGHIGH 0xbc
9672 +#define SBBCONFIG 0xc0
9673 +#define SBBSTATE 0xc8
9674 +#define SBACTCNFG 0xd8
9675 +#define SBFLAGST 0xe8
9676 +#define SBIDLOW 0xf8
9677 +#define SBIDHIGH 0xfc
9678 +
9679 +#ifndef _LANGUAGE_ASSEMBLY
9680 +
9681 +typedef volatile struct _sbconfig {
9682 + uint32 PAD[2];
9683 + uint32 sbipsflag; /* initiator port ocp slave flag */
9684 + uint32 PAD[3];
9685 + uint32 sbtpsflag; /* target port ocp slave flag */
9686 + uint32 PAD[11];
9687 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9688 + uint32 PAD;
9689 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9690 + uint32 PAD[3];
9691 + uint32 sbadmatch3; /* address match3 */
9692 + uint32 PAD;
9693 + uint32 sbadmatch2; /* address match2 */
9694 + uint32 PAD;
9695 + uint32 sbadmatch1; /* address match1 */
9696 + uint32 PAD[7];
9697 + uint32 sbimstate; /* initiator agent state */
9698 + uint32 sbintvec; /* interrupt mask */
9699 + uint32 sbtmstatelow; /* target state */
9700 + uint32 sbtmstatehigh; /* target state */
9701 + uint32 sbbwa0; /* bandwidth allocation table0 */
9702 + uint32 PAD;
9703 + uint32 sbimconfiglow; /* initiator configuration */
9704 + uint32 sbimconfighigh; /* initiator configuration */
9705 + uint32 sbadmatch0; /* address match0 */
9706 + uint32 PAD;
9707 + uint32 sbtmconfiglow; /* target configuration */
9708 + uint32 sbtmconfighigh; /* target configuration */
9709 + uint32 sbbconfig; /* broadcast configuration */
9710 + uint32 PAD;
9711 + uint32 sbbstate; /* broadcast state */
9712 + uint32 PAD[3];
9713 + uint32 sbactcnfg; /* activate configuration */
9714 + uint32 PAD[3];
9715 + uint32 sbflagst; /* current sbflags */
9716 + uint32 PAD[3];
9717 + uint32 sbidlow; /* identification */
9718 + uint32 sbidhigh; /* identification */
9719 +} sbconfig_t;
9720 +
9721 +#endif /* _LANGUAGE_ASSEMBLY */
9722 +
9723 +/* sbipsflag */
9724 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9725 +#define SBIPS_INT1_SHIFT 0
9726 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9727 +#define SBIPS_INT2_SHIFT 8
9728 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9729 +#define SBIPS_INT3_SHIFT 16
9730 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9731 +#define SBIPS_INT4_SHIFT 24
9732 +
9733 +/* sbtpsflag */
9734 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9735 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9736 +
9737 +/* sbtmerrlog */
9738 +#define SBTMEL_CM 0x00000007 /* command */
9739 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9740 +#define SBTMEL_EC 0x0f000000 /* error code */
9741 +#define SBTMEL_ME 0x80000000 /* multiple error */
9742 +
9743 +/* sbimstate */
9744 +#define SBIM_PC 0xf /* pipecount */
9745 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9746 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9747 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9748 +#define SBIM_AP_TK 0x20 /* use token only */
9749 +#define SBIM_AP_RSV 0x30 /* reserved */
9750 +#define SBIM_IBE 0x20000 /* inbanderror */
9751 +#define SBIM_TO 0x40000 /* timeout */
9752 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9753 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9754 +
9755 +/* sbtmstatelow */
9756 +#define SBTML_RESET 0x1 /* reset */
9757 +#define SBTML_REJ_MASK 0x6 /* reject */
9758 +#define SBTML_REJ_SHIFT 1
9759 +#define SBTML_CLK 0x10000 /* clock enable */
9760 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9761 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9762 +#define SBTML_PE 0x40000000 /* pme enable */
9763 +#define SBTML_BE 0x80000000 /* bist enable */
9764 +
9765 +/* sbtmstatehigh */
9766 +#define SBTMH_SERR 0x1 /* serror */
9767 +#define SBTMH_INT 0x2 /* interrupt */
9768 +#define SBTMH_BUSY 0x4 /* busy */
9769 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9770 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9771 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9772 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9773 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9774 +#define SBTMH_BISTD 0x80000000 /* bist done */
9775 +
9776 +
9777 +/* sbbwa0 */
9778 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9779 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9780 +#define SBBWA_TAB1_SHIFT 16
9781 +
9782 +/* sbimconfiglow */
9783 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9784 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9785 +#define SBIMCL_RTO_SHIFT 4
9786 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9787 +#define SBIMCL_CID_SHIFT 16
9788 +
9789 +/* sbimconfighigh */
9790 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9791 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9792 +#define SBIMCH_TEM_SHIFT 4
9793 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9794 +#define SBIMCH_BEM_SHIFT 6
9795 +
9796 +/* sbadmatch0 */
9797 +#define SBAM_TYPE_MASK 0x3 /* address type */
9798 +#define SBAM_AD64 0x4 /* reserved */
9799 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9800 +#define SBAM_ADINT0_SHIFT 3
9801 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9802 +#define SBAM_ADINT1_SHIFT 3
9803 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9804 +#define SBAM_ADINT2_SHIFT 3
9805 +#define SBAM_ADEN 0x400 /* enable */
9806 +#define SBAM_ADNEG 0x800 /* negative decode */
9807 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9808 +#define SBAM_BASE0_SHIFT 8
9809 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9810 +#define SBAM_BASE1_SHIFT 12
9811 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9812 +#define SBAM_BASE2_SHIFT 16
9813 +
9814 +/* sbtmconfiglow */
9815 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9816 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9817 +#define SBTMCL_CO_SHIFT 11
9818 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9819 +#define SBTMCL_IF_SHIFT 18
9820 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9821 +#define SBTMCL_IM_SHIFT 24
9822 +
9823 +/* sbtmconfighigh */
9824 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9825 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9826 +#define SBTMCH_RM_SHIFT 2
9827 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9828 +#define SBTMCH_SM_SHIFT 4
9829 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9830 +#define SBTMCH_EM_SHIFT 8
9831 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9832 +#define SBTMCH_IM_SHIFT 10
9833 +
9834 +/* sbbconfig */
9835 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9836 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9837 +#define SBBC_MAX0_SHIFT 16
9838 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9839 +#define SBBC_MAX1_SHIFT 20
9840 +
9841 +/* sbbstate */
9842 +#define SBBS_SRD 0x1 /* st reg disable */
9843 +#define SBBS_HRD 0x2 /* hold reg disable */
9844 +
9845 +/* sbidlow */
9846 +#define SBIDL_CS_MASK 0x3 /* config space */
9847 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9848 +#define SBIDL_AR_SHIFT 3
9849 +#define SBIDL_SYNCH 0x40 /* sync */
9850 +#define SBIDL_INIT 0x80 /* initiator */
9851 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9852 +#define SBIDL_MINLAT_SHIFT 8
9853 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9854 +#define SBIDL_MAXLAT_SHIFT 12
9855 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9856 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9857 +#define SBIDL_CW_SHIFT 18
9858 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9859 +#define SBIDL_TP_SHIFT 20
9860 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9861 +#define SBIDL_IP_SHIFT 24
9862 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9863 +#define SBIDL_RV_SHIFT 28
9864 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9865 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9866 +
9867 +/* sbidhigh */
9868 +#define SBIDH_RC_MASK 0x000f /* revision code */
9869 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9870 +#define SBIDH_RCE_SHIFT 8
9871 +#define SBCOREREV(sbidh) \
9872 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9873 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9874 +#define SBIDH_CC_SHIFT 4
9875 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9876 +#define SBIDH_VC_SHIFT 16
9877 +
9878 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9879 +
9880 +/* vendor codes */
9881 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9882 +
9883 +/* core codes */
9884 +#define SB_CC 0x800 /* chipcommon core */
9885 +#define SB_ILINE20 0x801 /* iline20 core */
9886 +#define SB_SDRAM 0x803 /* sdram core */
9887 +#define SB_PCI 0x804 /* pci core */
9888 +#define SB_MIPS 0x805 /* mips core */
9889 +#define SB_ENET 0x806 /* enet mac core */
9890 +#define SB_CODEC 0x807 /* v90 codec core */
9891 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9892 +#define SB_ADSL 0x809 /* ADSL core */
9893 +#define SB_ILINE100 0x80a /* iline100 core */
9894 +#define SB_IPSEC 0x80b /* ipsec core */
9895 +#define SB_PCMCIA 0x80d /* pcmcia core */
9896 +#define SB_SOCRAM 0x80e /* internal memory core */
9897 +#define SB_MEMC 0x80f /* memc sdram core */
9898 +#define SB_EXTIF 0x811 /* external interface core */
9899 +#define SB_D11 0x812 /* 802.11 MAC core */
9900 +#define SB_MIPS33 0x816 /* mips3302 core */
9901 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9902 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9903 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9904 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9905 +#define SB_SDIOH 0x81b /* sdio host core */
9906 +#define SB_ROBO 0x81c /* roboswitch core */
9907 +#define SB_ATA100 0x81d /* parallel ATA core */
9908 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9909 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9910 +#define SB_PCIE 0x820 /* pci express core */
9911 +#define SB_SRAMC 0x822 /* SRAM controller core */
9912 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9913 +
9914 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9915 +
9916 +/* Not really related to Silicon Backplane, but a couple of software
9917 + * conventions for the use the flash space:
9918 + */
9919 +
9920 +/* Minumum amount of flash we support */
9921 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9922 +
9923 +/* A boot/binary may have an embedded block that describes its size */
9924 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9925 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9926 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9927 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9928 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9929 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9930 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9931 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9932 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9933 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9934 +
9935 +#endif /* _SBCONFIG_H */
9936 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9937 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9938 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-01-12 00:20:30.737132500 +0100
9939 @@ -0,0 +1,242 @@
9940 +/*
9941 + * Hardware-specific External Interface I/O core definitions
9942 + * for the BCM47xx family of SiliconBackplane-based chips.
9943 + *
9944 + * The External Interface core supports a total of three external chip selects
9945 + * supporting external interfaces. One of the external chip selects is
9946 + * used for Flash, one is used for PCMCIA, and the other may be
9947 + * programmed to support either a synchronous interface or an
9948 + * asynchronous interface. The asynchronous interface can be used to
9949 + * support external devices such as UARTs and the BCM2019 Bluetooth
9950 + * baseband processor.
9951 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9952 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9953 + *
9954 + * Copyright 2005, Broadcom Corporation
9955 + * All Rights Reserved.
9956 + *
9957 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9958 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9959 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9960 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9961 + * $Id$
9962 + */
9963 +
9964 +#ifndef _SBEXTIF_H
9965 +#define _SBEXTIF_H
9966 +
9967 +/* external interface address space */
9968 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9969 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9970 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9971 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9972 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9973 +
9974 +/* cpp contortions to concatenate w/arg prescan */
9975 +#ifndef PAD
9976 +#define _PADLINE(line) pad ## line
9977 +#define _XSTR(line) _PADLINE(line)
9978 +#define PAD _XSTR(__LINE__)
9979 +#endif /* PAD */
9980 +
9981 +/*
9982 + * The multiple instances of output and output enable registers
9983 + * are present to allow driver software for multiple cores to control
9984 + * gpio outputs without needing to share a single register pair.
9985 + */
9986 +struct gpiouser {
9987 + uint32 out;
9988 + uint32 outen;
9989 +};
9990 +#define NGPIOUSER 5
9991 +
9992 +typedef volatile struct {
9993 + uint32 corecontrol;
9994 + uint32 extstatus;
9995 + uint32 PAD[2];
9996 +
9997 + /* pcmcia control registers */
9998 + uint32 pcmcia_config;
9999 + uint32 pcmcia_memwait;
10000 + uint32 pcmcia_attrwait;
10001 + uint32 pcmcia_iowait;
10002 +
10003 + /* programmable interface control registers */
10004 + uint32 prog_config;
10005 + uint32 prog_waitcount;
10006 +
10007 + /* flash control registers */
10008 + uint32 flash_config;
10009 + uint32 flash_waitcount;
10010 + uint32 PAD[4];
10011 +
10012 + uint32 watchdog;
10013 +
10014 + /* clock control */
10015 + uint32 clockcontrol_n;
10016 + uint32 clockcontrol_sb;
10017 + uint32 clockcontrol_pci;
10018 + uint32 clockcontrol_mii;
10019 + uint32 PAD[3];
10020 +
10021 + /* gpio */
10022 + uint32 gpioin;
10023 + struct gpiouser gpio[NGPIOUSER];
10024 + uint32 PAD;
10025 + uint32 ejtagouten;
10026 + uint32 gpiointpolarity;
10027 + uint32 gpiointmask;
10028 + uint32 PAD[153];
10029 +
10030 + uint8 uartdata;
10031 + uint8 PAD[3];
10032 + uint8 uartimer;
10033 + uint8 PAD[3];
10034 + uint8 uartfcr;
10035 + uint8 PAD[3];
10036 + uint8 uartlcr;
10037 + uint8 PAD[3];
10038 + uint8 uartmcr;
10039 + uint8 PAD[3];
10040 + uint8 uartlsr;
10041 + uint8 PAD[3];
10042 + uint8 uartmsr;
10043 + uint8 PAD[3];
10044 + uint8 uartscratch;
10045 + uint8 PAD[3];
10046 +} extifregs_t;
10047 +
10048 +/* corecontrol */
10049 +#define CC_UE (1 << 0) /* uart enable */
10050 +
10051 +/* extstatus */
10052 +#define ES_EM (1 << 0) /* endian mode (ro) */
10053 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10054 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10055 +
10056 +/* gpio bit mask */
10057 +#define GPIO_BIT0 (1 << 0)
10058 +#define GPIO_BIT1 (1 << 1)
10059 +#define GPIO_BIT2 (1 << 2)
10060 +#define GPIO_BIT3 (1 << 3)
10061 +#define GPIO_BIT4 (1 << 4)
10062 +#define GPIO_BIT5 (1 << 5)
10063 +#define GPIO_BIT6 (1 << 6)
10064 +#define GPIO_BIT7 (1 << 7)
10065 +
10066 +
10067 +/* pcmcia/prog/flash_config */
10068 +#define CF_EN (1 << 0) /* enable */
10069 +#define CF_EM_MASK 0xe /* mode */
10070 +#define CF_EM_SHIFT 1
10071 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10072 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10073 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10074 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10075 +#define CF_BS (1 << 5) /* byteswap */
10076 +#define CF_CD_MASK 0xc0 /* clock divider */
10077 +#define CF_CD_SHIFT 6
10078 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10079 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10080 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10081 +#define CF_CE (1 << 8) /* clock enable */
10082 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10083 +
10084 +/* pcmcia_memwait */
10085 +#define PM_W0_MASK 0x3f /* waitcount0 */
10086 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10087 +#define PM_W1_SHIFT 8
10088 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10089 +#define PM_W2_SHIFT 16
10090 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10091 +#define PM_W3_SHIFT 24
10092 +
10093 +/* pcmcia_attrwait */
10094 +#define PA_W0_MASK 0x3f /* waitcount0 */
10095 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10096 +#define PA_W1_SHIFT 8
10097 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10098 +#define PA_W2_SHIFT 16
10099 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10100 +#define PA_W3_SHIFT 24
10101 +
10102 +/* pcmcia_iowait */
10103 +#define PI_W0_MASK 0x3f /* waitcount0 */
10104 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10105 +#define PI_W1_SHIFT 8
10106 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10107 +#define PI_W2_SHIFT 16
10108 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10109 +#define PI_W3_SHIFT 24
10110 +
10111 +/* prog_waitcount */
10112 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10113 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10114 +#define PW_W1_SHIFT 8
10115 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10116 +#define PW_W2_SHIFT 16
10117 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10118 +#define PW_W3_SHIFT 24
10119 +
10120 +#define PW_W0 0x0000000c
10121 +#define PW_W1 0x00000a00
10122 +#define PW_W2 0x00020000
10123 +#define PW_W3 0x01000000
10124 +
10125 +/* flash_waitcount */
10126 +#define FW_W0_MASK 0x1f /* waitcount0 */
10127 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10128 +#define FW_W1_SHIFT 8
10129 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10130 +#define FW_W2_SHIFT 16
10131 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10132 +#define FW_W3_SHIFT 24
10133 +
10134 +/* watchdog */
10135 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10136 +
10137 +/* clockcontrol_n */
10138 +#define CN_N1_MASK 0x3f /* n1 control */
10139 +#define CN_N2_MASK 0x3f00 /* n2 control */
10140 +#define CN_N2_SHIFT 8
10141 +
10142 +/* clockcontrol_sb/pci/mii */
10143 +#define CC_M1_MASK 0x3f /* m1 control */
10144 +#define CC_M2_MASK 0x3f00 /* m2 control */
10145 +#define CC_M2_SHIFT 8
10146 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10147 +#define CC_M3_SHIFT 16
10148 +#define CC_MC_MASK 0x1f000000 /* mux control */
10149 +#define CC_MC_SHIFT 24
10150 +
10151 +/* Clock control default values */
10152 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10153 +#define CC_DEF_100 0x04020011
10154 +#define CC_DEF_33 0x11030011
10155 +#define CC_DEF_25 0x11050011
10156 +
10157 +/* Clock control values for 125Mhz */
10158 +#define CC_125_N 0x0802
10159 +#define CC_125_M 0x04020009
10160 +#define CC_125_M25 0x11090009
10161 +#define CC_125_M33 0x11090005
10162 +
10163 +/* Clock control magic field values */
10164 +#define CC_F6_2 0x02 /* A factor of 2 in */
10165 +#define CC_F6_3 0x03 /* 6-bit fields like */
10166 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10167 +#define CC_F6_5 0x09
10168 +#define CC_F6_6 0x11
10169 +#define CC_F6_7 0x21
10170 +
10171 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10172 +
10173 +#define CC_MC_BYPASS 0x08
10174 +#define CC_MC_M1 0x04
10175 +#define CC_MC_M1M2 0x02
10176 +#define CC_MC_M1M2M3 0x01
10177 +#define CC_MC_M1M3 0x11
10178 +
10179 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10180 +
10181 +#endif /* _SBEXTIF_H */
10182 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10183 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10184 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-01-12 00:20:30.737132500 +0100
10185 @@ -0,0 +1,148 @@
10186 +/*
10187 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10188 + *
10189 + * Copyright 2005, Broadcom Corporation
10190 + * All Rights Reserved.
10191 + *
10192 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10193 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10194 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10195 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10196 + *
10197 + * $Id$
10198 + */
10199 +
10200 +#ifndef _SBMEMC_H
10201 +#define _SBMEMC_H
10202 +
10203 +#ifdef _LANGUAGE_ASSEMBLY
10204 +
10205 +#define MEMC_CONTROL 0x00
10206 +#define MEMC_CONFIG 0x04
10207 +#define MEMC_REFRESH 0x08
10208 +#define MEMC_BISTSTAT 0x0c
10209 +#define MEMC_MODEBUF 0x10
10210 +#define MEMC_BKCLS 0x14
10211 +#define MEMC_PRIORINV 0x18
10212 +#define MEMC_DRAMTIM 0x1c
10213 +#define MEMC_INTSTAT 0x20
10214 +#define MEMC_INTMASK 0x24
10215 +#define MEMC_INTINFO 0x28
10216 +#define MEMC_NCDLCTL 0x30
10217 +#define MEMC_RDNCDLCOR 0x34
10218 +#define MEMC_WRNCDLCOR 0x38
10219 +#define MEMC_MISCDLYCTL 0x3c
10220 +#define MEMC_DQSGATENCDL 0x40
10221 +#define MEMC_SPARE 0x44
10222 +#define MEMC_TPADDR 0x48
10223 +#define MEMC_TPDATA 0x4c
10224 +#define MEMC_BARRIER 0x50
10225 +#define MEMC_CORE 0x54
10226 +
10227 +
10228 +#else
10229 +
10230 +/* Sonics side: MEMC core registers */
10231 +typedef volatile struct sbmemcregs {
10232 + uint32 control;
10233 + uint32 config;
10234 + uint32 refresh;
10235 + uint32 biststat;
10236 + uint32 modebuf;
10237 + uint32 bkcls;
10238 + uint32 priorinv;
10239 + uint32 dramtim;
10240 + uint32 intstat;
10241 + uint32 intmask;
10242 + uint32 intinfo;
10243 + uint32 reserved1;
10244 + uint32 ncdlctl;
10245 + uint32 rdncdlcor;
10246 + uint32 wrncdlcor;
10247 + uint32 miscdlyctl;
10248 + uint32 dqsgatencdl;
10249 + uint32 spare;
10250 + uint32 tpaddr;
10251 + uint32 tpdata;
10252 + uint32 barrier;
10253 + uint32 core;
10254 +} sbmemcregs_t;
10255 +
10256 +#endif
10257 +
10258 +/* MEMC Core Init values (OCP ID 0x80f) */
10259 +
10260 +/* For sdr: */
10261 +#define MEMC_SD_CONFIG_INIT 0x00048000
10262 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10263 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10264 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10265 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10266 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10267 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10268 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10269 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10270 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10271 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10272 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10273 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10274 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10275 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10276 +
10277 +
10278 +/* This is for SDRM8X8X4 */
10279 +#define MEMC_SDR_INIT 0x0008
10280 +#define MEMC_SDR_MODE 0x32
10281 +#define MEMC_SDR_NCDL 0x00020032
10282 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10283 +
10284 +/* For ddr: */
10285 +#define MEMC_CONFIG_INIT 0x00048000
10286 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10287 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10288 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10289 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10290 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10291 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10292 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10293 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10294 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10295 +#define MEMC_NCDLCTL_INIT 0x00002001
10296 +#define MEMC_CONTROL_INIT0 0x00000002
10297 +#define MEMC_CONTROL_INIT1 0x00000008
10298 +#define MEMC_MODEBUF_INIT0 0x00004000
10299 +#define MEMC_CONTROL_INIT2 0x00000010
10300 +#define MEMC_MODEBUF_INIT1 0x00000100
10301 +#define MEMC_CONTROL_INIT3 0x00000010
10302 +#define MEMC_CONTROL_INIT4 0x00000008
10303 +#define MEMC_REFRESH_INIT 0x0000840f
10304 +#define MEMC_CONTROL_INIT5 0x00000004
10305 +#define MEMC_MODEBUF_INIT2 0x00000000
10306 +#define MEMC_CONTROL_INIT6 0x00000010
10307 +#define MEMC_CONTROL_INIT7 0x00000001
10308 +
10309 +
10310 +/* This is for DDRM16X16X2 */
10311 +#define MEMC_DDR_INIT 0x0009
10312 +#define MEMC_DDR_MODE 0x62
10313 +#define MEMC_DDR_NCDL 0x0005050a
10314 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10315 +
10316 +/* mask for sdr/ddr calibration registers */
10317 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10318 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10319 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10320 +
10321 +/* masks for miscdlyctl registers */
10322 +#define MEMC_MISC_SM_MASK 0x30000000
10323 +#define MEMC_MISC_SM_SHIFT 28
10324 +#define MEMC_MISC_SD_MASK 0x0f000000
10325 +#define MEMC_MISC_SD_SHIFT 24
10326 +
10327 +/* hw threshhold for calculating wr/rd for sdr memc */
10328 +#define MEMC_CD_THRESHOLD 128
10329 +
10330 +/* Low bit of init register says if memc is ddr or sdr */
10331 +#define MEMC_CONFIG_DDR 0x00000001
10332 +
10333 +#endif /* _SBMEMC_H */
10334 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10335 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10336 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2006-01-12 00:20:30.737132500 +0100
10337 @@ -0,0 +1,62 @@
10338 +/*
10339 + * Broadcom SiliconBackplane MIPS definitions
10340 + *
10341 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10342 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10343 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10344 + * interface. The core revision is stored in the SB ID register in SB
10345 + * configuration space.
10346 + *
10347 + * Copyright 2005, Broadcom Corporation
10348 + * All Rights Reserved.
10349 + *
10350 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10351 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10352 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10353 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10354 + *
10355 + * $Id$
10356 + */
10357 +
10358 +#ifndef _SBMIPS_H
10359 +#define _SBMIPS_H
10360 +
10361 +#include <mipsinc.h>
10362 +
10363 +#ifndef _LANGUAGE_ASSEMBLY
10364 +
10365 +/* cpp contortions to concatenate w/arg prescan */
10366 +#ifndef PAD
10367 +#define _PADLINE(line) pad ## line
10368 +#define _XSTR(line) _PADLINE(line)
10369 +#define PAD _XSTR(__LINE__)
10370 +#endif /* PAD */
10371 +
10372 +typedef volatile struct {
10373 + uint32 corecontrol;
10374 + uint32 PAD[2];
10375 + uint32 biststatus;
10376 + uint32 PAD[4];
10377 + uint32 intstatus;
10378 + uint32 intmask;
10379 + uint32 timer;
10380 +} mipsregs_t;
10381 +
10382 +extern uint32 sb_flag(sb_t *sbh);
10383 +extern uint sb_irq(sb_t *sbh);
10384 +
10385 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10386 +
10387 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10388 +extern void sb_jtagm_disable(void *h);
10389 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10390 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10391 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10392 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10393 +extern void BCMINIT(enable_pfc)(uint32 mode);
10394 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10395 +
10396 +
10397 +#endif /* _LANGUAGE_ASSEMBLY */
10398 +
10399 +#endif /* _SBMIPS_H */
10400 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10401 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10402 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-01-12 00:20:30.737132500 +0100
10403 @@ -0,0 +1,122 @@
10404 +/*
10405 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10406 + *
10407 + * $Id$
10408 + * Copyright 2005, Broadcom Corporation
10409 + * All Rights Reserved.
10410 + *
10411 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10412 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10413 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10414 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10415 + */
10416 +
10417 +#ifndef _SBPCI_H
10418 +#define _SBPCI_H
10419 +
10420 +/* cpp contortions to concatenate w/arg prescan */
10421 +#ifndef PAD
10422 +#define _PADLINE(line) pad ## line
10423 +#define _XSTR(line) _PADLINE(line)
10424 +#define PAD _XSTR(__LINE__)
10425 +#endif
10426 +
10427 +/* Sonics side: PCI core and host control registers */
10428 +typedef struct sbpciregs {
10429 + uint32 control; /* PCI control */
10430 + uint32 PAD[3];
10431 + uint32 arbcontrol; /* PCI arbiter control */
10432 + uint32 PAD[3];
10433 + uint32 intstatus; /* Interrupt status */
10434 + uint32 intmask; /* Interrupt mask */
10435 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10436 + uint32 PAD[9];
10437 + uint32 bcastaddr; /* Sonics broadcast address */
10438 + uint32 bcastdata; /* Sonics broadcast data */
10439 + uint32 PAD[2];
10440 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10441 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10442 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10443 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10444 + uint32 PAD[36];
10445 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10446 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10447 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10448 + uint32 PAD[445];
10449 + uint16 sprom[36]; /* SPROM shadow Area */
10450 + uint32 PAD[46];
10451 +} sbpciregs_t;
10452 +
10453 +/* PCI control */
10454 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10455 +#define PCI_RST 0x02 /* Value driven out to pin */
10456 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10457 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10458 +
10459 +/* PCI arbiter control */
10460 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10461 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10462 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10463 +#define PCI_PARKID_SHIFT 1
10464 +#define PCI_PARKID_LAST 0 /* Last requestor */
10465 +#define PCI_PARKID_4710 1 /* 4710 */
10466 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10467 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10468 +
10469 +/* Interrupt status/mask */
10470 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10471 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10472 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10473 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10474 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10475 +
10476 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10477 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10478 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10479 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10480 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10481 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10482 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10483 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10484 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10485 +
10486 +/* Sonics broadcast address */
10487 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10488 +
10489 +/* Sonics to PCI translation types */
10490 +#define SBTOPCI0_MASK 0xfc000000
10491 +#define SBTOPCI1_MASK 0xfc000000
10492 +#define SBTOPCI2_MASK 0xc0000000
10493 +#define SBTOPCI_MEM 0
10494 +#define SBTOPCI_IO 1
10495 +#define SBTOPCI_CFG0 2
10496 +#define SBTOPCI_CFG1 3
10497 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10498 +#define SBTOPCI_BURST 0x8 /* burst enable */
10499 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10500 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10501 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10502 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10503 +
10504 +/* PCI core index in SROM shadow area */
10505 +#define SRSH_PI_OFFSET 0 /* first word */
10506 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10507 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10508 +
10509 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10510 +#define cap_list rsvd_a[0]
10511 +#define bar0_window dev_dep[0x80 - 0x40]
10512 +#define bar1_window dev_dep[0x84 - 0x40]
10513 +#define sprom_control dev_dep[0x88 - 0x40]
10514 +
10515 +#ifndef _LANGUAGE_ASSEMBLY
10516 +
10517 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10518 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10519 +extern void sbpci_ban(uint16 core);
10520 +extern int sbpci_init(sb_t *sbh);
10521 +extern void sbpci_check(sb_t *sbh);
10522 +
10523 +#endif /* !_LANGUAGE_ASSEMBLY */
10524 +
10525 +#endif /* _SBPCI_H */
10526 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10527 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10528 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-01-12 00:20:30.737132500 +0100
10529 @@ -0,0 +1,75 @@
10530 +/*
10531 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10532 + *
10533 + * Copyright 2005, Broadcom Corporation
10534 + * All Rights Reserved.
10535 + *
10536 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10537 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10538 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10539 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10540 + * $Id$
10541 + */
10542 +
10543 +#ifndef _SBSDRAM_H
10544 +#define _SBSDRAM_H
10545 +
10546 +#ifndef _LANGUAGE_ASSEMBLY
10547 +
10548 +/* Sonics side: SDRAM core registers */
10549 +typedef volatile struct sbsdramregs {
10550 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10551 + uint32 config; /* Initializes external SDRAM mode register */
10552 + uint32 refresh; /* Controls external SDRAM refresh rate */
10553 + uint32 pad1;
10554 + uint32 pad2;
10555 +} sbsdramregs_t;
10556 +
10557 +#endif
10558 +
10559 +/* SDRAM initialization control (initcontrol) register bits */
10560 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10561 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10562 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10563 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10564 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10565 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10566 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10567 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10568 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10569 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10570 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10571 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10572 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10573 +
10574 +/* SDRAM configuration (config) register bits */
10575 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10576 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10577 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10578 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10579 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10580 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10581 +
10582 +/* SDRAM refresh control (refresh) register bits */
10583 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10584 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10585 +
10586 +/* SDRAM Core default Init values (OCP ID 0x803) */
10587 +#define SDRAM_INIT MEM4MX16X2
10588 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10589 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10590 +
10591 +#define MEM1MX16 0x009 /* 2 MB */
10592 +#define MEM1MX16X2 0x409 /* 4 MB */
10593 +#define MEM2MX8X2 0x809 /* 4 MB */
10594 +#define MEM2MX8X4 0xc09 /* 8 MB */
10595 +#define MEM2MX32 0x439 /* 8 MB */
10596 +#define MEM4MX16 0x019 /* 8 MB */
10597 +#define MEM4MX16X2 0x419 /* 16 MB */
10598 +#define MEM8MX8X2 0x819 /* 16 MB */
10599 +#define MEM8MX16 0x829 /* 16 MB */
10600 +#define MEM4MX32 0x429 /* 16 MB */
10601 +#define MEM8MX8X4 0xc19 /* 32 MB */
10602 +#define MEM8MX16X2 0xc29 /* 32 MB */
10603 +
10604 +#endif /* _SBSDRAM_H */
10605 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10606 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10607 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-01-12 00:20:30.737132500 +0100
10608 @@ -0,0 +1,136 @@
10609 +/*
10610 + * Misc utility routines for accessing chip-specific features
10611 + * of Broadcom HNBU SiliconBackplane-based chips.
10612 + *
10613 + * Copyright 2005, Broadcom Corporation
10614 + * All Rights Reserved.
10615 + *
10616 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10617 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10618 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10619 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10620 + *
10621 + * $Id$
10622 + */
10623 +
10624 +#ifndef _sbutils_h_
10625 +#define _sbutils_h_
10626 +
10627 +/*
10628 + * Datastructure to export all chip specific common variables
10629 + * public (read-only) portion of sbutils handle returned by
10630 + * sb_attach()/sb_kattach()
10631 +*/
10632 +
10633 +struct sb_pub {
10634 +
10635 + uint bustype; /* SB_BUS, PCI_BUS */
10636 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10637 + uint buscorerev; /* buscore rev */
10638 + uint buscoreidx; /* buscore index */
10639 + int ccrev; /* chip common core rev */
10640 + uint boardtype; /* board type */
10641 + uint boardvendor; /* board vendor */
10642 + uint chip; /* chip number */
10643 + uint chiprev; /* chip revision */
10644 + uint chippkg; /* chip package option */
10645 + uint sonicsrev; /* sonics backplane rev */
10646 +};
10647 +
10648 +typedef const struct sb_pub sb_t;
10649 +
10650 +/*
10651 + * Many of the routines below take an 'sbh' handle as their first arg.
10652 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10653 + * At any one time, the sbh is logically focused on one particular sb core
10654 + * (the "current core").
10655 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10656 + */
10657 +
10658 +/* exported externs */
10659 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10660 +extern sb_t * BCMINIT(sb_kattach)(void);
10661 +extern void sb_detach(sb_t *sbh);
10662 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10663 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10664 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10665 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10666 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10667 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10668 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10669 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10670 +extern uint sb_bus(sb_t *sbh);
10671 +extern uint sb_buscoretype(sb_t *sbh);
10672 +extern uint sb_buscorerev(sb_t *sbh);
10673 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10674 +extern uint sb_coreid(sb_t *sbh);
10675 +extern uint sb_coreidx(sb_t *sbh);
10676 +extern uint sb_coreunit(sb_t *sbh);
10677 +extern uint sb_corevendor(sb_t *sbh);
10678 +extern uint sb_corerev(sb_t *sbh);
10679 +extern void *sb_osh(sb_t *sbh);
10680 +extern void *sb_coreregs(sb_t *sbh);
10681 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10682 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10683 +extern bool sb_iscoreup(sb_t *sbh);
10684 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10685 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10686 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10687 +extern void sb_commit(sb_t *sbh);
10688 +extern uint32 sb_base(uint32 admatch);
10689 +extern uint32 sb_size(uint32 admatch);
10690 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10691 +extern void sb_core_tofixup(sb_t *sbh);
10692 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10693 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10694 +extern uint32 sb_clock(sb_t *sbh);
10695 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10696 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10697 +extern void *sb_gpiosetcore(sb_t *sbh);
10698 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10699 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10700 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10701 +extern uint32 sb_gpioin(sb_t *sbh);
10702 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10703 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10704 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10705 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10706 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10707 +
10708 +extern void sb_clkctl_init(sb_t *sbh);
10709 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10710 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10711 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10712 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10713 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10714 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10715 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10716 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10717 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10718 +
10719 +
10720 +
10721 +/*
10722 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10723 +* The returned path is NULL terminated and has trailing '/'.
10724 +* Return 0 on success, nonzero otherwise.
10725 +*/
10726 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10727 +
10728 +/* clkctl xtal what flags */
10729 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10730 +#define PLL 0x2 /* main chip pll */
10731 +
10732 +/* clkctl clk mode */
10733 +#define CLK_FAST 0 /* force fast (pll) clock */
10734 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10735 +
10736 +
10737 +/* GPIO usage priorities */
10738 +#define GPIO_DRV_PRIORITY 0
10739 +#define GPIO_APP_PRIORITY 1
10740 +
10741 +/* device path */
10742 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10743 +
10744 +#endif /* _sbutils_h_ */
10745 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10746 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10747 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-01-12 00:20:30.745133000 +0100
10748 @@ -0,0 +1,36 @@
10749 +/*
10750 + * Broadcom SiliconBackplane chipcommon serial flash interface
10751 + *
10752 + * Copyright 2005, Broadcom Corporation
10753 + * All Rights Reserved.
10754 + *
10755 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10756 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10757 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10758 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10759 + *
10760 + * $Id$
10761 + */
10762 +
10763 +#ifndef _sflash_h_
10764 +#define _sflash_h_
10765 +
10766 +#include <typedefs.h>
10767 +#include <sbchipc.h>
10768 +
10769 +struct sflash {
10770 + uint blocksize; /* Block size */
10771 + uint numblocks; /* Number of blocks */
10772 + uint32 type; /* Type */
10773 + uint size; /* Total size in bytes */
10774 +};
10775 +
10776 +/* Utility functions */
10777 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10778 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10779 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10780 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10781 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10782 +extern struct sflash * sflash_init(chipcregs_t *cc);
10783 +
10784 +#endif /* _sflash_h_ */
10785 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10786 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10787 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-01-12 00:20:30.745133000 +0100
10788 @@ -0,0 +1,33 @@
10789 +/*
10790 + * TRX image file header format.
10791 + *
10792 + * Copyright 2005, Broadcom Corporation
10793 + * All Rights Reserved.
10794 + *
10795 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10796 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10797 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10798 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10799 + *
10800 + * $Id$
10801 + */
10802 +
10803 +#include <typedefs.h>
10804 +
10805 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10806 +#define TRX_VERSION 1
10807 +#define TRX_MAX_LEN 0x3A0000
10808 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10809 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10810 +#define TRX_MAX_OFFSET 3
10811 +
10812 +struct trx_header {
10813 + uint32 magic; /* "HDR0" */
10814 + uint32 len; /* Length of file including header */
10815 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10816 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10817 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10818 +};
10819 +
10820 +/* Compatibility */
10821 +typedef struct trx_header TRXHDR, *PTRXHDR;
10822 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10823 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10824 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-01-12 00:20:30.745133000 +0100
10825 @@ -0,0 +1,326 @@
10826 +/*
10827 + * Copyright 2005, Broadcom Corporation
10828 + * All Rights Reserved.
10829 + *
10830 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10831 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10832 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10833 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10834 + * $Id$
10835 + */
10836 +
10837 +#ifndef _TYPEDEFS_H_
10838 +#define _TYPEDEFS_H_
10839 +
10840 +
10841 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10842 + * typedef file "site_typedefs.h".
10843 + *
10844 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10845 + * section of this file makes inferences about the compile environment
10846 + * based on defined symbols and possibly compiler pragmas.
10847 + *
10848 + * Following these two sections is the "Default Typedefs"
10849 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10850 + * defined. This section has a default set of typedefs and a few
10851 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10852 + */
10853 +
10854 +#ifdef SITE_TYPEDEFS
10855 +
10856 +/*******************************************************************************
10857 + * Site Specific Typedefs
10858 + *******************************************************************************/
10859 +
10860 +#include "site_typedefs.h"
10861 +
10862 +#else
10863 +
10864 +/*******************************************************************************
10865 + * Inferred Typedefs
10866 + *******************************************************************************/
10867 +
10868 +/* Infer the compile environment based on preprocessor symbols and pramas.
10869 + * Override type definitions as needed, and include configuration dependent
10870 + * header files to define types.
10871 + */
10872 +
10873 +#ifdef __cplusplus
10874 +
10875 +#define TYPEDEF_BOOL
10876 +#ifndef FALSE
10877 +#define FALSE false
10878 +#endif
10879 +#ifndef TRUE
10880 +#define TRUE true
10881 +#endif
10882 +
10883 +#else /* ! __cplusplus */
10884 +
10885 +#if defined(_WIN32)
10886 +
10887 +#define TYPEDEF_BOOL
10888 +typedef unsigned char bool; /* consistent w/BOOL */
10889 +
10890 +#endif /* _WIN32 */
10891 +
10892 +#endif /* ! __cplusplus */
10893 +
10894 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10895 +#if defined(_WIN64)
10896 +#include <basetsd.h>
10897 +#define TYPEDEF_UINTPTR
10898 +typedef ULONG_PTR uintptr;
10899 +#endif
10900 +
10901 +#ifdef _HNDRTE_
10902 +typedef long unsigned int size_t;
10903 +#endif
10904 +
10905 +#ifdef _MSC_VER /* Microsoft C */
10906 +#define TYPEDEF_INT64
10907 +#define TYPEDEF_UINT64
10908 +typedef signed __int64 int64;
10909 +typedef unsigned __int64 uint64;
10910 +#endif
10911 +
10912 +#if defined(MACOSX) && defined(KERNEL)
10913 +#define TYPEDEF_BOOL
10914 +#endif
10915 +
10916 +
10917 +#if defined(linux)
10918 +#define TYPEDEF_UINT
10919 +#define TYPEDEF_USHORT
10920 +#define TYPEDEF_ULONG
10921 +#endif
10922 +
10923 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10924 +#define TYPEDEF_UINT
10925 +#define TYPEDEF_USHORT
10926 +#endif
10927 +
10928 +
10929 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10930 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10931 +#define TYPEDEF_INT64
10932 +#define TYPEDEF_UINT64
10933 +#endif
10934 +
10935 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10936 + * for singned or unsigned */
10937 +#if defined(__ICL)
10938 +
10939 +#define TYPEDEF_INT64
10940 +
10941 +#if defined(__STDC__)
10942 +#define TYPEDEF_UINT64
10943 +#endif
10944 +
10945 +#endif /* __ICL */
10946 +
10947 +
10948 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10949 +
10950 +/* pick up ushort & uint from standard types.h */
10951 +#if defined(linux) && defined(__KERNEL__)
10952 +
10953 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10954 +
10955 +#else
10956 +
10957 +#include <sys/types.h>
10958 +
10959 +#endif
10960 +
10961 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10962 +
10963 +#if defined(MACOSX) && defined(KERNEL)
10964 +#include <IOKit/IOTypes.h>
10965 +#endif
10966 +
10967 +
10968 +/* use the default typedefs in the next section of this file */
10969 +#define USE_TYPEDEF_DEFAULTS
10970 +
10971 +#endif /* SITE_TYPEDEFS */
10972 +
10973 +
10974 +/*******************************************************************************
10975 + * Default Typedefs
10976 + *******************************************************************************/
10977 +
10978 +#ifdef USE_TYPEDEF_DEFAULTS
10979 +#undef USE_TYPEDEF_DEFAULTS
10980 +
10981 +#ifndef TYPEDEF_BOOL
10982 +typedef /*@abstract@*/ unsigned char bool;
10983 +#endif
10984 +
10985 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10986 +
10987 +#ifndef TYPEDEF_UCHAR
10988 +typedef unsigned char uchar;
10989 +#endif
10990 +
10991 +#ifndef TYPEDEF_USHORT
10992 +typedef unsigned short ushort;
10993 +#endif
10994 +
10995 +#ifndef TYPEDEF_UINT
10996 +typedef unsigned int uint;
10997 +#endif
10998 +
10999 +#ifndef TYPEDEF_ULONG
11000 +typedef unsigned long ulong;
11001 +#endif
11002 +
11003 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
11004 +
11005 +#ifndef TYPEDEF_UINT8
11006 +typedef unsigned char uint8;
11007 +#endif
11008 +
11009 +#ifndef TYPEDEF_UINT16
11010 +typedef unsigned short uint16;
11011 +#endif
11012 +
11013 +#ifndef TYPEDEF_UINT32
11014 +typedef unsigned int uint32;
11015 +#endif
11016 +
11017 +#ifndef TYPEDEF_UINT64
11018 +typedef unsigned long long uint64;
11019 +#endif
11020 +
11021 +#ifndef TYPEDEF_UINTPTR
11022 +typedef unsigned int uintptr;
11023 +#endif
11024 +
11025 +#ifndef TYPEDEF_INT8
11026 +typedef signed char int8;
11027 +#endif
11028 +
11029 +#ifndef TYPEDEF_INT16
11030 +typedef signed short int16;
11031 +#endif
11032 +
11033 +#ifndef TYPEDEF_INT32
11034 +typedef signed int int32;
11035 +#endif
11036 +
11037 +#ifndef TYPEDEF_INT64
11038 +typedef signed long long int64;
11039 +#endif
11040 +
11041 +/*----------------------- define float32/64, float_t -----------------------*/
11042 +
11043 +#ifndef TYPEDEF_FLOAT32
11044 +typedef float float32;
11045 +#endif
11046 +
11047 +#ifndef TYPEDEF_FLOAT64
11048 +typedef double float64;
11049 +#endif
11050 +
11051 +/*
11052 + * abstracted floating point type allows for compile time selection of
11053 + * single or double precision arithmetic. Compiling with -DFLOAT32
11054 + * selects single precision; the default is double precision.
11055 + */
11056 +
11057 +#ifndef TYPEDEF_FLOAT_T
11058 +
11059 +#if defined(FLOAT32)
11060 +typedef float32 float_t;
11061 +#else /* default to double precision floating point */
11062 +typedef float64 float_t;
11063 +#endif
11064 +
11065 +#endif /* TYPEDEF_FLOAT_T */
11066 +
11067 +/*----------------------- define macro values -----------------------------*/
11068 +
11069 +#ifndef FALSE
11070 +#define FALSE 0
11071 +#endif
11072 +
11073 +#ifndef TRUE
11074 +#define TRUE 1
11075 +#endif
11076 +
11077 +#ifndef NULL
11078 +#define NULL 0
11079 +#endif
11080 +
11081 +#ifndef OFF
11082 +#define OFF 0
11083 +#endif
11084 +
11085 +#ifndef ON
11086 +#define ON 1
11087 +#endif
11088 +
11089 +#define AUTO (-1)
11090 +
11091 +/* Reclaiming text and data :
11092 + The following macros specify special linker sections that can be reclaimed
11093 + after a system is considered 'up'.
11094 + */
11095 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11096 +extern bool bcmreclaimed;
11097 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11098 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11099 +#define BCMINIT(_id) _id##_ini
11100 +#else
11101 +#define BCMINITDATA(_data) _data
11102 +#define BCMINITFN(_fn) _fn
11103 +#define BCMINIT(_id) _id
11104 +#define bcmreclaimed 0
11105 +#endif
11106 +
11107 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11108 +
11109 +#ifndef PTRSZ
11110 +#define PTRSZ sizeof (char*)
11111 +#endif
11112 +
11113 +#ifndef INLINE
11114 +
11115 +#ifdef _MSC_VER
11116 +
11117 +#define INLINE __inline
11118 +
11119 +#elif __GNUC__
11120 +
11121 +#define INLINE __inline__
11122 +
11123 +#else
11124 +
11125 +#define INLINE
11126 +
11127 +#endif /* _MSC_VER */
11128 +
11129 +#endif /* INLINE */
11130 +
11131 +#undef TYPEDEF_BOOL
11132 +#undef TYPEDEF_UCHAR
11133 +#undef TYPEDEF_USHORT
11134 +#undef TYPEDEF_UINT
11135 +#undef TYPEDEF_ULONG
11136 +#undef TYPEDEF_UINT8
11137 +#undef TYPEDEF_UINT16
11138 +#undef TYPEDEF_UINT32
11139 +#undef TYPEDEF_UINT64
11140 +#undef TYPEDEF_UINTPTR
11141 +#undef TYPEDEF_INT8
11142 +#undef TYPEDEF_INT16
11143 +#undef TYPEDEF_INT32
11144 +#undef TYPEDEF_INT64
11145 +#undef TYPEDEF_FLOAT32
11146 +#undef TYPEDEF_FLOAT64
11147 +#undef TYPEDEF_FLOAT_T
11148 +
11149 +#endif /* USE_TYPEDEF_DEFAULTS */
11150 +
11151 +#endif /* _TYPEDEFS_H_ */
11152 diff -urN linux.old/arch/mips/bcm947xx/int-handler.S linux.dev/arch/mips/bcm947xx/int-handler.S
11153 --- linux.old/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
11154 +++ linux.dev/arch/mips/bcm947xx/int-handler.S 2006-01-12 00:20:30.745133000 +0100
11155 @@ -0,0 +1,48 @@
11156 +/*
11157 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11158 + *
11159 + * This program is free software; you can redistribute it and/or modify it
11160 + * under the terms of the GNU General Public License as published by the
11161 + * Free Software Foundation; either version 2 of the License, or (at your
11162 + * option) any later version.
11163 + *
11164 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11165 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11166 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11167 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11168 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11169 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11170 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11171 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11172 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11173 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11174 + *
11175 + * You should have received a copy of the GNU General Public License along
11176 + * with this program; if not, write to the Free Software Foundation, Inc.,
11177 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11178 + */
11179 +
11180 +#include <asm/asm.h>
11181 +#include <asm/mipsregs.h>
11182 +#include <asm/regdef.h>
11183 +#include <asm/stackframe.h>
11184 +
11185 + .text
11186 + .set noreorder
11187 + .set noat
11188 + .align 5
11189 +
11190 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
11191 + SAVE_ALL
11192 + CLI
11193 +
11194 + .set at
11195 + .set noreorder
11196 +
11197 + jal bcm47xx_irq_dispatch
11198 + move a0, sp
11199 +
11200 + j ret_from_irq
11201 + nop
11202 +
11203 + END(bcm47xx_irq_handler)
11204 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11205 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11206 +++ linux.dev/arch/mips/bcm947xx/irq.c 2006-01-12 00:20:30.745133000 +0100
11207 @@ -0,0 +1,67 @@
11208 +/*
11209 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11210 + *
11211 + * This program is free software; you can redistribute it and/or modify it
11212 + * under the terms of the GNU General Public License as published by the
11213 + * Free Software Foundation; either version 2 of the License, or (at your
11214 + * option) any later version.
11215 + *
11216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11226 + *
11227 + * You should have received a copy of the GNU General Public License along
11228 + * with this program; if not, write to the Free Software Foundation, Inc.,
11229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11230 + */
11231 +
11232 +#include <linux/config.h>
11233 +#include <linux/errno.h>
11234 +#include <linux/init.h>
11235 +#include <linux/interrupt.h>
11236 +#include <linux/irq.h>
11237 +#include <linux/module.h>
11238 +#include <linux/smp.h>
11239 +#include <linux/types.h>
11240 +
11241 +#include <asm/cpu.h>
11242 +#include <asm/io.h>
11243 +#include <asm/irq.h>
11244 +#include <asm/irq_cpu.h>
11245 +
11246 +extern asmlinkage void bcm47xx_irq_handler(void);
11247 +
11248 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
11249 +{
11250 + u32 cause;
11251 +
11252 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11253 +
11254 + clear_c0_status(cause);
11255 +
11256 + if (cause & CAUSEF_IP7)
11257 + do_IRQ(7, regs);
11258 + if (cause & CAUSEF_IP2)
11259 + do_IRQ(2, regs);
11260 + if (cause & CAUSEF_IP3)
11261 + do_IRQ(3, regs);
11262 + if (cause & CAUSEF_IP4)
11263 + do_IRQ(4, regs);
11264 + if (cause & CAUSEF_IP5)
11265 + do_IRQ(5, regs);
11266 + if (cause & CAUSEF_IP6)
11267 + do_IRQ(6, regs);
11268 +}
11269 +
11270 +void __init arch_init_irq(void)
11271 +{
11272 + set_except_vector(0, bcm47xx_irq_handler);
11273 + mips_cpu_irq_init(0);
11274 +}
11275 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11276 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11277 +++ linux.dev/arch/mips/bcm947xx/pci.c 2006-01-12 00:20:30.745133000 +0100
11278 @@ -0,0 +1,215 @@
11279 +#include <linux/kernel.h>
11280 +#include <linux/init.h>
11281 +#include <linux/pci.h>
11282 +#include <linux/types.h>
11283 +
11284 +#include <asm/cpu.h>
11285 +#include <asm/io.h>
11286 +
11287 +#include <typedefs.h>
11288 +#include <osl.h>
11289 +#include <sbutils.h>
11290 +#include <sbmips.h>
11291 +#include <sbconfig.h>
11292 +#include <sbpci.h>
11293 +#include <bcmdevs.h>
11294 +#include <pcicfg.h>
11295 +
11296 +extern sb_t *sbh;
11297 +extern spinlock_t sbh_lock;
11298 +
11299 +
11300 +static int
11301 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11302 + int reg, int size, u32 *val)
11303 +{
11304 + int ret;
11305 + unsigned long flags;
11306 +
11307 + spin_lock_irqsave(&sbh_lock, flags);
11308 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11309 + spin_unlock_irqrestore(&sbh_lock, flags);
11310 +
11311 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11312 +}
11313 +
11314 +static int
11315 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11316 + int reg, int size, u32 val)
11317 +{
11318 + int ret;
11319 + unsigned long flags;
11320 +
11321 + spin_lock_irqsave(&sbh_lock, flags);
11322 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11323 + spin_unlock_irqrestore(&sbh_lock, flags);
11324 +
11325 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11326 +}
11327 +
11328 +
11329 +static struct pci_ops sb_pci_ops = {
11330 + .read = sb_pci_read_config,
11331 + .write = sb_pci_write_config,
11332 +};
11333 +
11334 +static struct resource sb_pci_mem_resource = {
11335 + .name = "SB PCI Memory resources",
11336 + .start = SB_ENUM_BASE,
11337 + .end = SB_ENUM_LIM - 1,
11338 + .flags = IORESOURCE_MEM,
11339 +};
11340 +
11341 +static struct resource sb_pci_io_resource = {
11342 + .name = "SB PCI I/O resources",
11343 + .start = 0x000,
11344 + .end = 0x0FF,
11345 + .flags = IORESOURCE_IO,
11346 +};
11347 +
11348 +static struct pci_controller bcm47xx_sb_pci_controller = {
11349 + .pci_ops = &sb_pci_ops,
11350 + .mem_resource = &sb_pci_mem_resource,
11351 + .io_resource = &sb_pci_io_resource,
11352 +};
11353 +
11354 +static struct resource ext_pci_mem_resource = {
11355 + .name = "Ext PCI Memory resources",
11356 + .start = 0x40000000,
11357 + .end = 0x7fffffff,
11358 + .flags = IORESOURCE_MEM,
11359 +};
11360 +
11361 +static struct resource ext_pci_io_resource = {
11362 + .name = "Ext PCI I/O resources",
11363 + .start = 0x100,
11364 + .end = 0x1FF,
11365 + .flags = IORESOURCE_IO,
11366 +};
11367 +
11368 +static struct pci_controller bcm47xx_ext_pci_controller = {
11369 + .pci_ops = &sb_pci_ops,
11370 + .io_resource = &ext_pci_io_resource,
11371 + .mem_resource = &ext_pci_mem_resource,
11372 + .mem_offset = 0x24000000,
11373 +};
11374 +
11375 +void bcm47xx_pci_init(void)
11376 +{
11377 + unsigned long flags;
11378 +
11379 + spin_lock_irqsave(&sbh_lock, flags);
11380 + sbpci_init(sbh);
11381 + spin_unlock_irqrestore(&sbh_lock, flags);
11382 +
11383 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11384 +
11385 + register_pci_controller(&bcm47xx_sb_pci_controller);
11386 + register_pci_controller(&bcm47xx_ext_pci_controller);
11387 +}
11388 +
11389 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11390 +{
11391 + u8 irq;
11392 +
11393 + if (dev->bus->number == 1)
11394 + return 2;
11395 +
11396 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11397 + return irq + 2;
11398 +}
11399 +
11400 +u32 pci_iobase = 0x100;
11401 +u32 pci_membase = SB_PCI_DMA;
11402 +
11403 +static void bcm47xx_fixup_device(struct pci_dev *d)
11404 +{
11405 + struct resource *res;
11406 + int pos, size;
11407 + u32 *base;
11408 +
11409 + if (d->bus->number == 0)
11410 + return;
11411 +
11412 + printk("PCI: Fixing up device %s\n", pci_name(d));
11413 +
11414 + /* Fix up resource bases */
11415 + for (pos = 0; pos < 6; pos++) {
11416 + res = &d->resource[pos];
11417 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11418 + if (res->end) {
11419 + size = res->end - res->start + 1;
11420 + if (*base & (size - 1))
11421 + *base = (*base + size) & ~(size - 1);
11422 + res->start = *base;
11423 + res->end = res->start + size - 1;
11424 + *base += size;
11425 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11426 + }
11427 + /* Fix up PCI bridge BAR0 only */
11428 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11429 + break;
11430 + }
11431 + /* Fix up interrupt lines */
11432 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11433 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11434 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11435 +}
11436 +
11437 +
11438 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11439 +{
11440 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11441 + return;
11442 +
11443 + printk("PCI: fixing up bridge\n");
11444 +
11445 + /* Enable PCI bridge bus mastering and memory space */
11446 + pci_set_master(dev);
11447 + pcibios_enable_device(dev, ~0);
11448 +
11449 + /* Enable PCI bridge BAR1 prefetch and burst */
11450 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11451 +}
11452 +
11453 +/* Do platform specific device initialization at pci_enable_device() time */
11454 +int pcibios_plat_dev_init(struct pci_dev *dev)
11455 +{
11456 + uint coreidx;
11457 + unsigned long flags;
11458 +
11459 + bcm47xx_fixup_device(dev);
11460 +
11461 + /* These cores come out of reset enabled */
11462 + if ((dev->bus->number != 0) ||
11463 + (dev->device == SB_MIPS) ||
11464 + (dev->device == SB_MIPS33) ||
11465 + (dev->device == SB_EXTIF) ||
11466 + (dev->device == SB_CC))
11467 + return 0;
11468 +
11469 + /* Do a core reset */
11470 + spin_lock_irqsave(&sbh_lock, flags);
11471 + coreidx = sb_coreidx(sbh);
11472 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11473 + /*
11474 + * The USB core requires a special bit to be set during core
11475 + * reset to enable host (OHCI) mode. Resetting the SB core in
11476 + * pcibios_enable_device() is a hack for compatibility with
11477 + * vanilla usb-ohci so that it does not have to know about
11478 + * SB. A driver that wants to use the USB core in device mode
11479 + * should know about SB and should reset the bit back to 0
11480 + * after calling pcibios_enable_device().
11481 + */
11482 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11483 + sb_core_reset(sbh, 1 << 29);
11484 + } else {
11485 + sb_core_reset(sbh, 0);
11486 + }
11487 + sb_setcoreidx(sbh, coreidx);
11488 + spin_unlock_irqrestore(&sbh_lock, flags);
11489 +
11490 + return 0;
11491 +}
11492 +
11493 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11494 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11495 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11496 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-01-12 00:20:30.745133000 +0100
11497 @@ -0,0 +1,59 @@
11498 +/*
11499 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11500 + *
11501 + * This program is free software; you can redistribute it and/or modify it
11502 + * under the terms of the GNU General Public License as published by the
11503 + * Free Software Foundation; either version 2 of the License, or (at your
11504 + * option) any later version.
11505 + *
11506 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11507 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11508 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11509 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11510 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11511 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11512 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11513 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11514 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11515 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11516 + *
11517 + * You should have received a copy of the GNU General Public License along
11518 + * with this program; if not, write to the Free Software Foundation, Inc.,
11519 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11520 + */
11521 +
11522 +#include <linux/init.h>
11523 +#include <linux/mm.h>
11524 +#include <linux/sched.h>
11525 +#include <linux/bootmem.h>
11526 +
11527 +#include <asm/addrspace.h>
11528 +#include <asm/bootinfo.h>
11529 +#include <asm/pmon.h>
11530 +
11531 +const char *get_system_type(void)
11532 +{
11533 + return "Broadcom BCM47xx";
11534 +}
11535 +
11536 +void __init prom_init(void)
11537 +{
11538 + unsigned long mem;
11539 +
11540 + mips_machgroup = MACH_GROUP_BRCM;
11541 + mips_machtype = MACH_BCM47XX;
11542 +
11543 + /* Figure out memory size by finding aliases */
11544 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11545 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11546 + *(unsigned long *)(prom_init))
11547 + break;
11548 + }
11549 +
11550 + add_memory_region(0, mem, BOOT_MEM_RAM);
11551 +}
11552 +
11553 +unsigned long __init prom_free_prom_memory(void)
11554 +{
11555 + return 0;
11556 +}
11557 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11558 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11559 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-01-12 00:20:30.749133250 +0100
11560 @@ -0,0 +1,157 @@
11561 +/*
11562 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11563 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11564 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11565 + *
11566 + * This program is free software; you can redistribute it and/or modify it
11567 + * under the terms of the GNU General Public License as published by the
11568 + * Free Software Foundation; either version 2 of the License, or (at your
11569 + * option) any later version.
11570 + *
11571 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11572 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11573 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11574 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11575 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11576 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11577 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11578 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11579 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11580 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11581 + *
11582 + * You should have received a copy of the GNU General Public License along
11583 + * with this program; if not, write to the Free Software Foundation, Inc.,
11584 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11585 + */
11586 +
11587 +#include <linux/init.h>
11588 +#include <linux/types.h>
11589 +#include <linux/tty.h>
11590 +#include <linux/serial.h>
11591 +#include <linux/serial_core.h>
11592 +#include <linux/serial_reg.h>
11593 +#include <asm/bootinfo.h>
11594 +#include <asm/time.h>
11595 +#include <asm/reboot.h>
11596 +
11597 +#include <typedefs.h>
11598 +#include <osl.h>
11599 +#include <sbutils.h>
11600 +#include <sbmips.h>
11601 +#include <sbpci.h>
11602 +#include <sbconfig.h>
11603 +#include <bcmdevs.h>
11604 +#include <bcmutils.h>
11605 +#include <bcmnvram.h>
11606 +
11607 +extern void bcm47xx_pci_init(void);
11608 +extern void bcm47xx_time_init(void);
11609 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11610 +void *sbh;
11611 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11612 +int boardflags;
11613 +
11614 +static int ser_line = 0;
11615 +
11616 +typedef struct {
11617 + void *regs;
11618 + uint irq;
11619 + uint baud_base;
11620 + uint reg_shift;
11621 +} serial_port;
11622 +
11623 +static serial_port ports[4];
11624 +static int num_ports = 0;
11625 +
11626 +static void
11627 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11628 +{
11629 + ports[num_ports].regs = regs;
11630 + ports[num_ports].irq = irq;
11631 + ports[num_ports].baud_base = baud_base;
11632 + ports[num_ports].reg_shift = reg_shift;
11633 + num_ports++;
11634 +}
11635 +
11636 +static void
11637 +do_serial_add(serial_port *port)
11638 +{
11639 + void *regs;
11640 + uint irq;
11641 + uint baud_base;
11642 + uint reg_shift;
11643 + struct uart_port s;
11644 +
11645 + regs = port->regs;
11646 + irq = port->irq;
11647 + baud_base = port->baud_base;
11648 + reg_shift = port->reg_shift;
11649 +
11650 + memset(&s, 0, sizeof(s));
11651 +
11652 + s.line = ser_line++;
11653 + s.membase = regs;
11654 + s.irq = irq + 2;
11655 + s.uartclk = baud_base;
11656 + s.flags = ASYNC_BOOT_AUTOCONF;
11657 + s.iotype = SERIAL_IO_MEM;
11658 + s.regshift = reg_shift;
11659 +
11660 + if (early_serial_setup(&s) != 0) {
11661 + printk(KERN_ERR "Serial setup failed!\n");
11662 + }
11663 +}
11664 +
11665 +static void bcm47xx_machine_restart(char *command)
11666 +{
11667 + printk("Please stand by while rebooting the system...\n");
11668 +
11669 + /* Set the watchdog timer to reset immediately */
11670 + local_irq_disable();
11671 + sb_watchdog(sbh, 1);
11672 + while (1);
11673 +}
11674 +
11675 +static void bcm47xx_machine_halt(void)
11676 +{
11677 + /* Disable interrupts and watchdog and spin forever */
11678 + local_irq_disable();
11679 + sb_watchdog(sbh, 0);
11680 + while (1);
11681 +}
11682 +
11683 +void __init plat_setup(void)
11684 +{
11685 + char *s;
11686 + int i;
11687 +
11688 + sbh = (void *) sb_kattach();
11689 + sb_mips_init(sbh);
11690 +
11691 + bcm47xx_pci_init();
11692 +
11693 + sb_serial_init(sbh, serial_add);
11694 + boardflags = getintvar(NULL, "boardflags");
11695 +
11696 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11697 + s = early_nvram_get("kernel_args");
11698 + if (!s) s = "";
11699 + if (!strncmp(s, "console=ttyS1", 13)) {
11700 + for (i = num_ports; i; i--)
11701 + do_serial_add(&ports[i - 1]);
11702 + } else {
11703 + for (i = 0; i < num_ports; i++)
11704 + do_serial_add(&ports[i]);
11705 + }
11706 +
11707 + _machine_restart = bcm47xx_machine_restart;
11708 + _machine_halt = bcm47xx_machine_halt;
11709 + _machine_power_off = bcm47xx_machine_halt;
11710 +
11711 + board_time_init = bcm47xx_time_init;
11712 + board_timer_setup = bcm47xx_timer_setup;
11713 +}
11714 +
11715 +EXPORT_SYMBOL(sbh);
11716 +EXPORT_SYMBOL(sbh_lock);
11717 +EXPORT_SYMBOL(boardflags);
11718 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11719 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11720 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-01-12 00:20:30.749133250 +0100
11721 @@ -0,0 +1,59 @@
11722 +/*
11723 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11724 + *
11725 + * This program is free software; you can redistribute it and/or modify it
11726 + * under the terms of the GNU General Public License as published by the
11727 + * Free Software Foundation; either version 2 of the License, or (at your
11728 + * option) any later version.
11729 + *
11730 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11731 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11732 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11733 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11734 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11735 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11736 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11737 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11738 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11739 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11740 + *
11741 + * You should have received a copy of the GNU General Public License along
11742 + * with this program; if not, write to the Free Software Foundation, Inc.,
11743 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11744 + */
11745 +
11746 +#include <linux/config.h>
11747 +#include <linux/init.h>
11748 +#include <linux/kernel.h>
11749 +#include <linux/sched.h>
11750 +#include <linux/serial_reg.h>
11751 +#include <linux/interrupt.h>
11752 +#include <asm/addrspace.h>
11753 +#include <asm/io.h>
11754 +#include <asm/time.h>
11755 +
11756 +void __init
11757 +bcm47xx_time_init(void)
11758 +{
11759 + unsigned int hz;
11760 +
11761 + /*
11762 + * Use deterministic values for initial counter interrupt
11763 + * so that calibrate delay avoids encountering a counter wrap.
11764 + */
11765 + write_c0_count(0);
11766 + write_c0_compare(0xffff);
11767 +
11768 + hz = 200 * 1000 * 1000;
11769 +
11770 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11771 + mips_hpt_frequency = hz / 2;
11772 +
11773 +}
11774 +
11775 +void __init
11776 +bcm47xx_timer_setup(struct irqaction *irq)
11777 +{
11778 + /* Enable the timer interrupt */
11779 + setup_irq(7, irq);
11780 +}
11781 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11782 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-01-12 00:25:32.684003000 +0100
11783 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-01-12 00:20:30.757133750 +0100
11784 @@ -656,6 +656,28 @@
11785 }
11786
11787
11788 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11789 +{
11790 + decode_config1(c);
11791 + switch (c->processor_id & 0xff00) {
11792 + case PRID_IMP_BCM3302:
11793 + c->cputype = CPU_BCM3302;
11794 + c->isa_level = MIPS_CPU_ISA_M32;
11795 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11796 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11797 + break;
11798 + case PRID_IMP_BCM4710:
11799 + c->cputype = CPU_BCM4710;
11800 + c->isa_level = MIPS_CPU_ISA_M32;
11801 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11802 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11803 + break;
11804 + default:
11805 + c->cputype = CPU_UNKNOWN;
11806 + break;
11807 + }
11808 +}
11809 +
11810 __init void cpu_probe(void)
11811 {
11812 struct cpuinfo_mips *c = &current_cpu_data;
11813 @@ -678,6 +700,9 @@
11814 case PRID_COMP_SIBYTE:
11815 cpu_probe_sibyte(c);
11816 break;
11817 + case PRID_COMP_BROADCOM:
11818 + cpu_probe_broadcom(c);
11819 + break;
11820 case PRID_COMP_SANDCRAFT:
11821 cpu_probe_sandcraft(c);
11822 break;
11823 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11824 --- linux.old/arch/mips/kernel/head.S 2006-01-12 00:25:32.684003000 +0100
11825 +++ linux.dev/arch/mips/kernel/head.S 2006-01-12 00:20:30.761134000 +0100
11826 @@ -107,6 +107,14 @@
11827 #endif
11828 .endm
11829
11830 +#ifdef CONFIG_BCM4710
11831 +#undef eret
11832 +#define eret nop; nop; eret
11833 +#endif
11834 +
11835 + j kernel_entry
11836 + nop
11837 +
11838 /*
11839 * Reserved space for exception handlers.
11840 * Necessary for machines which link their kernels at KSEG0.
11841 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11842 --- linux.old/arch/mips/kernel/proc.c 2006-01-12 00:25:32.692003500 +0100
11843 +++ linux.dev/arch/mips/kernel/proc.c 2006-01-12 00:20:30.765134250 +0100
11844 @@ -82,6 +82,8 @@
11845 [CPU_VR4181] = "NEC VR4181",
11846 [CPU_VR4181A] = "NEC VR4181A",
11847 [CPU_SR71000] = "Sandcraft SR71000",
11848 + [CPU_BCM3302] = "Broadcom BCM3302",
11849 + [CPU_BCM4710] = "Broadcom BCM4710",
11850 [CPU_PR4450] = "Philips PR4450",
11851 };
11852
11853 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11854 --- linux.old/arch/mips/mm/tlbex.c 2006-01-12 00:25:32.796010000 +0100
11855 +++ linux.dev/arch/mips/mm/tlbex.c 2006-01-12 00:20:31.137157500 +0100
11856 @@ -862,6 +862,8 @@
11857 case CPU_4KSC:
11858 case CPU_20KC:
11859 case CPU_25KF:
11860 + case CPU_BCM3302:
11861 + case CPU_BCM4710:
11862 tlbw(p);
11863 break;
11864
11865 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11866 --- linux.old/include/asm-mips/bootinfo.h 2006-01-12 00:25:32.800010250 +0100
11867 +++ linux.dev/include/asm-mips/bootinfo.h 2006-01-12 00:20:30.777135000 +0100
11868 @@ -218,6 +218,12 @@
11869 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11870 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11871
11872 +/*
11873 + * Valid machtype for group Broadcom
11874 + */
11875 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11876 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11877 +
11878 #define CL_SIZE COMMAND_LINE_SIZE
11879
11880 const char *get_system_type(void);
11881 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11882 --- linux.old/include/asm-mips/cpu.h 2006-01-12 00:25:32.800010250 +0100
11883 +++ linux.dev/include/asm-mips/cpu.h 2006-01-12 00:20:30.777135000 +0100
11884 @@ -102,6 +102,13 @@
11885 #define PRID_IMP_SR71000 0x0400
11886
11887 /*
11888 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11889 + */
11890 +
11891 +#define PRID_IMP_BCM4710 0x4000
11892 +#define PRID_IMP_BCM3302 0x9000
11893 +
11894 +/*
11895 * Definitions for 7:0 on legacy processors
11896 */
11897
11898 @@ -196,7 +203,9 @@
11899 #define CPU_34K 60
11900 #define CPU_PR4450 61
11901 #define CPU_SB1A 62
11902 -#define CPU_LAST 62
11903 +#define CPU_BCM3302 63
11904 +#define CPU_BCM4710 64
11905 +#define CPU_LAST 64
11906
11907 /*
11908 * ISA Level encodings
11909 diff -urN linux.old/include/linux/init.h linux.dev/include/linux/init.h
11910 --- linux.old/include/linux/init.h 2006-01-12 00:25:32.828012000 +0100
11911 +++ linux.dev/include/linux/init.h 2006-01-12 00:20:30.777135000 +0100
11912 @@ -86,6 +86,8 @@
11913 static initcall_t __initcall_##fn __attribute_used__ \
11914 __attribute__((__section__(".initcall" level ".init"))) = fn
11915
11916 +#define early_initcall(fn) __define_initcall(".early1",fn)
11917 +
11918 #define core_initcall(fn) __define_initcall("1",fn)
11919 #define postcore_initcall(fn) __define_initcall("2",fn)
11920 #define arch_initcall(fn) __define_initcall("3",fn)
11921 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11922 --- linux.old/include/linux/pci_ids.h 2006-01-12 00:25:32.828012000 +0100
11923 +++ linux.dev/include/linux/pci_ids.h 2006-01-12 00:20:30.781135250 +0100
11924 @@ -1836,6 +1836,7 @@
11925 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11926 #define PCI_DEVICE_ID_BCM4401 0x4401
11927 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11928 +#define PCI_DEVICE_ID_BCM4713 0x4713
11929
11930 #define PCI_VENDOR_ID_TOPIC 0x151f
11931 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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