package/lqdsl/src/ifxmips_atm_danube.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_danube.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include <lantiq.h>
  49 #include <lantiq_regs.h>
  50 #include "ifxmips_compat.h"
  51 #include "ifxmips_atm_core.h"
  52 #include "ifxmips_atm_fw_danube.h"
  53
  54
  55
  56 /*
  57  * ####################################
  58  *              Definition
  59  * ####################################
  60  */
  61
  62 /*
  63  *  EMA Settings
  64  */
  65 #define EMA_CMD_BUF_LEN      0x0040
  66 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  67 #define EMA_DATA_BUF_LEN     0x0100
  68 #define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
  69 #define EMA_WRITE_BURST      0x2
  70 #define EMA_READ_BURST       0x2
  71
  72
  73
  74 /*
  75  * ####################################
  76  *             Declaration
  77  * ####################################
  78  */
  79
  80 /*
  81  *  Hardware Init/Uninit Functions
  82  */
  83 static inline void init_pmu(void);
  84 static inline void uninit_pmu(void);
  85 static inline void init_ema(void);
  86 static inline void init_mailbox(void);
  87 static inline void init_atm_tc(void);
  88 static inline void clear_share_buffer(void);
  89
  90
  91
  92 /*
  93  * ####################################
  94  *            Local Variable
  95  * ####################################
  96  */
  97
  98
  99
 100 /*
 101  * ####################################
 102  *            Local Function
 103  * ####################################
 104  */
 105
 106 static inline void init_pmu(void)
 107 {
 108     //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
 109     PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 110     PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 111     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 112     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 113     PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 114     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 115     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
 116 }
 117
 118 static inline void uninit_pmu(void)
 119 {
 120     PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 121     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 122     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 123     PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 124     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 125     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 126     PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
 127 }
 128
 129 static inline void init_ema(void)
 130 {
 131     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 132     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 133     IFX_REG_W32(0x000000FF, EMA_IER);
 134     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 135 }
 136
 137 static inline void init_mailbox(void)
 138 {
 139     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 140     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 141     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 142     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 143 }
 144
 145 static inline void init_atm_tc(void)
 146 {
 147     //  for ReTX expansion in future
 148     //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); //  pnum = 6
 149     //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); //  pnum = 6
 150 }
 151
 152 static inline void clear_share_buffer(void)
 153 {
 154     volatile u32 *p = SB_RAM0_ADDR(0);
 155     unsigned int i;
 156
 157     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 158         IFX_REG_W32(0, p++);
 159 }
 160
 161 /*
 162  *  Description:
 163  *    Download PPE firmware binary code.
 164  *  Input:
 165  *    src       --- u32 *, binary code buffer
 166  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 167  *  Output:
 168  *    int       --- IFX_SUCCESS:    Success
 169  *                  else:           Error Code
 170  */
 171 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 172 {
 173     volatile u32 *dest;
 174
 175     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 176         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 177         return IFX_ERROR;
 178
 179     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 180         IFX_REG_W32(0x00, CDM_CFG);
 181     else
 182         IFX_REG_W32(0x02, CDM_CFG);
 183
 184     /*  copy code   */
 185     dest = CDM_CODE_MEMORY(0, 0);
 186     while ( code_dword_len-- > 0 )
 187         IFX_REG_W32(*code_src++, dest++);
 188
 189     /*  copy data   */
 190     dest = CDM_DATA_MEMORY(0, 0);
 191     while ( data_dword_len-- > 0 )
 192         IFX_REG_W32(*data_src++, dest++);
 193
 194     return IFX_SUCCESS;
 195 }
 196
 197
 198
 199 /*
 200  * ####################################
 201  *           Global Function
 202  * ####################################
 203  */
 204
 205 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
 206 {
 207     ASSERT(major != NULL, "pointer is NULL");
 208     ASSERT(minor != NULL, "pointer is NULL");
 209
 210     *major = ATM_FW_VER_MAJOR;
 211     *minor = ATM_FW_VER_MINOR;
 212 }
 213
 214 void ifx_atm_init_chip(void)
 215 {
 216     init_pmu();
 217
 218     init_ema();
 219
 220     init_mailbox();
 221
 222     init_atm_tc();
 223
 224     clear_share_buffer();
 225 }
 226
 227 void ifx_atm_uninit_chip(void)
 228 {
 229     uninit_pmu();
 230 }
 231
 232 /*
 233  *  Description:
 234  *    Initialize and start up PP32.
 235  *  Input:
 236  *    none
 237  *  Output:
 238  *    int  --- IFX_SUCCESS: Success
 239  *             else:        Error Code
 240  */
 241 int ifx_pp32_start(int pp32)
 242 {
 243     int ret;
 244
 245     /*  download firmware   */
 246     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 247     if ( ret != IFX_SUCCESS )
 248         return ret;
 249
 250     /*  run PP32    */
 251     IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
 252
 253     /*  idle for a while to let PP32 init itself    */
 254     udelay(10);
 255
 256     return IFX_SUCCESS;
 257 }
 258
 259 /*
 260  *  Description:
 261  *    Halt PP32.
 262  *  Input:
 263  *    none
 264  *  Output:
 265  *    none
 266  */
 267 void ifx_pp32_stop(int pp32)
 268 {
 269     /*  halt PP32   */
 270     IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
 271 }