target/linux/ar71xx/files/drivers/spi/spi_vsc7385.c

   1 /*
   2  * SPI driver for the Vitesse VSC7385 ethernet switch
   3  *
   4  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/bitops.h>
  20 #include <linux/firmware.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/vsc7385.h>
  23
  24 #define DRV_NAME        "spi-vsc7385"
  25 #define DRV_DESC        "Vitesse VSC7385 Gbit ethernet switch driver"
  26 #define DRV_VERSION     "0.1.0"
  27
  28 #define VSC73XX_BLOCK_MAC       0x1
  29 #define VSC73XX_BLOCK_2         0x2
  30 #define VSC73XX_BLOCK_MII       0x3
  31 #define VSC73XX_BLOCK_4         0x4
  32 #define VSC73XX_BLOCK_5         0x5
  33 #define VSC73XX_BLOCK_SYSTEM    0x7
  34
  35 #define VSC73XX_SUBBLOCK_PORT_0         0
  36 #define VSC73XX_SUBBLOCK_PORT_1         1
  37 #define VSC73XX_SUBBLOCK_PORT_2         2
  38 #define VSC73XX_SUBBLOCK_PORT_3         3
  39 #define VSC73XX_SUBBLOCK_PORT_4         4
  40 #define VSC73XX_SUBBLOCK_PORT_MAC       6
  41
  42 /* MAC Block registers */
  43 #define VSC73XX_MAC_CFG         0x0
  44 #define VSC73XX_ADVPORTM        0x19
  45 #define VSC73XX_RXOCT           0x50
  46 #define VSC73XX_TXOCT           0x51
  47 #define VSC73XX_C_RX0           0x52
  48 #define VSC73XX_C_RX1           0x53
  49 #define VSC73XX_C_RX2           0x54
  50 #define VSC73XX_C_TX0           0x55
  51 #define VSC73XX_C_TX1           0x56
  52 #define VSC73XX_C_TX2           0x57
  53 #define VSC73XX_C_CFG           0x58
  54
  55 /* MAC_CFG register bits */
  56 #define VSC73XX_MAC_CFG_WEXC_DIS        (1 << 31)
  57 #define VSC73XX_MAC_CFG_PORT_RST        (1 << 29)
  58 #define VSC73XX_MAC_CFG_TX_EN           (1 << 28)
  59 #define VSC73XX_MAC_CFG_SEED_LOAD       (1 << 27)
  60 #define VSC73XX_MAC_CFG_FDX             (1 << 18)
  61 #define VSC73XX_MAC_CFG_GIGE            (1 << 17)
  62 #define VSC73XX_MAC_CFG_RX_EN           (1 << 16)
  63 #define VSC73XX_MAC_CFG_VLAN_DBLAWR     (1 << 15)
  64 #define VSC73XX_MAC_CFG_VLAN_AWR        (1 << 14)
  65 #define VSC73XX_MAC_CFG_100_BASE_T      (1 << 13)
  66 #define VSC73XX_MAC_CFG_TX_IPG(x)       ((x & 0x1f) << 6)
  67 #define VSC73XX_MAC_CFG_MAC_RX_RST      (1 << 5)
  68 #define VSC73XX_MAC_CFG_MAC_TX_RST      (1 << 4)
  69 #define VSC73XX_MAC_CFG_CLK_SEL(x)      ((x & 0x3) << 0)
  70
  71 /* ADVPORTM register bits */
  72 #define VSC73XX_ADVPORTM_IFG_PPM        (1 << 7)
  73 #define VSC73XX_ADVPORTM_EXC_COL_CONT   (1 << 6)
  74 #define VSC73XX_ADVPORTM_EXT_PORT       (1 << 5)
  75 #define VSC73XX_ADVPORTM_INV_GTX        (1 << 4)
  76 #define VSC73XX_ADVPORTM_ENA_GTX        (1 << 3)
  77 #define VSC73XX_ADVPORTM_DDR_MODE       (1 << 2)
  78 #define VSC73XX_ADVPORTM_IO_LOOPBACK    (1 << 1)
  79 #define VSC73XX_ADVPORTM_HOST_LOOPBACK  (1 << 0)
  80
  81 /* MII Block registers */
  82 #define VSC73XX_MII_STAT        0x0
  83 #define VSC73XX_MII_CMD         0x1
  84 #define VSC73XX_MII_DATA        0x2
  85
  86 /* System Block registers */
  87 #define VSC73XX_ICPU_SIPAD              0x01
  88 #define VSC73XX_ICPU_CLOCK_DELAY        0x05
  89 #define VSC73XX_ICPU_CTRL               0x10
  90 #define VSC73XX_ICPU_ADDR               0x11
  91 #define VSC73XX_ICPU_SRAM               0x12
  92 #define VSC73XX_ICPU_MBOX_VAL           0x15
  93 #define VSC73XX_ICPU_MBOX_SET           0x16
  94 #define VSC73XX_ICPU_MBOX_CLR           0x17
  95 #define VSC73XX_ICPU_CHIPID             0x18
  96 #define VSC73XX_ICPU_GPIO               0x34
  97
  98 #define VSC73XX_ICPU_CTRL_CLK_DIV       (1 << 8)
  99 #define VSC73XX_ICPU_CTRL_SRST_HOLD     (1 << 7)
 100 #define VSC73XX_ICPU_CTRL_BOOT_EN       (1 << 3)
 101 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN    (1 << 2)
 102 #define VSC73XX_ICPU_CTRL_CLK_EN        (1 << 1)
 103 #define VSC73XX_ICPU_CTRL_SRST          (1 << 0)
 104
 105 #define VSC73XX_CMD_MODE_READ           0
 106 #define VSC73XX_CMD_MODE_WRITE          1
 107 #define VSC73XX_CMD_MODE_SHIFT          4
 108 #define VSC73XX_CMD_BLOCK_SHIFT         5
 109 #define VSC73XX_CMD_BLOCK_MASK          0x7
 110 #define VSC73XX_CMD_SUBBLOCK_MASK       0xf
 111
 112 #define VSC7385_CLOCK_DELAY             ((3 << 4) | 3)
 113 #define VSC7385_CLOCK_DELAY_MASK        ((3 << 4) | 3)
 114
 115 #define VSC73XX_ICPU_CTRL_STOP  (VSC73XX_ICPU_CTRL_SRST_HOLD | \
 116                                  VSC73XX_ICPU_CTRL_BOOT_EN | \
 117                                  VSC73XX_ICPU_CTRL_EXT_ACC_EN)
 118
 119 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
 120                                  VSC73XX_ICPU_CTRL_BOOT_EN | \
 121                                  VSC73XX_ICPU_CTRL_CLK_EN | \
 122                                  VSC73XX_ICPU_CTRL_SRST)
 123
 124 #define VSC7385_ADVPORTM_MASK   (VSC73XX_ADVPORTM_IFG_PPM | \
 125                                  VSC73XX_ADVPORTM_EXC_COL_CONT | \
 126                                  VSC73XX_ADVPORTM_EXT_PORT | \
 127                                  VSC73XX_ADVPORTM_INV_GTX | \
 128                                  VSC73XX_ADVPORTM_ENA_GTX | \
 129                                  VSC73XX_ADVPORTM_DDR_MODE | \
 130                                  VSC73XX_ADVPORTM_IO_LOOPBACK | \
 131                                  VSC73XX_ADVPORTM_HOST_LOOPBACK)
 132
 133 #define VSC7385_ADVPORTM_INIT   (VSC73XX_ADVPORTM_EXT_PORT | \
 134                                  VSC73XX_ADVPORTM_ENA_GTX | \
 135                                  VSC73XX_ADVPORTM_DDR_MODE)
 136
 137 #define VSC7385_MAC_CFG_RESET   (VSC73XX_MAC_CFG_PORT_RST | \
 138                                  VSC73XX_MAC_CFG_MAC_RX_RST | \
 139                                  VSC73XX_MAC_CFG_MAC_TX_RST)
 140
 141 #define VSC7385_MAC_CFG_INIT    (VSC73XX_MAC_CFG_TX_EN | \
 142                                  VSC73XX_MAC_CFG_FDX | \
 143                                  VSC73XX_MAC_CFG_GIGE | \
 144                                  VSC73XX_MAC_CFG_RX_EN | \
 145                                  VSC73XX_MAC_CFG_TX_IPG(6) | \
 146                                  4)
 147
 148 #define VSC73XX_RESET_DELAY     100
 149
 150 struct vsc7385 {
 151         struct spi_device               *spi;
 152         struct mutex                    lock;
 153         struct vsc7385_platform_data    *pdata;
 154 };
 155
 156 static int vsc7385_is_addr_valid(u8 block, u8 subblock)
 157 {
 158         switch (block) {
 159         case VSC73XX_BLOCK_MAC:
 160                 switch (subblock) {
 161                 case 0 ... 4:
 162                 case 6:
 163                         return 1;
 164                 }
 165                 break;
 166
 167         case VSC73XX_BLOCK_2:
 168         case VSC73XX_BLOCK_SYSTEM:
 169                 switch (subblock) {
 170                 case 0:
 171                         return 1;
 172                 }
 173                 break;
 174
 175         case VSC73XX_BLOCK_MII:
 176         case VSC73XX_BLOCK_4:
 177         case VSC73XX_BLOCK_5:
 178                 switch (subblock) {
 179                 case 0 ... 1:
 180                         return 1;
 181                 }
 182                 break;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock)
 189 {
 190         u8 ret;
 191
 192         ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT;
 193         ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT;
 194         ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK;
 195
 196         return ret;
 197 }
 198
 199 static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
 200                         u32 *value)
 201 {
 202         u8 cmd[4];
 203         u8 buf[4];
 204         struct spi_transfer t[2];
 205         struct spi_message m;
 206         int err;
 207
 208         if (!vsc7385_is_addr_valid(block, subblock))
 209                 return -EINVAL;
 210
 211         spi_message_init(&m);
 212
 213         memset(&t, 0, sizeof(t));
 214
 215         t[0].tx_buf = cmd;
 216         t[0].len = sizeof(cmd);
 217         spi_message_add_tail(&t[0], &m);
 218
 219         t[1].rx_buf = buf;
 220         t[1].len = sizeof(buf);
 221         spi_message_add_tail(&t[1], &m);
 222
 223         cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock);
 224         cmd[1] = reg;
 225         cmd[2] = 0;
 226         cmd[3] = 0;
 227
 228         mutex_lock(&vsc->lock);
 229         err = spi_sync(vsc->spi, &m);
 230         mutex_unlock(&vsc->lock);
 231
 232         if (err)
 233                 return err;
 234
 235         *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) |
 236                  (((u32) buf[2]) << 8) | ((u32) buf[3]);
 237
 238         return 0;
 239 }
 240
 241
 242 static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
 243                          u32 value)
 244 {
 245         u8 cmd[2];
 246         u8 buf[4];
 247         struct spi_transfer t[2];
 248         struct spi_message m;
 249         int err;
 250
 251         if (!vsc7385_is_addr_valid(block, subblock))
 252                 return -EINVAL;
 253
 254         spi_message_init(&m);
 255
 256         memset(&t, 0, sizeof(t));
 257
 258         t[0].tx_buf = cmd;
 259         t[0].len = sizeof(cmd);
 260         spi_message_add_tail(&t[0], &m);
 261
 262         t[1].tx_buf = buf;
 263         t[1].len = sizeof(buf);
 264         spi_message_add_tail(&t[1], &m);
 265
 266         cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock);
 267         cmd[1] = reg;
 268
 269         buf[0] = (value >> 24) & 0xff;
 270         buf[1] = (value >> 16) & 0xff;
 271         buf[2] = (value >> 8) & 0xff;
 272         buf[3] = value & 0xff;
 273
 274         mutex_lock(&vsc->lock);
 275         err = spi_sync(vsc->spi, &m);
 276         mutex_unlock(&vsc->lock);
 277
 278         return err;
 279 }
 280
 281 static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block,
 282                                        u8 subblock, u8 reg, u32 value,
 283                                        u32 read_mask, u32 read_val)
 284 {
 285         struct spi_device *spi = vsc->spi;
 286         u32 t;
 287         int err;
 288
 289         err = vsc7385_write(vsc, block, subblock, reg, value);
 290         if (err)
 291                 return err;
 292
 293         err = vsc7385_read(vsc, block, subblock, reg, &t);
 294         if (err)
 295                 return err;
 296
 297         if ((t & read_mask) != read_val) {
 298                 dev_err(&spi->dev, "register write error\n");
 299                 return -EIO;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val)
 306 {
 307         return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 308                              VSC73XX_ICPU_CLOCK_DELAY, val);
 309 }
 310
 311 static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val)
 312 {
 313         return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 314                             VSC73XX_ICPU_CLOCK_DELAY, val);
 315 }
 316
 317 static inline int vsc7385_icpu_stop(struct vsc7385 *vsc)
 318 {
 319         return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
 320                              VSC73XX_ICPU_CTRL_STOP);
 321 }
 322
 323 static inline int vsc7385_icpu_start(struct vsc7385 *vsc)
 324 {
 325         return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
 326                              VSC73XX_ICPU_CTRL_START);
 327 }
 328
 329 static inline int vsc7385_icpu_reset(struct vsc7385 *vsc)
 330 {
 331         int rc;
 332
 333         rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR,
 334                            0x0000);
 335         if (rc)
 336                 dev_err(&vsc->spi->dev,
 337                         "could not reset microcode, err=%d\n", rc);
 338
 339         return rc;
 340 }
 341
 342 static int vsc7385_upload_ucode(struct vsc7385 *vsc)
 343 {
 344         struct spi_device *spi = vsc->spi;
 345         const struct firmware *firmware;
 346         char *ucode_name;
 347         unsigned char *dp;
 348         unsigned int curVal;
 349         int i;
 350         int diffs;
 351         int rc;
 352
 353         ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name
 354                                               : "vsc7385_ucode.bin";
 355         rc = request_firmware(&firmware, ucode_name, &spi->dev);
 356         if (rc) {
 357                 dev_err(&spi->dev, "request_firmware failed, err=%d\n",
 358                         rc);
 359                 return rc;
 360         }
 361
 362         rc = vsc7385_icpu_stop(vsc);
 363         if (rc)
 364                 goto out;
 365
 366         rc = vsc7385_icpu_reset(vsc);
 367         if (rc)
 368                 goto out;
 369
 370         dev_info(&spi->dev, "uploading microcode...\n");
 371
 372         dp = (unsigned char *) firmware->data;
 373         for (i = 0; i < firmware->size; i++) {
 374                 rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 375                                    VSC73XX_ICPU_SRAM, *dp++);
 376                 if (rc) {
 377                         dev_err(&spi->dev, "could not load microcode, err=%d\n",
 378                                 rc);
 379                         goto out;
 380                 }
 381         }
 382
 383         rc = vsc7385_icpu_reset(vsc);
 384         if (rc)
 385                 goto out;
 386
 387         dev_info(&spi->dev, "verifying microcode...\n");
 388
 389         dp = (unsigned char *) firmware->data;
 390         diffs = 0;
 391         for (i = 0; i < firmware->size; i++) {
 392                 rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 393                                   VSC73XX_ICPU_SRAM, &curVal);
 394                 if (rc) {
 395                         dev_err(&spi->dev, "could not read microcode %d\n",rc);
 396                         goto out;
 397                 }
 398
 399                 if (curVal > 0xff) {
 400                         dev_err(&spi->dev, "bad val read: %04x : %02x  %02x\n",
 401                                 i, *dp, curVal);
 402                         rc = -EIO;
 403                         goto out;
 404                 }
 405
 406                 if ((curVal & 0xff) != *dp) {
 407                         diffs++;
 408                         dev_err(&spi->dev, "verify error: %04x : %02x  %02x\n",
 409                                 i, *dp, curVal);
 410
 411                         if (diffs > 4)
 412                                 break;
 413                         }
 414                 dp++;
 415         }
 416
 417         if (diffs) {
 418                 dev_err(&spi->dev, "microcode verification failed\n");
 419                 rc = -EIO;
 420                 goto out;
 421         }
 422
 423         dev_info(&spi->dev, "microcode uploaded\n");
 424
 425         rc = vsc7385_icpu_start(vsc);
 426
 427  out:
 428         release_firmware(firmware);
 429         return rc;
 430 }
 431
 432 static int vsc7385_setup(struct vsc7385 *vsc)
 433 {
 434         int err;
 435
 436         err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 437                                    VSC73XX_ICPU_CLOCK_DELAY,
 438                                    VSC7385_CLOCK_DELAY,
 439                                    VSC7385_CLOCK_DELAY_MASK,
 440                                    VSC7385_CLOCK_DELAY);
 441         if (err)
 442                 goto err;
 443
 444         err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC,
 445                                    VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM,
 446                                    VSC7385_ADVPORTM_INIT,
 447                                    VSC7385_ADVPORTM_MASK,
 448                                    VSC7385_ADVPORTM_INIT);
 449         if (err)
 450                 goto err;
 451
 452         err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
 453                             VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET);
 454         if (err)
 455                 goto err;
 456
 457         err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
 458                             VSC73XX_MAC_CFG, VSC7385_MAC_CFG_INIT);
 459         if (err)
 460                 goto err;
 461
 462         return 0;
 463
 464  err:
 465         return err;
 466 }
 467
 468 static int vsc7385_detect(struct vsc7385 *vsc)
 469 {
 470         struct spi_device *spi = vsc->spi;
 471         u32 t;
 472         u32 id;
 473         u32 rev;
 474         int err;
 475
 476         err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 477                                 VSC73XX_ICPU_MBOX_VAL, &t);
 478         if (err) {
 479                 dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err);
 480                 return err;
 481         }
 482
 483         if (t == 0xffffffff) {
 484                 dev_dbg(&spi->dev, "assert chip reset\n");
 485                 if (vsc->pdata->reset)
 486                         vsc->pdata->reset();
 487
 488         }
 489
 490         err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
 491                                 VSC73XX_ICPU_CHIPID, &t);
 492         if (err) {
 493                 dev_err(&spi->dev, "unable to read chip id, err=%d\n", err);
 494                 return err;
 495         }
 496
 497         id = (t >> 12) & 0xffff;
 498         switch (id) {
 499         case 0x7385:
 500                 break;
 501         default:
 502                 dev_err(&spi->dev, "unsupported chip, id=%04x\n", id);
 503                 return -ENODEV;
 504         }
 505
 506         rev = (t >> 28) & 0xf;
 507         dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev);
 508
 509         return 0;
 510 }
 511
 512 static int __devinit vsc7385_probe(struct spi_device *spi)
 513 {
 514         struct vsc7385 *vsc;
 515         struct vsc7385_platform_data *pdata;
 516         int     err;
 517
 518         printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n");
 519
 520         pdata = spi->dev.platform_data;
 521         if (!pdata) {
 522                 dev_err(&spi->dev, "no platform data specified\n");
 523                 return-ENODEV;
 524         }
 525
 526         vsc = kzalloc(sizeof(*vsc), GFP_KERNEL);
 527         if (!vsc) {
 528                 dev_err(&spi->dev, "no memory for private data\n");
 529                 return-ENOMEM;
 530         }
 531
 532         mutex_init(&vsc->lock);
 533         vsc->pdata = pdata;
 534         vsc->spi = spi_dev_get(spi);
 535         dev_set_drvdata(&spi->dev, vsc);
 536
 537         spi->mode = SPI_MODE_0;
 538         spi->bits_per_word = 8;
 539         err = spi_setup(spi);
 540         if (err) {
 541                 dev_err(&spi->dev, "spi_setup failed, err=%d \n", err);
 542                 goto err_drvdata;
 543         }
 544
 545         err = vsc7385_detect(vsc);
 546         if (err) {
 547                 dev_err(&spi->dev, "no chip found, err=%d \n", err);
 548                 goto err_drvdata;
 549         }
 550
 551         err = vsc7385_upload_ucode(vsc);
 552         if (err)
 553                 goto err_drvdata;
 554
 555         err = vsc7385_setup(vsc);
 556         if (err)
 557                 goto err_drvdata;
 558
 559         return 0;
 560
 561  err_drvdata:
 562         dev_set_drvdata(&spi->dev, NULL);
 563         kfree(vsc);
 564         return err;
 565 }
 566
 567 static int __devexit vsc7385_remove(struct spi_device *spi)
 568 {
 569         struct vsc7385_data     *vsc;
 570
 571         vsc = dev_get_drvdata(&spi->dev);
 572         dev_set_drvdata(&spi->dev, NULL);
 573         kfree(vsc);
 574
 575         return 0;
 576 }
 577
 578 static struct spi_driver vsc7385_driver = {
 579         .driver = {
 580                 .name           = DRV_NAME,
 581                 .bus            = &spi_bus_type,
 582                 .owner          = THIS_MODULE,
 583         },
 584         .probe          = vsc7385_probe,
 585         .remove         = __devexit_p(vsc7385_remove),
 586 };
 587
 588 static int __init vsc7385_init(void)
 589 {
 590         return spi_register_driver(&vsc7385_driver);
 591 }
 592 module_init(vsc7385_init);
 593
 594 static void __exit vsc7385_exit(void)
 595 {
 596         spi_unregister_driver(&vsc7385_driver);
 597 }
 598 module_exit(vsc7385_exit);
 599
 600 MODULE_DESCRIPTION(DRV_DESC);
 601 MODULE_VERSION(DRV_VERSION);
 602 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 603 MODULE_LICENSE("GPL v2");
 604