target/linux/atheros-2.6/patches/100-board.patch

   1 diff -urN linux.old/arch/mips/ar531x/ar531x.h linux.dev/arch/mips/ar531x/ar531x.h
   2 --- linux.old/arch/mips/ar531x/ar531x.h 1970-01-01 01:00:00.000000000 +0100
   3 +++ linux.dev/arch/mips/ar531x/ar531x.h 2006-12-16 03:51:47.000000000 +0100
   4 @@ -0,0 +1,734 @@
   5 +/*
   6 + * This file is subject to the terms and conditions of the GNU General Public
   7 + * License.  See the file "COPYING" in the main directory of this archive
   8 + * for more details.
   9 + *
  10 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
  11 + * Copyright (C) 2006 FON Technology, SL.
  12 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
  13 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  14 + */
  15 +
  16 +#ifndef AR531X_H
  17 +#define AR531X_H 1
  18 +
  19 +/*
  20 + * Address map
  21 + */
  22 +#define AR5315_SDRAM0           0x00000000      /* DRAM */
  23 +#define AR5315_SPI_READ         0x08000000      /* SPI FLASH */
  24 +#define AR5315_WLAN0            0xB0000000      /* Wireless MMR */
  25 +#define AR5315_PCI              0xB0100000      /* PCI MMR */
  26 +#define AR5315_SDRAMCTL         0xB0300000      /* SDRAM MMR */
  27 +#define AR5315_LOCAL            0xB0400000      /* LOCAL BUS MMR */
  28 +#define AR5315_ENET0            0xB0500000      /* ETHERNET MMR */
  29 +#define AR5315_DSLBASE          0xB1000000      /* RESET CONTROL MMR */
  30 +#define AR5315_UART0            0xB1100003      /* UART MMR */
  31 +#define AR5315_SPI              0xB1300000      /* SPI FLASH MMR */
  32 +#define AR5315_FLASHBT          0xBfc00000      /* ro boot alias to FLASH */
  33 +#define AR5315_RAM1             0x40000000      /* ram alias */
  34 +#define AR5315_PCIEXT           0x80000000      /* pci external */
  35 +#define AR5315_RAM2             0xc0000000      /* ram alias */
  36 +#define AR5315_RAM3             0xe0000000      /* ram alias */
  37 +
  38 +/*
  39 + * Reset Register
  40 + */
  41 +#define AR5315_COLD_RESET       (AR5315_DSLBASE + 0x0000)
  42 +
  43 +/* Cold Reset */
  44 +#define RESET_COLD_AHB              0x00000001
  45 +#define RESET_COLD_APB              0x00000002
  46 +#define RESET_COLD_CPU              0x00000004
  47 +#define RESET_COLD_CPUWARM          0x00000008
  48 +#define RESET_SYSTEM                (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB)      /* full system */
  49 +
  50 +#define AR5317_RESET_SYSTEM        0x00000010
  51 +
  52 +/* Warm Reset */
  53 +
  54 +#define AR5315_RESET            (AR5315_DSLBASE + 0x0004)
  55 +
  56 +#define RESET_WARM_WLAN0_MAC        0x00000001      /* warm reset WLAN0 MAC */
  57 +#define RESET_WARM_WLAN0_BB         0x00000002      /* warm reset WLAN0 BaseBand */
  58 +#define RESET_MPEGTS_RSVD           0x00000004      /* warm reset MPEG-TS */
  59 +#define RESET_PCIDMA                0x00000008      /* warm reset PCI ahb/dma */
  60 +#define RESET_MEMCTL                0x00000010      /* warm reset memory controller */
  61 +#define RESET_LOCAL                 0x00000020      /* warm reset local bus */
  62 +#define RESET_I2C_RSVD              0x00000040      /* warm reset I2C bus */
  63 +#define RESET_SPI                   0x00000080      /* warm reset SPI interface */
  64 +#define RESET_UART0                 0x00000100      /* warm reset UART0 */
  65 +#define RESET_IR_RSVD               0x00000200      /* warm reset IR interface */
  66 +#define RESET_EPHY0                 0x00000400      /* cold reset ENET0 phy */
  67 +#define RESET_ENET0                 0x00000800      /* cold reset ENET0 mac */
  68 +
  69 +/*
  70 + * AHB master arbitration control
  71 + */
  72 +#define AR5315_AHB_ARB_CTL      (AR5315_DSLBASE + 0x0008)
  73 +
  74 +#define ARB_CPU                     0x00000001      /* CPU, default */
  75 +#define ARB_WLAN                    0x00000002      /* WLAN */
  76 +#define ARB_MPEGTS_RSVD             0x00000004      /* MPEG-TS */
  77 +#define ARB_LOCAL                   0x00000008      /* LOCAL */
  78 +#define ARB_PCI                     0x00000010      /* PCI */
  79 +#define ARB_ETHERNET                0x00000020      /* Ethernet */
  80 +#define ARB_RETRY                   0x00000100      /* retry policy, debug only */
  81 +
  82 +/*
  83 + * Config Register
  84 + */
  85 +#define AR5315_ENDIAN_CTL       (AR5315_DSLBASE + 0x000c)
  86 +
  87 +#define CONFIG_AHB                  0x00000001      /* EC - AHB bridge endianess */
  88 +#define CONFIG_WLAN                 0x00000002      /* WLAN byteswap */
  89 +#define CONFIG_MPEGTS_RSVD          0x00000004      /* MPEG-TS byteswap */
  90 +#define CONFIG_PCI                  0x00000008      /* PCI byteswap */
  91 +#define CONFIG_MEMCTL               0x00000010      /* Memory controller endianess */
  92 +#define CONFIG_LOCAL                0x00000020      /* Local bus byteswap */
  93 +#define CONFIG_ETHERNET             0x00000040      /* Ethernet byteswap */
  94 +
  95 +#define CONFIG_MERGE                0x00000200      /* CPU write buffer merge */
  96 +#define CONFIG_CPU                  0x00000400      /* CPU big endian */
  97 +#define CONFIG_PCIAHB               0x00000800
  98 +#define CONFIG_PCIAHB_BRIDGE        0x00001000
  99 +#define CONFIG_SPI                  0x00008000      /* SPI byteswap */
 100 +#define CONFIG_CPU_DRAM             0x00010000
 101 +#define CONFIG_CPU_PCI              0x00020000
 102 +#define CONFIG_CPU_MMR              0x00040000
 103 +#define CONFIG_BIG                  0x00000400
 104 +
 105 +
 106 +/*
 107 + * NMI control
 108 + */
 109 +#define AR5315_NMI_CTL          (AR5315_DSLBASE + 0x0010)
 110 +
 111 +#define NMI_EN  1
 112 +
 113 +/*
 114 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
 115 + */
 116 +#define AR5315_SREV             (AR5315_DSLBASE + 0x0014)
 117 +
 118 +#define REV_MAJ                     0x00f0
 119 +#define REV_MAJ_S                   4
 120 +#define REV_MIN                     0x000f
 121 +#define REV_MIN_S                   0
 122 +#define REV_CHIP                    (REV_MAJ|REV_MIN)
 123 +
 124 +/*
 125 + * Interface Enable
 126 + */
 127 +#define AR5315_IF_CTL           (AR5315_DSLBASE + 0x0018)
 128 +
 129 +#define IF_MASK                     0x00000007
 130 +#define IF_DISABLED                 0
 131 +#define IF_PCI                      1
 132 +#define IF_TS_LOCAL                 2
 133 +#define IF_ALL                      3   /* only for emulation with separate pins */
 134 +#define IF_LOCAL_HOST               0x00000008
 135 +#define IF_PCI_HOST                 0x00000010
 136 +#define IF_PCI_INTR                 0x00000020
 137 +#define IF_PCI_CLK_MASK             0x00030000
 138 +#define IF_PCI_CLK_INPUT            0
 139 +#define IF_PCI_CLK_OUTPUT_LOW       1
 140 +#define IF_PCI_CLK_OUTPUT_CLK       2
 141 +#define IF_PCI_CLK_OUTPUT_HIGH      3
 142 +#define IF_PCI_CLK_SHIFT            16
 143 +
 144 +
 145 +/* Major revision numbers, bits 7..4 of Revision ID register */
 146 +#define REV_MAJ_AR5311              0x01
 147 +#define REV_MAJ_AR5312              0x04
 148 +#define REV_MAJ_AR5315              0x0B
 149 +
 150 +/*
 151 + * APB Interrupt control
 152 + */
 153 +
 154 +#define AR5315_ISR              (AR5315_DSLBASE + 0x0020)
 155 +#define AR5315_IMR              (AR5315_DSLBASE + 0x0024)
 156 +#define AR5315_GISR             (AR5315_DSLBASE + 0x0028)
 157 +
 158 +#define ISR_UART0                   0x0001           /* high speed UART */
 159 +#define ISR_I2C_RSVD                0x0002           /* I2C bus */
 160 +#define ISR_SPI                     0x0004           /* SPI bus */
 161 +#define ISR_AHB                     0x0008           /* AHB error */
 162 +#define ISR_APB                     0x0010           /* APB error */
 163 +#define ISR_TIMER                   0x0020           /* timer */
 164 +#define ISR_GPIO                    0x0040           /* GPIO */
 165 +#define ISR_WD                      0x0080           /* watchdog */
 166 +#define ISR_IR_RSVD                 0x0100           /* IR */
 167 +
 168 +#define IMR_UART0                   ISR_UART0
 169 +#define IMR_I2C_RSVD                ISR_I2C_RSVD
 170 +#define IMR_SPI                     ISR_SPI
 171 +#define IMR_AHB                     ISR_AHB
 172 +#define IMR_APB                     ISR_APB
 173 +#define IMR_TIMER                   ISR_TIMER
 174 +#define IMR_GPIO                    ISR_GPIO
 175 +#define IMR_WD                      ISR_WD
 176 +#define IMR_IR_RSVD                 ISR_IR_RSVD
 177 +
 178 +#define GISR_MISC                   0x0001
 179 +#define GISR_WLAN0                  0x0002
 180 +#define GISR_MPEGTS_RSVD            0x0004
 181 +#define GISR_LOCALPCI               0x0008
 182 +#define GISR_WMACPOLL               0x0010
 183 +#define GISR_TIMER                  0x0020
 184 +#define GISR_ETHERNET               0x0040
 185 +
 186 +/*
 187 + * Interrupt routing from IO to the processor IP bits
 188 + * Define our inter mask and level
 189 + */
 190 +#define AR5315_INTR_MISCIO      SR_IBIT3
 191 +#define AR5315_INTR_WLAN0       SR_IBIT4
 192 +#define AR5315_INTR_ENET0       SR_IBIT5
 193 +#define AR5315_INTR_LOCALPCI    SR_IBIT6
 194 +#define AR5315_INTR_WMACPOLL    SR_IBIT7
 195 +#define AR5315_INTR_COMPARE     SR_IBIT8
 196 +
 197 +/*
 198 + * Timers
 199 + */
 200 +#define AR5315_TIMER            (AR5315_DSLBASE + 0x0030)
 201 +#define AR5315_RELOAD           (AR5315_DSLBASE + 0x0034)
 202 +#define AR5315_WD               (AR5315_DSLBASE + 0x0038)
 203 +#define AR5315_WDC              (AR5315_DSLBASE + 0x003c)
 204 +
 205 +#define WDC_RESET                   0x00000002               /* reset on watchdog */
 206 +#define WDC_NMI                     0x00000001               /* NMI on watchdog */
 207 +#define WDC_IGNORE_EXPIRATION       0x00000000
 208 +
 209 +/*
 210 + * Interface Debug
 211 + */
 212 +#define AR531X_FLASHDBG             (AR531X_RESETTMR + 0x0040)
 213 +#define AR531X_MIIDBG               (AR531X_RESETTMR + 0x0044)
 214 +
 215 +
 216 +/*
 217 + * CPU Performance Counters
 218 + */
 219 +#define AR5315_PERFCNT0         (AR5315_DSLBASE + 0x0048)
 220 +#define AR5315_PERFCNT1         (AR5315_DSLBASE + 0x004c)
 221 +
 222 +#define PERF_DATAHIT                0x0001  /* Count Data Cache Hits */
 223 +#define PERF_DATAMISS               0x0002  /* Count Data Cache Misses */
 224 +#define PERF_INSTHIT                0x0004  /* Count Instruction Cache Hits */
 225 +#define PERF_INSTMISS               0x0008  /* Count Instruction Cache Misses */
 226 +#define PERF_ACTIVE                 0x0010  /* Count Active Processor Cycles */
 227 +#define PERF_WBHIT                  0x0020  /* Count CPU Write Buffer Hits */
 228 +#define PERF_WBMISS                 0x0040  /* Count CPU Write Buffer Misses */
 229 +
 230 +#define PERF_EB_ARDY                0x0001  /* Count EB_ARdy signal */
 231 +#define PERF_EB_AVALID              0x0002  /* Count EB_AValid signal */
 232 +#define PERF_EB_WDRDY               0x0004  /* Count EB_WDRdy signal */
 233 +#define PERF_EB_RDVAL               0x0008  /* Count EB_RdVal signal */
 234 +#define PERF_VRADDR                 0x0010  /* Count valid read address cycles */
 235 +#define PERF_VWADDR                 0x0020  /* Count valid write address cycles */
 236 +#define PERF_VWDATA                 0x0040  /* Count valid write data cycles */
 237 +
 238 +/*
 239 + * AHB Error Reporting.
 240 + */
 241 +#define AR5315_AHB_ERR0         (AR5315_DSLBASE + 0x0050)  /* error  */
 242 +#define AR5315_AHB_ERR1         (AR5315_DSLBASE + 0x0054)  /* haddr  */
 243 +#define AR5315_AHB_ERR2         (AR5315_DSLBASE + 0x0058)  /* hwdata */
 244 +#define AR5315_AHB_ERR3         (AR5315_DSLBASE + 0x005c)  /* hrdata */
 245 +#define AR5315_AHB_ERR4         (AR5315_DSLBASE + 0x0060)  /* status */
 246 +
 247 +#define AHB_ERROR_DET               1   /* AHB Error has been detected,          */
 248 +                                        /* write 1 to clear all bits in ERR0     */
 249 +#define AHB_ERROR_OVR               2   /* AHB Error overflow has been detected  */
 250 +#define AHB_ERROR_WDT               4   /* AHB Error due to wdt instead of hresp */
 251 +
 252 +#define PROCERR_HMAST               0x0000000f
 253 +#define PROCERR_HMAST_DFLT          0
 254 +#define PROCERR_HMAST_WMAC          1
 255 +#define PROCERR_HMAST_ENET          2
 256 +#define PROCERR_HMAST_PCIENDPT      3
 257 +#define PROCERR_HMAST_LOCAL         4
 258 +#define PROCERR_HMAST_CPU           5
 259 +#define PROCERR_HMAST_PCITGT        6
 260 +
 261 +#define PROCERR_HMAST_S             0
 262 +#define PROCERR_HWRITE              0x00000010
 263 +#define PROCERR_HSIZE               0x00000060
 264 +#define PROCERR_HSIZE_S             5
 265 +#define PROCERR_HTRANS              0x00000180
 266 +#define PROCERR_HTRANS_S            7
 267 +#define PROCERR_HBURST              0x00000e00
 268 +#define PROCERR_HBURST_S            9
 269 +
 270 +
 271 +
 272 +/*
 273 + * Clock Control
 274 + */
 275 +#define AR5315_PLLC_CTL         (AR5315_DSLBASE + 0x0064)
 276 +#define AR5315_PLLV_CTL         (AR5315_DSLBASE + 0x0068)
 277 +#define AR5315_CPUCLK           (AR5315_DSLBASE + 0x006c)
 278 +#define AR5315_AMBACLK          (AR5315_DSLBASE + 0x0070)
 279 +#define AR5315_SYNCCLK          (AR5315_DSLBASE + 0x0074)
 280 +#define AR5315_DSL_SLEEP_CTL    (AR5315_DSLBASE + 0x0080)
 281 +#define AR5315_DSL_SLEEP_DUR    (AR5315_DSLBASE + 0x0084)
 282 +
 283 +/* PLLc Control fields */
 284 +#define PLLC_REF_DIV_M              0x00000003
 285 +#define PLLC_REF_DIV_S              0
 286 +#define PLLC_FDBACK_DIV_M           0x0000007C
 287 +#define PLLC_FDBACK_DIV_S           2
 288 +#define PLLC_ADD_FDBACK_DIV_M       0x00000080
 289 +#define PLLC_ADD_FDBACK_DIV_S       7
 290 +#define PLLC_CLKC_DIV_M             0x0001c000
 291 +#define PLLC_CLKC_DIV_S             14
 292 +#define PLLC_CLKM_DIV_M             0x00700000
 293 +#define PLLC_CLKM_DIV_S             20
 294 +
 295 +/* CPU CLK Control fields */
 296 +#define CPUCLK_CLK_SEL_M            0x00000003
 297 +#define CPUCLK_CLK_SEL_S            0
 298 +#define CPUCLK_CLK_DIV_M            0x0000000c
 299 +#define CPUCLK_CLK_DIV_S            2
 300 +
 301 +/* AMBA CLK Control fields */
 302 +#define AMBACLK_CLK_SEL_M           0x00000003
 303 +#define AMBACLK_CLK_SEL_S           0
 304 +#define AMBACLK_CLK_DIV_M           0x0000000c
 305 +#define AMBACLK_CLK_DIV_S           2
 306 +
 307 +#if defined(COBRA_EMUL)
 308 +#define AR5315_AMBA_CLOCK_RATE  20000000
 309 +#define AR5315_CPU_CLOCK_RATE   40000000
 310 +#else
 311 +#if defined(DEFAULT_PLL)
 312 +#define AR5315_AMBA_CLOCK_RATE  40000000
 313 +#define AR5315_CPU_CLOCK_RATE   40000000
 314 +#else
 315 +#define AR5315_AMBA_CLOCK_RATE  92000000
 316 +#define AR5315_CPU_CLOCK_RATE   184000000
 317 +#endif /* ! DEFAULT_PLL */
 318 +#endif /* ! COBRA_EMUL */
 319 +
 320 +#define AR5315_UART_CLOCK_RATE  AR5315_AMBA_CLOCK_RATE
 321 +#define AR5315_SDRAM_CLOCK_RATE AR5315_AMBA_CLOCK_RATE
 322 +
 323 +/*
 324 + * The UART computes baud rate as:
 325 + *   baud = clock / (16 * divisor)
 326 + * where divisor is specified as a High Byte (DLM) and a Low Byte (DLL).
 327 + */
 328 +#define DESIRED_BAUD_RATE           38400
 329 +
 330 +/*
 331 + * The WATCHDOG value is computed as
 332 + *  10 seconds * AR531X_WATCHDOG_CLOCK_RATE
 333 + */
 334 +#define DESIRED_WATCHDOG_SECONDS    10
 335 +#define AR531X_WATCHDOG_TIME \
 336 +        (DESIRED_WATCHDOG_SECONDS * AR531X_WATCHDOG_CLOCK_RATE)
 337 +
 338 +
 339 +#define CLOCKCTL_UART0  0x0010  /* enable UART0 external clock */
 340 +
 341 +
 342 + /*
 343 + * Applicable "PCICFG" bits for WLAN(s).  Assoc status and LED mode.
 344 + */
 345 +#define AR531X_PCICFG               (AR531X_RESETTMR + 0x00b0)
 346 +#define ASSOC_STATUS_M              0x00000003
 347 +#define ASSOC_STATUS_NONE           0
 348 +#define ASSOC_STATUS_PENDING        1
 349 +#define ASSOC_STATUS_ASSOCIATED     2
 350 +#define LED_MODE_M                  0x0000001c
 351 +#define LED_BLINK_THRESHOLD_M       0x000000e0
 352 +#define LED_SLOW_BLINK_MODE         0x00000100
 353 +
 354 +/*
 355 + * GPIO
 356 + */
 357 +
 358 +#define AR5315_GPIO_DI          (AR5315_DSLBASE + 0x0088)
 359 +#define AR5315_GPIO_DO          (AR5315_DSLBASE + 0x0090)
 360 +#define AR5315_GPIO_CR          (AR5315_DSLBASE + 0x0098)
 361 +#define AR5315_GPIO_INT         (AR5315_DSLBASE + 0x00a0)
 362 +
 363 +#define GPIO_CR_M(x)                (1 << (x))                  /* mask for i/o */
 364 +#define GPIO_CR_O(x)                (1 << (x))                  /* output */
 365 +#define GPIO_CR_I(x)                (0 << (x))                  /* input */
 366 +
 367 +#define GPIO_INT(x,Y)               ((x) << (8 * (Y)))          /* interrupt enable */
 368 +#define GPIO_INT_M(Y)               ((0x3F) << (8 * (Y)))       /* mask for int */
 369 +#define GPIO_INT_LVL(x,Y)           ((x) << (8 * (Y) + 6))      /* interrupt level */
 370 +#define GPIO_INT_LVL_M(Y)           ((0x3) << (8 * (Y) + 6))    /* mask for int level */
 371 +
 372 +#define AR5315_RESET_GPIO       5
 373 +#define AR5315_NUM_GPIO         22
 374 +
 375 +
 376 +/*
 377 + *  PCI Clock Control
 378 + */
 379 +
 380 +#define AR5315_PCICLK           (AR5315_DSLBASE + 0x00a4)
 381 +
 382 +#define PCICLK_INPUT_M              0x3
 383 +#define PCICLK_INPUT_S              0
 384 +
 385 +#define PCICLK_PLLC_CLKM            0
 386 +#define PCICLK_PLLC_CLKM1           1
 387 +#define PCICLK_PLLC_CLKC            2
 388 +#define PCICLK_REF_CLK              3
 389 +
 390 +#define PCICLK_DIV_M                0xc
 391 +#define PCICLK_DIV_S                2
 392 +
 393 +#define PCICLK_IN_FREQ              0
 394 +#define PCICLK_IN_FREQ_DIV_6        1
 395 +#define PCICLK_IN_FREQ_DIV_8        2
 396 +#define PCICLK_IN_FREQ_DIV_10       3
 397 +
 398 +/*
 399 + * Observation Control Register
 400 + */
 401 +#define AR5315_OCR              (AR5315_DSLBASE + 0x00b0)
 402 +#define OCR_GPIO0_IRIN              0x0040
 403 +#define OCR_GPIO1_IROUT             0x0080
 404 +#define OCR_GPIO3_RXCLR             0x0200
 405 +
 406 +/*
 407 + *  General Clock Control
 408 + */
 409 +
 410 +#define AR5315_MISCCLK          (AR5315_DSLBASE + 0x00b4)
 411 +#define MISCCLK_PLLBYPASS_EN        0x00000001
 412 +#define MISCCLK_PROCREFCLK          0x00000002
 413 +
 414 +/*
 415 + * SDRAM Controller
 416 + *   - No read or write buffers are included.
 417 + */
 418 +#define AR5315_MEM_CFG          (AR5315_SDRAMCTL + 0x00)
 419 +#define AR5315_MEM_CTRL         (AR5315_SDRAMCTL + 0x0c)
 420 +#define AR5315_MEM_REF          (AR5315_SDRAMCTL + 0x10)
 421 +
 422 +#define SDRAM_DATA_WIDTH_M          0x00006000
 423 +#define SDRAM_DATA_WIDTH_S          13
 424 +
 425 +#define SDRAM_COL_WIDTH_M           0x00001E00
 426 +#define SDRAM_COL_WIDTH_S           9
 427 +
 428 +#define SDRAM_ROW_WIDTH_M           0x000001E0
 429 +#define SDRAM_ROW_WIDTH_S           5
 430 +
 431 +#define SDRAM_BANKADDR_BITS_M       0x00000018
 432 +#define SDRAM_BANKADDR_BITS_S       3
 433 +
 434 +
 435 +/*
 436 + * SDRAM Memory Refresh (MEM_REF) value is computed as:
 437 + * MEMCTL_SREFR = (Tr * hclk_freq) / R
 438 + * where Tr is max. time of refresh of any single row
 439 + * R is number of rows in the DRAM
 440 + * For most 133MHz SDRAM parts, Tr=64ms, R=4096 or 8192
 441 + */
 442 +#if defined(COBRA_EMUL)
 443 +#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x96
 444 +#else
 445 +#if defined(DEFAULT_PLL)
 446 +#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x200
 447 +#else
 448 +#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x61a
 449 +#endif /* ! DEFAULT_PLL */
 450 +#endif
 451 +
 452 +#define AR5315_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
 453 +#define AR5315_SDRAM_DATA_WIDTH     16
 454 +#define AR5315_SDRAM_COL_WIDTH      8
 455 +#define AR5315_SDRAM_ROW_WIDTH      12
 456 +
 457 +/*
 458 + * SPI Flash Interface Registers
 459 + */
 460 +
 461 +#define AR5315_SPI_CTL      (AR5315_SPI + 0x00)
 462 +#define AR5315_SPI_OPCODE   (AR5315_SPI + 0x04)
 463 +#define AR5315_SPI_DATA     (AR5315_SPI + 0x08)
 464 +
 465 +#define SPI_CTL_START           0x00000100
 466 +#define SPI_CTL_BUSY            0x00010000
 467 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 468 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 469 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 470 +#define SPI_CTL_SIZE_MASK       0x00060000
 471 +
 472 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 473 +#define SPI_OPCODE_MASK         0x000000ff
 474 +
 475 +/*
 476 + * PCI-MAC Configuration registers
 477 + */
 478 +#define PCI_MAC_RC              (AR5315_PCI + 0x4000)
 479 +#define PCI_MAC_SCR             (AR5315_PCI + 0x4004)
 480 +#define PCI_MAC_INTPEND         (AR5315_PCI + 0x4008)
 481 +#define PCI_MAC_SFR             (AR5315_PCI + 0x400C)
 482 +#define PCI_MAC_PCICFG          (AR5315_PCI + 0x4010)
 483 +#define PCI_MAC_SREV            (AR5315_PCI + 0x4020)
 484 +
 485 +#define PCI_MAC_RC_MAC          0x00000001
 486 +#define PCI_MAC_RC_BB           0x00000002
 487 +
 488 +#define PCI_MAC_SCR_SLMODE_M    0x00030000
 489 +#define PCI_MAC_SCR_SLMODE_S    16
 490 +#define PCI_MAC_SCR_SLM_FWAKE   0
 491 +#define PCI_MAC_SCR_SLM_FSLEEP  1
 492 +#define PCI_MAC_SCR_SLM_NORMAL  2
 493 +
 494 +#define PCI_MAC_SFR_SLEEP       0x00000001
 495 +
 496 +#define PCI_MAC_PCICFG_SPWR_DN  0x00010000
 497 +
 498 +
 499 +
 500 +
 501 +/*
 502 + * PCI Bus Interface Registers
 503 + */
 504 +#define AR5315_PCI_1MS_REG      (AR5315_PCI + 0x0008)
 505 +#define AR5315_PCI_1MS_MASK     0x3FFFF         /* # of AHB clk cycles in 1ms */
 506 +
 507 +#define AR5315_PCI_MISC_CONFIG  (AR5315_PCI + 0x000c)
 508 +#define AR5315_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
 509 +#define AR5315_PCIMISC_CFG_SEL  0x00000002      /* mem or config cycles */
 510 +#define AR5315_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
 511 +#define AR5315_PCIMISC_RST_MODE 0x00000030
 512 +#define AR5315_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
 513 +#define AR5315_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
 514 +#define AR5315_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
 515 +#define AR5315_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
 516 +#define AR5315_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
 517 +#define AR5315_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
 518 +#define AR5315_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
 519 +#define AR5315_PCICACHE_DIS     0x00001000      /* PCI external access cache disable */
 520 +
 521 +#define AR5315_PCI_OUT_TSTAMP   (AR5315_PCI + 0x0010)
 522 +
 523 +#define AR5315_PCI_UNCACHE_CFG  (AR5315_PCI + 0x0014)
 524 +
 525 +#define AR5315_PCI_IN_EN        (AR5315_PCI + 0x0100)
 526 +#define AR5315_PCI_IN_EN0       0x01            /* Enable chain 0 */
 527 +#define AR5315_PCI_IN_EN1       0x02            /* Enable chain 1 */
 528 +#define AR5315_PCI_IN_EN2       0x04            /* Enable chain 2 */
 529 +#define AR5315_PCI_IN_EN3       0x08            /* Enable chain 3 */
 530 +
 531 +#define AR5315_PCI_IN_DIS       (AR5315_PCI + 0x0104)
 532 +#define AR5315_PCI_IN_DIS0      0x01            /* Disable chain 0 */
 533 +#define AR5315_PCI_IN_DIS1      0x02            /* Disable chain 1 */
 534 +#define AR5315_PCI_IN_DIS2      0x04            /* Disable chain 2 */
 535 +#define AR5315_PCI_IN_DIS3      0x08            /* Disable chain 3 */
 536 +
 537 +#define AR5315_PCI_IN_PTR       (AR5315_PCI + 0x0200)
 538 +
 539 +#define AR5315_PCI_OUT_EN       (AR5315_PCI + 0x0400)
 540 +#define AR5315_PCI_OUT_EN0      0x01            /* Enable chain 0 */
 541 +
 542 +#define AR5315_PCI_OUT_DIS      (AR5315_PCI + 0x0404)
 543 +#define AR5315_PCI_OUT_DIS0     0x01            /* Disable chain 0 */
 544 +
 545 +#define AR5315_PCI_OUT_PTR      (AR5315_PCI + 0x0408)
 546 +
 547 +#define AR5315_PCI_INT_STATUS   (AR5315_PCI + 0x0500)   /* write one to clr */
 548 +#define AR5315_PCI_TXINT        0x00000001      /* Desc In Completed */
 549 +#define AR5315_PCI_TXOK         0x00000002      /* Desc In OK */
 550 +#define AR5315_PCI_TXERR        0x00000004      /* Desc In ERR */
 551 +#define AR5315_PCI_TXEOL        0x00000008      /* Desc In End-of-List */
 552 +#define AR5315_PCI_RXINT        0x00000010      /* Desc Out Completed */
 553 +#define AR5315_PCI_RXOK         0x00000020      /* Desc Out OK */
 554 +#define AR5315_PCI_RXERR        0x00000040      /* Desc Out ERR */
 555 +#define AR5315_PCI_RXEOL        0x00000080      /* Desc Out EOL */
 556 +#define AR5315_PCI_TXOOD        0x00000200      /* Desc In Out-of-Desc */
 557 +#define AR5315_PCI_MASK         0x0000FFFF      /* Desc Mask */
 558 +#define AR5315_PCI_EXT_INT      0x02000000
 559 +#define AR5315_PCI_ABORT_INT    0x04000000
 560 +
 561 +#define AR5315_PCI_INT_MASK     (AR5315_PCI + 0x0504)   /* same as INT_STATUS */
 562 +
 563 +#define AR5315_PCI_INTEN_REG    (AR5315_PCI + 0x0508)
 564 +#define AR5315_PCI_INT_DISABLE  0x00            /* disable pci interrupts */
 565 +#define AR5315_PCI_INT_ENABLE   0x01            /* enable pci interrupts */
 566 +
 567 +#define AR5315_PCI_HOST_IN_EN   (AR5315_PCI + 0x0800)
 568 +#define AR5315_PCI_HOST_IN_DIS  (AR5315_PCI + 0x0804)
 569 +#define AR5315_PCI_HOST_IN_PTR  (AR5315_PCI + 0x0810)
 570 +#define AR5315_PCI_HOST_OUT_EN  (AR5315_PCI + 0x0900)
 571 +#define AR5315_PCI_HOST_OUT_DIS (AR5315_PCI + 0x0904)
 572 +#define AR5315_PCI_HOST_OUT_PTR (AR5315_PCI + 0x0908)
 573 +
 574 +
 575 +/*
 576 + * Local Bus Interface Registers
 577 + */
 578 +#define AR5315_LB_CONFIG        (AR5315_LOCAL + 0x0000)
 579 +#define AR5315_LBCONF_OE        0x00000001      /* =1 OE is low-true */
 580 +#define AR5315_LBCONF_CS0       0x00000002      /* =1 first CS is low-true */
 581 +#define AR5315_LBCONF_CS1       0x00000004      /* =1 2nd CS is low-true */
 582 +#define AR5315_LBCONF_RDY       0x00000008      /* =1 RDY is low-true */
 583 +#define AR5315_LBCONF_WE        0x00000010      /* =1 Write En is low-true */
 584 +#define AR5315_LBCONF_WAIT      0x00000020      /* =1 WAIT is low-true */
 585 +#define AR5315_LBCONF_ADS       0x00000040      /* =1 Adr Strobe is low-true */
 586 +#define AR5315_LBCONF_MOT       0x00000080      /* =0 Intel, =1 Motorola */
 587 +#define AR5315_LBCONF_8CS       0x00000100      /* =1 8 bits CS, 0= 16bits */
 588 +#define AR5315_LBCONF_8DS       0x00000200      /* =1 8 bits Data S, 0=16bits */
 589 +#define AR5315_LBCONF_ADS_EN    0x00000400      /* =1 Enable ADS */
 590 +#define AR5315_LBCONF_ADR_OE    0x00000800      /* =1 Adr cap on OE, WE or DS */
 591 +#define AR5315_LBCONF_ADDT_MUX  0x00001000      /* =1 Adr and Data share bus */
 592 +#define AR5315_LBCONF_DATA_OE   0x00002000      /* =1 Data cap on OE, WE, DS */
 593 +#define AR5315_LBCONF_16DATA    0x00004000      /* =1 Data is 16 bits wide */
 594 +#define AR5315_LBCONF_SWAPDT    0x00008000      /* =1 Byte swap data */
 595 +#define AR5315_LBCONF_SYNC      0x00010000      /* =1 Bus synchronous to clk */
 596 +#define AR5315_LBCONF_INT       0x00020000      /* =1 Intr is low true */
 597 +#define AR5315_LBCONF_INT_CTR0  0x00000000      /* GND high-Z, Vdd is high-Z */
 598 +#define AR5315_LBCONF_INT_CTR1  0x00040000      /* GND drive, Vdd is high-Z */
 599 +#define AR5315_LBCONF_INT_CTR2  0x00080000      /* GND high-Z, Vdd drive */
 600 +#define AR5315_LBCONF_INT_CTR3  0x000C0000      /* GND drive, Vdd drive */
 601 +#define AR5315_LBCONF_RDY_WAIT  0x00100000      /* =1 RDY is negative of WAIT */
 602 +#define AR5315_LBCONF_INT_PULSE 0x00200000      /* =1 Interrupt is a pulse */
 603 +#define AR5315_LBCONF_ENABLE    0x00400000      /* =1 Falcon respond to LB */
 604 +
 605 +#define AR5315_LB_CLKSEL        (AR5315_LOCAL + 0x0004)
 606 +#define AR5315_LBCLK_EXT        0x0001          /* use external clk for lb */
 607 +
 608 +#define AR5315_LB_1MS           (AR5315_LOCAL + 0x0008)
 609 +#define AR5315_LB1MS_MASK       0x3FFFF         /* # of AHB clk cycles in 1ms */
 610 +
 611 +#define AR5315_LB_MISCCFG       (AR5315_LOCAL + 0x000C)
 612 +#define AR5315_LBM_TXD_EN       0x00000001      /* Enable TXD for fragments */
 613 +#define AR5315_LBM_RX_INTEN     0x00000002      /* Enable LB ints on RX ready */
 614 +#define AR5315_LBM_MBOXWR_INTEN 0x00000004      /* Enable LB ints on mbox wr */
 615 +#define AR5315_LBM_MBOXRD_INTEN 0x00000008      /* Enable LB ints on mbox rd */
 616 +#define AR5315_LMB_DESCSWAP_EN  0x00000010      /* Byte swap desc enable */
 617 +#define AR5315_LBM_TIMEOUT_MASK 0x00FFFF80
 618 +#define AR5315_LBM_TIMEOUT_SHFT 7
 619 +#define AR5315_LBM_PORTMUX      0x07000000
 620 +
 621 +
 622 +#define AR5315_LB_RXTSOFF       (AR5315_LOCAL + 0x0010)
 623 +
 624 +#define AR5315_LB_TX_CHAIN_EN   (AR5315_LOCAL + 0x0100)
 625 +#define AR5315_LB_TXEN_0        0x01
 626 +#define AR5315_LB_TXEN_1        0x02
 627 +#define AR5315_LB_TXEN_2        0x04
 628 +#define AR5315_LB_TXEN_3        0x08
 629 +
 630 +#define AR5315_LB_TX_CHAIN_DIS  (AR5315_LOCAL + 0x0104)
 631 +#define AR5315_LB_TX_DESC_PTR   (AR5315_LOCAL + 0x0200)
 632 +
 633 +#define AR5315_LB_RX_CHAIN_EN   (AR5315_LOCAL + 0x0400)
 634 +#define AR5315_LB_RXEN          0x01
 635 +
 636 +#define AR5315_LB_RX_CHAIN_DIS  (AR5315_LOCAL + 0x0404)
 637 +#define AR5315_LB_RX_DESC_PTR   (AR5315_LOCAL + 0x0408)
 638 +
 639 +#define AR5315_LB_INT_STATUS    (AR5315_LOCAL + 0x0500)
 640 +#define AR5315_INT_TX_DESC      0x0001
 641 +#define AR5315_INT_TX_OK        0x0002
 642 +#define AR5315_INT_TX_ERR       0x0004
 643 +#define AR5315_INT_TX_EOF       0x0008
 644 +#define AR5315_INT_RX_DESC      0x0010
 645 +#define AR5315_INT_RX_OK        0x0020
 646 +#define AR5315_INT_RX_ERR       0x0040
 647 +#define AR5315_INT_RX_EOF       0x0080
 648 +#define AR5315_INT_TX_TRUNC     0x0100
 649 +#define AR5315_INT_TX_STARVE    0x0200
 650 +#define AR5315_INT_LB_TIMEOUT   0x0400
 651 +#define AR5315_INT_LB_ERR       0x0800
 652 +#define AR5315_INT_MBOX_WR      0x1000
 653 +#define AR5315_INT_MBOX_RD      0x2000
 654 +
 655 +/* Bit definitions for INT MASK are the same as INT_STATUS */
 656 +#define AR5315_LB_INT_MASK      (AR5315_LOCAL + 0x0504)
 657 +
 658 +#define AR5315_LB_INT_EN        (AR5315_LOCAL + 0x0508)
 659 +#define AR5315_LB_MBOX          (AR5315_LOCAL + 0x0600)
 660 +
 661 +
 662 +
 663 +/*
 664 + * IR Interface Registers
 665 + */
 666 +#define AR5315_IR_PKTDATA                   (AR5315_IR + 0x0000)
 667 +
 668 +#define AR5315_IR_PKTLEN                    (AR5315_IR + 0x07fc) /* 0 - 63 */
 669 +
 670 +#define AR5315_IR_CONTROL                   (AR5315_IR + 0x0800)
 671 +#define AR5315_IRCTL_TX                     0x00000000  /* use as tranmitter */
 672 +#define AR5315_IRCTL_RX                     0x00000001  /* use as receiver   */
 673 +#define AR5315_IRCTL_SAMPLECLK_MASK         0x00003ffe  /* Sample clk divisor mask */
 674 +#define AR5315_IRCTL_SAMPLECLK_SHFT                  1
 675 +#define AR5315_IRCTL_OUTPUTCLK_MASK         0x03ffc000  /* Output clk divisor mask */
 676 +#define AR5315_IRCTL_OUTPUTCLK_SHFT                 14
 677 +
 678 +#define AR5315_IR_STATUS                    (AR5315_IR + 0x0804)
 679 +#define AR5315_IRSTS_RX                     0x00000001  /* receive in progress */
 680 +#define AR5315_IRSTS_TX                     0x00000002  /* transmit in progress */
 681 +
 682 +#define AR5315_IR_CONFIG                    (AR5315_IR + 0x0808)
 683 +#define AR5315_IRCFG_INVIN                  0x00000001  /* invert input polarity */
 684 +#define AR5315_IRCFG_INVOUT                 0x00000002  /* invert output polarity */
 685 +#define AR5315_IRCFG_SEQ_START_WIN_SEL      0x00000004  /* 1 => 28, 0 => 7 */
 686 +#define AR5315_IRCFG_SEQ_START_THRESH       0x000000f0  /*  */
 687 +#define AR5315_IRCFG_SEQ_END_UNIT_SEL       0x00000100  /*  */
 688 +#define AR5315_IRCFG_SEQ_END_UNIT_THRESH    0x00007e00  /*  */
 689 +#define AR5315_IRCFG_SEQ_END_WIN_SEL        0x00008000  /*  */
 690 +#define AR5315_IRCFG_SEQ_END_WIN_THRESH     0x001f0000  /*  */
 691 +#define AR5315_IRCFG_NUM_BACKOFF_WORDS      0x01e00000  /*  */
 692 +
 693 +/*
 694 + * PCI memory constants: Memory area 1 and 2 are the same size -
 695 + * (twice the PCI_TLB_PAGE_SIZE). The definition of
 696 + * CPU_TO_PCI_MEM_SIZE is coupled with the TLB setup routine
 697 + * sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
 698 + * PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
 699 + */
 700 +
 701 +#define CPU_TO_PCI_MEM_BASE1    0xE0000000
 702 +#define CPU_TO_PCI_MEM_SIZE1    (2*PCI_TLB_PAGE_SIZE)
 703 +
 704 +
 705 +/* TLB attributes for PCI transactions */
 706 +
 707 +#define PCI_MMU_PAGEMASK        0x00003FFF
 708 +#define MMU_PAGE_UNCACHED       0x00000010
 709 +#define MMU_PAGE_DIRTY          0x00000004
 710 +#define MMU_PAGE_VALID          0x00000002
 711 +#define MMU_PAGE_GLOBAL         0x00000001
 712 +#define PCI_MMU_PAGEATTRIB      (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
 713 +                                 MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
 714 +#define PCI_MEMORY_SPACE1_VIRT  0xE0000000      /* Used for non-prefet  mem   */
 715 +#define PCI_MEMORY_SPACE1_PHYS  0x80000000
 716 +#define PCI_TLB_PAGE_SIZE       0x01000000
 717 +#define TLB_HI_MASK             0xFFFFE000
 718 +#define TLB_LO_MASK             0x3FFFFFFF
 719 +#define PAGEMASK_SHIFT          11
 720 +#define TLB_LO_SHIFT            6
 721 +
 722 +#define PCI_MAX_LATENCY         0xFFF           /* Max PCI latency            */
 723 +
 724 +#define HOST_PCI_DEV_ID         3
 725 +#define HOST_PCI_MBAR0          0x10000000
 726 +#define HOST_PCI_MBAR1          0x20000000
 727 +#define HOST_PCI_MBAR2          0x30000000
 728 +
 729 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
 730 +#define PCI_DEVICE_MEM_SPACE    0x800000
 731 +
 732 +#define sysRegRead(phys)       \
 733 +       (*(volatile u32 *)KSEG1ADDR(phys))
 734 +
 735 +#define sysRegWrite(phys, val) \
 736 +       ((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
 737 +
 738 +#endif
 739 diff -urN linux.old/arch/mips/ar531x/ar531xlnx.h linux.dev/arch/mips/ar531x/ar531xlnx.h
 740 --- linux.old/arch/mips/ar531x/ar531xlnx.h      1970-01-01 01:00:00.000000000 +0100
 741 +++ linux.dev/arch/mips/ar531x/ar531xlnx.h      2006-12-16 04:49:36.000000000 +0100
 742 @@ -0,0 +1,74 @@
 743 +/*
 744 + * This file is subject to the terms and conditions of the GNU General Public
 745 + * License.  See the file "COPYING" in the main directory of this archive
 746 + * for more details.
 747 + *
 748 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
 749 + * Copyright (C) 2006 FON Technology, SL.
 750 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 751 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 752 + */
 753 +
 754 +/*
 755 + * This file contains definitions needed in order to compile
 756 + * AR531X products for linux.  Definitions that are largely
 757 + * AR531X-specific and independent of operating system belong
 758 + * in ar531x.h rather than this file.
 759 + */
 760 +#ifndef _AR531XLNX_H
 761 +#define _AR531XLNX_H
 762 +
 763 +#include "ar531x.h"
 764 +
 765 +/*
 766 + * Board support data.  The driver is required to locate
 767 + * and fill-in this information before passing a reference to
 768 + * this structure as the HAL_BUS_TAG parameter supplied to
 769 + * ath_hal_attach.
 770 + */
 771 +struct ar531x_config {
 772 +       const char  *board;     /* board config data */
 773 +       const char      *radio;                 /* radio config data */
 774 +       int             unit;                   /* unit number [0, 1] */
 775 +       u32             tag;                    /* used as devid for now */
 776 +};
 777 +
 778 +#define MIPS_CPU_IRQ_BASE              0x00
 779 +#define AR531X_HIGH_PRIO                0x10
 780 +#define AR531X_MISC_IRQ_BASE           0x20
 781 +#define AR531X_GPIO_IRQ_BASE            0x30
 782 +
 783 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
 784 +#define AR531X_IRQ_NONE                MIPS_CPU_IRQ_BASE+0
 785 +#define AR531X_IRQ_MISC_INTRS  MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
 786 +#define AR531X_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
 787 +#define AR531X_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
 788 +#define AR531X_IRQ_LCBUS_PCI   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
 789 +#define AR531X_IRQ_WLAN0_POLL  MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
 790 +#define AR531X_IRQ_CPU_CLOCK   MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
 791 +
 792 +/* Miscellaneous interrupts, which share IP6 */
 793 +#define AR531X_MISC_IRQ_NONE           AR531X_MISC_IRQ_BASE+0
 794 +#define AR531X_MISC_IRQ_TIMER          AR531X_MISC_IRQ_BASE+1
 795 +#define AR531X_MISC_IRQ_AHB_PROC       AR531X_MISC_IRQ_BASE+2
 796 +#define AR531X_MISC_IRQ_AHB_DMA                AR531X_MISC_IRQ_BASE+3
 797 +#define AR531X_MISC_IRQ_GPIO           AR531X_MISC_IRQ_BASE+4
 798 +#define AR531X_MISC_IRQ_UART0          AR531X_MISC_IRQ_BASE+5
 799 +#define AR531X_MISC_IRQ_UART0_DMA      AR531X_MISC_IRQ_BASE+6
 800 +#define AR531X_MISC_IRQ_WATCHDOG       AR531X_MISC_IRQ_BASE+7
 801 +#define AR531X_MISC_IRQ_LOCAL          AR531X_MISC_IRQ_BASE+8
 802 +#define AR531X_MISC_IRQ_COUNT          9
 803 +
 804 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
 805 +#define AR531X_GPIO_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
 806 +#define AR531X_GPIO_IRQ(n)              AR531X_MISC_IRQ_BASE+(n)+1
 807 +#define AR531X_GPIO_IRQ_COUNT           22
 808 +
 809 +extern struct ar531x_boarddata *ar531x_board_configuration;
 810 +extern char *ar531x_radio_configuration;
 811 +extern char *enet_mac_address_get(int MACUnit);
 812 +
 813 +#define A_DATA_CACHE_INVAL(start, length) \
 814 +        dma_cache_inv((UINT32)(start),(length))
 815 +
 816 +#endif /* _AR531XLNX_H */
 817 diff -urN linux.old/arch/mips/ar531x/devices.c linux.dev/arch/mips/ar531x/devices.c
 818 --- linux.old/arch/mips/ar531x/devices.c        1970-01-01 01:00:00.000000000 +0100
 819 +++ linux.dev/arch/mips/ar531x/devices.c        2006-12-16 04:46:43.000000000 +0100
 820 @@ -0,0 +1,281 @@
 821 +/*
 822 + * This file is subject to the terms and conditions of the GNU General Public
 823 + * License.  See the file "COPYING" in the main directory of this archive
 824 + * for more details.
 825 + *
 826 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
 827 + * Copyright (C) 2006 FON Technology, SL.
 828 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 829 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 830 + */
 831 +
 832 +/*
 833 + * Platform devices for AR531x SoC.
 834 + */
 835 +
 836 +#include <linux/autoconf.h>
 837 +#include <linux/init.h>
 838 +#include <linux/module.h>
 839 +#include <linux/types.h>
 840 +#include <linux/string.h>
 841 +#include <linux/platform_device.h>
 842 +#include <linux/kernel.h>
 843 +#include <asm/io.h>
 844 +#include <ar531x_platform.h>
 845 +
 846 +#include "ar531xlnx.h"
 847 +
 848 +static struct resource ar531x_eth_res[] = {
 849 +       {
 850 +               .name = "eth_membase",
 851 +               .flags = IORESOURCE_MEM,
 852 +               .start = 0xb0500000,
 853 +               .end = 0xb0502000,
 854 +       },
 855 +       {
 856 +               .name = "eth_irq",
 857 +               .flags = IORESOURCE_IRQ,
 858 +               .start = 4,
 859 +               .end = 4,
 860 +       },
 861 +};
 862 +
 863 +static struct ar531x_eth ar531x_eth_data = {
 864 +       .phy = 1,
 865 +       .mac = 0,
 866 +       .reset_base = 0x11000004,
 867 +       .reset_mac = 0x800,
 868 +       .reset_phy = 0x400,
 869 +};
 870 +
 871 +static struct platform_device ar531x_eth = {
 872 +       .id = 0,
 873 +       .name = "ar531x-eth",
 874 +       .dev.platform_data = &ar531x_eth_data,
 875 +       .resource = ar531x_eth_res,
 876 +       .num_resources = ARRAY_SIZE(ar531x_eth_res)
 877 +};
 878 +
 879 +static struct platform_device ar531x_wmac = {
 880 +       .id = 0,
 881 +       .name = "ar531x-wmac",
 882 +       /* FIXME: add resources */
 883 +};
 884 +
 885 +static struct resource ar531x_spiflash_res[] = {
 886 +       {
 887 +               .name = "flash_base",
 888 +               .flags = IORESOURCE_MEM,
 889 +               .start = 0xa8000000,
 890 +               .end = 0xa8400000,
 891 +       },
 892 +       {
 893 +               .name = "flash_regs",
 894 +               .flags = IORESOURCE_MEM,
 895 +               .start = 0x11300000,
 896 +               .end = 0x11300012,
 897 +       },
 898 +};
 899 +
 900 +static struct platform_device ar531x_spiflash = {
 901 +       .id = 0,
 902 +       .name = "spiflash",
 903 +       .resource = ar531x_spiflash_res,
 904 +       .num_resources = ARRAY_SIZE(ar531x_spiflash_res)
 905 +};
 906 +
 907 +static __initdata struct platform_device *ar531x_devs[] = {
 908 +       &ar531x_eth,
 909 +       &ar531x_wmac,
 910 +       &ar531x_spiflash
 911 +};
 912 +
 913 +
 914 +
 915 +static void *flash_regs;
 916 +
 917 +static inline __u32 spiflash_regread32(int reg)
 918 +{
 919 +       volatile __u32 *data = (__u32 *)(flash_regs + reg);
 920 +
 921 +       return (*data);
 922 +}
 923 +
 924 +static inline void spiflash_regwrite32(int reg, __u32 data)
 925 +{
 926 +       volatile __u32 *addr = (__u32 *)(flash_regs + reg);
 927 +
 928 +       *addr = data;
 929 +}
 930 +
 931 +#define SPI_FLASH_CTL      0x00
 932 +#define SPI_FLASH_OPCODE   0x04
 933 +#define SPI_FLASH_DATA     0x08
 934 +
 935 +static __u8 spiflash_probe(void)
 936 +{
 937 +        __u32 reg;
 938 +
 939 +       do {
 940 +               reg = spiflash_regread32(SPI_FLASH_CTL);
 941 +       } while (reg & SPI_CTL_BUSY);
 942 +
 943 +       spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
 944 +
 945 +       reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
 946 +               (1 << 4) | SPI_CTL_START;
 947 +
 948 +       spiflash_regwrite32(SPI_FLASH_CTL, reg);
 949 +
 950 +       do {
 951 +               reg = spiflash_regread32(SPI_FLASH_CTL);
 952 +       } while (reg & SPI_CTL_BUSY);
 953 +
 954 +       reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
 955 +       reg &= 0xff;
 956 +
 957 +       return (u8) reg;
 958 +}
 959 +
 960 +static u8 *find_board_config(void)
 961 +{
 962 +       char *addr;
 963 +       int found = 0;
 964 +
 965 +       for (addr = (char *) (ar531x_spiflash_res[0].end - 0x1000);
 966 +               addr >= (char *) (ar531x_spiflash_res[0].end - 0x30000);
 967 +               addr -= 0x1000) {
 968 +
 969 +               if ( *(int *)addr == 0x35333131) {
 970 +                       /* config magic found */
 971 +                       found = 1;
 972 +                       break;
 973 +               }
 974 +       }
 975 +
 976 +       if (!found) {
 977 +               printk("WARNING: No board configuration data found!\n");
 978 +               addr = NULL;
 979 +       }
 980 +
 981 +       return addr;
 982 +}
 983 +
 984 +static void *find_radio_config(char *board_config)
 985 +{
 986 +       int dataFound;
 987 +       u32 radio_config;
 988 +
 989 +       /*
 990 +        * Now find the start of Radio Configuration data, using heuristics:
 991 +        * Search forward from Board Configuration data by 0x1000 bytes
 992 +        * at a time until we find non-0xffffffff.
 993 +        */
 994 +       dataFound = 0;
 995 +       for (radio_config = (u32) board_config + 0x1000;
 996 +            (radio_config < (u32) ar531x_spiflash_res[0].end);
 997 +            radio_config += 0x1000) {
 998 +               if (*(int *)radio_config != 0xffffffff) {
 999 +                       dataFound = 1;
1000 +                       break;
1001 +               }
1002 +       }
1003 +
1004 +       if (!dataFound) { /* AR2316 relocates radio config to new location */
1005 +           for (radio_config = (u32) board_config + 0xf8;
1006 +               (radio_config < (u32) ar531x_spiflash_res[0].end - 0x1000 + 0xf8);
1007 +                        radio_config += 0x1000) {
1008 +                       if (*(int *)radio_config != 0xffffffff) {
1009 +                               dataFound = 1;
1010 +                               break;
1011 +                       }
1012 +           }
1013 +       }
1014 +
1015 +       if (!dataFound) {
1016 +               printk("Could not find Radio Configuration data\n");
1017 +               radio_config = 0;
1018 +       }
1019 +
1020 +       return (u8 *) radio_config;
1021 +}
1022 +
1023 +
1024 +#define STM_8MBIT_SIGNATURE     0x13
1025 +#define STM_16MBIT_SIGNATURE    0x14
1026 +#define STM_32MBIT_SIGNATURE    0x15
1027 +#define STM_64MBIT_SIGNATURE    0x16
1028 +
1029 +
1030 +static void __init ar531x_init_flash(void)
1031 +{
1032 +       u8 sig;
1033 +       u32 flash_size = 0;
1034 +       unsigned int rcfg_size;
1035 +       char *bcfg, *rcfg, *board_config, *radio_config;
1036 +       struct ar531x_config *config;
1037 +
1038 +       /* probe the flash chip size */
1039 +       flash_regs = ioremap_nocache(ar531x_spiflash_res[1].start, ar531x_spiflash_res[1].end - ar531x_spiflash_res[1].start);
1040 +       sig = spiflash_probe();
1041 +       iounmap(flash_regs);
1042 +
1043 +       switch(sig) {
1044 +               case STM_8MBIT_SIGNATURE:
1045 +                       flash_size = 0x00100000;
1046 +                       break;
1047 +               case STM_16MBIT_SIGNATURE:
1048 +                       flash_size = 0x00200000;
1049 +                       break;
1050 +               case STM_32MBIT_SIGNATURE:
1051 +                       flash_size = 0x00400000;
1052 +                       break;
1053 +               case STM_64MBIT_SIGNATURE:
1054 +                       flash_size = 0x00800000;
1055 +                       break;
1056 +       }
1057 +
1058 +       if (!flash_size)
1059 +               return;
1060 +
1061 +       ar531x_spiflash_res[0].end = ar531x_spiflash_res[0].start + flash_size;
1062 +
1063 +       /* Copy the board and radio data to RAM, because with the new
1064 +        * spiflash driver, accessing the mapped memory directly is no
1065 +        * longer safe */
1066 +
1067 +       bcfg = find_board_config();
1068 +       if (!bcfg)
1069 +               return;
1070 +
1071 +       board_config = kmalloc(0x1000, GFP_KERNEL);
1072 +       memcpy(board_config, bcfg, 0x100);
1073 +       ar531x_eth_data.board_config = board_config;
1074 +
1075 +       /* Radio config starts 0x100 bytes after board config, regardless
1076 +        * of what the physical layout on the flash chip looks like */
1077 +
1078 +       rcfg = find_radio_config(bcfg);
1079 +       if (!rcfg)
1080 +               return;
1081 +       printk("Radio config found at offset 0x%x\n", rcfg - bcfg);
1082 +       radio_config = board_config + 0x100 + ((rcfg - bcfg) & 0xfff);
1083 +       rcfg_size = 0x1000 - ((rcfg - bcfg) & 0xfff);
1084 +       memcpy(radio_config, rcfg, rcfg_size);
1085 +
1086 +       config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
1087 +       config->board = board_config;
1088 +       config->radio = radio_config;
1089 +       config->unit = 0;
1090 +       config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & REV_CHIP);
1091 +       ar531x_wmac.dev.platform_data = config;
1092 +}
1093 +
1094 +static int __init ar531x_register_devices(void)
1095 +{
1096 +       ar531x_init_flash();
1097 +       return platform_add_devices(ar531x_devs, ARRAY_SIZE(ar531x_devs));
1098 +}
1099 +
1100 +
1101 +arch_initcall(ar531x_register_devices);
1102 diff -urN linux.old/arch/mips/ar531x/gpio.c linux.dev/arch/mips/ar531x/gpio.c
1103 --- linux.old/arch/mips/ar531x/gpio.c   1970-01-01 01:00:00.000000000 +0100
1104 +++ linux.dev/arch/mips/ar531x/gpio.c   2006-12-16 04:49:20.000000000 +0100
1105 @@ -0,0 +1,127 @@
1106 +/*
1107 + * This file is subject to the terms and conditions of the GNU General Public
1108 + * License.  See the file "COPYING" in the main directory of this archive
1109 + * for more details.
1110 + *
1111 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
1112 + * Copyright (C) 2006 FON Technology, SL.
1113 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1114 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1115 + */
1116 +
1117 +/*
1118 + * Support for GPIO -- General Purpose Input/Output Pins
1119 + * XXX: should be rewritten
1120 + */
1121 +
1122 +#include <linux/autoconf.h>
1123 +#include <linux/kernel.h>
1124 +#include <linux/signal.h>
1125 +#include <linux/interrupt.h>
1126 +#include <linux/irq.h>
1127 +
1128 +#include "ar531xlnx.h"
1129 +
1130 +/* GPIO Interrupt Support */
1131 +
1132 +/* Turn on the specified AR531X_GPIO_IRQ interrupt */
1133 +static unsigned int
1134 +ar531x_gpio_intr_startup(unsigned int irq)
1135 +{
1136 +       ar531x_gpio_intr_enable(irq);
1137 +
1138 +       return 0;
1139 +}
1140 +
1141 +/* Turn off the specified AR531X_GPIO_IRQ interrupt */
1142 +static void
1143 +ar531x_gpio_intr_shutdown(unsigned int irq)
1144 +{
1145 +       ar531x_gpio_intr_disable(irq);
1146 +}
1147 +
1148 +u32 gpioIntMask = 0;
1149 +
1150 +static void ar531x_gpio_intr_set_enabled(unsigned int gpio, int enabled)
1151 +{
1152 +       u32 reg;
1153 +       int intnum = 0;
1154 +       int intlevel = 2;
1155 +
1156 +       reg = sysRegRead(AR5315_GPIO_CR);
1157 +       reg &= ~(GPIO_CR_M(gpio));
1158 +       reg |= GPIO_CR_I(gpio);
1159 +       sysRegWrite(AR5315_GPIO_CR, reg);
1160 +       (void)sysRegRead(AR5315_GPIO_CR); /* flush write to hardware */
1161 +
1162 +       reg = sysRegRead(AR5315_GPIO_INT);
1163 +
1164 +       reg &= ~(GPIO_INT_M(intnum));
1165 +       reg &= ~(GPIO_INT_LVL_M(intnum));
1166 +
1167 +       if (enabled) {
1168 +               reg |= GPIO_INT_LVL(intlevel, intnum);
1169 +               reg |= GPIO_INT(gpio, intnum);
1170 +       }
1171 +
1172 +       sysRegWrite(AR5315_GPIO_INT, reg);
1173 +       (void)sysRegRead(AR5315_GPIO_INT); /* flush write to hardware */
1174 +}
1175 +
1176 +
1177 +/* Enable the specified AR531X_GPIO_IRQ interrupt */
1178 +static void
1179 +ar531x_gpio_intr_enable(unsigned int irq)
1180 +{
1181 +       int gpio = irq - AR531X_GPIO_IRQ_BASE;
1182 +
1183 +       gpioIntMask |= (1<<gpio);
1184 +       ar531x_gpio_intr_set_enabled(irq, 1);
1185 +}
1186 +
1187 +/* Disable the specified AR531X_GPIO_IRQ interrupt */
1188 +static void
1189 +ar531x_gpio_intr_disable(unsigned int irq)
1190 +{
1191 +       int gpio = irq - AR531X_GPIO_IRQ_BASE;
1192 +
1193 +       gpioIntMask &= (1<<gpio);
1194 +       ar531x_gpio_intr_set_enabled(irq, 0);
1195 +}
1196 +
1197 +
1198 +static void
1199 +ar531x_gpio_intr_end(unsigned int irq)
1200 +{
1201 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1202 +               ar531x_gpio_intr_enable(irq);
1203 +}
1204 +
1205 +int ar531x_gpio_irq_base;
1206 +
1207 +struct hw_interrupt_type ar531x_gpio_intr_controller = {
1208 +       .typename = "AR531X GPIO",
1209 +       .startup = ar531x_gpio_intr_startup,
1210 +       .shutdown = ar531x_gpio_intr_shutdown,
1211 +       .enable = ar531x_gpio_intr_enable,
1212 +       .disable = ar531x_gpio_intr_disable,
1213 +       .ack = ar531x_gpio_intr_disable,
1214 +       .end = ar531x_gpio_intr_end,
1215 +};
1216 +
1217 +void
1218 +ar531x_gpio_intr_init(int irq_base)
1219 +{
1220 +       int i;
1221 +
1222 +       for (i = irq_base; i < irq_base + AR531X_GPIO_IRQ_COUNT; i++) {
1223 +               irq_desc[i].status = IRQ_DISABLED;
1224 +               irq_desc[i].action = NULL;
1225 +               irq_desc[i].depth = 1;
1226 +               irq_desc[i].chip = &ar531x_gpio_intr_controller;
1227 +       }
1228 +
1229 +       ar531x_gpio_irq_base = irq_base;
1230 +}
1231 +
1232 +
1233 diff -urN linux.old/arch/mips/ar531x/irq.c linux.dev/arch/mips/ar531x/irq.c
1234 --- linux.old/arch/mips/ar531x/irq.c    1970-01-01 01:00:00.000000000 +0100
1235 +++ linux.dev/arch/mips/ar531x/irq.c    2006-12-17 15:09:04.000000000 +0100
1236 @@ -0,0 +1,312 @@
1237 +/*
1238 + * This file is subject to the terms and conditions of the GNU General Public
1239 + * License.  See the file "COPYING" in the main directory of this archive
1240 + * for more details.
1241 + *
1242 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
1243 + * Copyright (C) 2006 FON Technology, SL.
1244 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1245 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1246 + */
1247 +
1248 +/*
1249 + * Interrupt support for AR531X WiSOC.
1250 + */
1251 +
1252 +#include <linux/autoconf.h>
1253 +#include <linux/init.h>
1254 +#include <linux/kernel_stat.h>
1255 +#include <linux/signal.h>
1256 +#include <linux/sched.h>
1257 +#include <linux/interrupt.h>
1258 +#include <linux/slab.h>
1259 +#include <linux/random.h>
1260 +#include <linux/pm.h>
1261 +#include <linux/delay.h>
1262 +#include <linux/reboot.h>
1263 +
1264 +#include <asm/irq.h>
1265 +#include <asm/mipsregs.h>
1266 +#include <asm/gdb-stub.h>
1267 +
1268 +#include "ar531xlnx.h"
1269 +#include <asm/irq_cpu.h>
1270 +
1271 +extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
1272 +
1273 +static void ar531x_misc_intr_enable(unsigned int irq);
1274 +static void ar531x_misc_intr_disable(unsigned int irq);
1275 +
1276 +
1277 +/* Turn on the specified AR531X_MISC_IRQ interrupt */
1278 +static unsigned int
1279 +ar531x_misc_intr_startup(unsigned int irq)
1280 +{
1281 +       ar531x_misc_intr_enable(irq);
1282 +       return 0;
1283 +}
1284 +
1285 +/* Turn off the specified AR531X_MISC_IRQ interrupt */
1286 +static void
1287 +ar531x_misc_intr_shutdown(unsigned int irq)
1288 +{
1289 +       ar531x_misc_intr_disable(irq);
1290 +}
1291 +
1292 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1293 +static void
1294 +ar531x_misc_intr_enable(unsigned int irq)
1295 +{
1296 +       unsigned int imr;
1297 +
1298 +       imr = sysRegRead(AR5315_IMR);
1299 +       switch(irq)
1300 +       {
1301 +          case AR531X_MISC_IRQ_TIMER:
1302 +            imr |= IMR_TIMER;
1303 +            break;
1304 +
1305 +          case AR531X_MISC_IRQ_AHB_PROC:
1306 +            imr |= IMR_AHB;
1307 +            break;
1308 +
1309 +          case AR531X_MISC_IRQ_AHB_DMA:
1310 +            imr |= 0/* ?? */;
1311 +            break;
1312 +
1313 +          case AR531X_MISC_IRQ_GPIO:
1314 +            imr |= IMR_GPIO;
1315 +            break;
1316 +
1317 +          case AR531X_MISC_IRQ_UART0:
1318 +            imr |= IMR_UART0;
1319 +            break;
1320 +
1321 +
1322 +          case AR531X_MISC_IRQ_WATCHDOG:
1323 +            imr |= IMR_WD;
1324 +            break;
1325 +
1326 +          case AR531X_MISC_IRQ_LOCAL:
1327 +            imr |= 0/* ?? */;
1328 +            break;
1329 +
1330 +       }
1331 +       sysRegWrite(AR5315_IMR, imr);
1332 +       imr=sysRegRead(AR5315_IMR); /* flush write buffer */
1333 +       //printk("enable Interrupt irq 0x%x imr 0x%x \n",irq,imr);
1334 +
1335 +}
1336 +
1337 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1338 +static void
1339 +ar531x_misc_intr_disable(unsigned int irq)
1340 +{
1341 +       unsigned int imr;
1342 +
1343 +       imr = sysRegRead(AR5315_IMR);
1344 +       switch(irq)
1345 +       {
1346 +          case AR531X_MISC_IRQ_TIMER:
1347 +            imr &= (~IMR_TIMER);
1348 +            break;
1349 +
1350 +          case AR531X_MISC_IRQ_AHB_PROC:
1351 +            imr &= (~IMR_AHB);
1352 +            break;
1353 +
1354 +          case AR531X_MISC_IRQ_AHB_DMA:
1355 +            imr &= 0/* ?? */;
1356 +            break;
1357 +
1358 +          case AR531X_MISC_IRQ_GPIO:
1359 +            imr &= ~IMR_GPIO;
1360 +            break;
1361 +
1362 +          case AR531X_MISC_IRQ_UART0:
1363 +            imr &= (~IMR_UART0);
1364 +            break;
1365 +
1366 +          case AR531X_MISC_IRQ_WATCHDOG:
1367 +            imr &= (~IMR_WD);
1368 +            break;
1369 +
1370 +          case AR531X_MISC_IRQ_LOCAL:
1371 +            imr &= ~0/* ?? */;
1372 +            break;
1373 +
1374 +       }
1375 +       sysRegWrite(AR5315_IMR, imr);
1376 +       sysRegRead(AR5315_IMR); /* flush write buffer */
1377 +}
1378 +
1379 +static void
1380 +ar531x_misc_intr_ack(unsigned int irq)
1381 +{
1382 +       ar531x_misc_intr_disable(irq);
1383 +}
1384 +
1385 +static void
1386 +ar531x_misc_intr_end(unsigned int irq)
1387 +{
1388 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1389 +               ar531x_misc_intr_enable(irq);
1390 +}
1391 +
1392 +struct irq_chip ar531x_misc_intr_controller = {
1393 +       .typename       = "AR531X MISC",
1394 +       .startup        = ar531x_misc_intr_startup,
1395 +       .shutdown       = ar531x_misc_intr_shutdown,
1396 +       .enable         = ar531x_misc_intr_enable,
1397 +       .disable        = ar531x_misc_intr_disable,
1398 +       .ack            = ar531x_misc_intr_ack,
1399 +       .end            = ar531x_misc_intr_end,
1400 +};
1401 +
1402 +/*
1403 + * Determine interrupt source among interrupts that use IP6
1404 + */
1405 +void
1406 +ar531x_misc_intr_init(int irq_base)
1407 +{
1408 +       int i;
1409 +
1410 +       for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
1411 +               irq_desc[i].status = IRQ_DISABLED;
1412 +               irq_desc[i].action = NULL;
1413 +               irq_desc[i].depth = 1;
1414 +               irq_desc[i].chip = &ar531x_misc_intr_controller;
1415 +       }
1416 +}
1417 +
1418 +/* ARGSUSED */
1419 +irqreturn_t
1420 +spurious_irq_handler(int cpl, void *dev_id)
1421 +{
1422 +    /*
1423 +    printk("spurious_irq_handler: %d  cause=0x%8.8x  status=0x%8.8x\n",
1424 +          cpl, cause_intrs, status_intrs);
1425 +    */
1426 +       return IRQ_NONE;
1427 +}
1428 +
1429 +/* ARGSUSED */
1430 +irqreturn_t
1431 +spurious_misc_handler(int cpl, void *dev_id)
1432 +{
1433 +    /*
1434 +    printk("spurious_misc_handler: 0x%x isr=0x%8.8x imr=0x%8.8x\n",
1435 +          cpl, ar531x_isr, ar531x_imr);
1436 +    */
1437 +       return IRQ_NONE;
1438 +}
1439 +
1440 +irqreturn_t
1441 +ar531x_ahb_proc_handler(int cpl, void *dev_id)
1442 +{
1443 +    u32 procAddr = -1;
1444 +    u32 proc1 = -1;
1445 +    u32 dmaAddr = -1;
1446 +    u32 dma1 = -1;
1447 +    sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
1448 +    sysRegRead(AR5315_AHB_ERR1);
1449 +
1450 +    printk("AHB interrupt: PROCADDR=0x%8.8x  PROC1=0x%8.8x  DMAADDR=0x%8.8x  DMA1=0x%8.8x\n",
1451 +       procAddr, proc1, dmaAddr, dma1);
1452 +
1453 +    machine_restart("AHB error"); /* Catastrophic failure */
1454 +    return IRQ_HANDLED;
1455 +}
1456 +
1457 +static struct irqaction cascade  = {
1458 +       .handler        = no_action,
1459 +       .flags          = SA_INTERRUPT,
1460 +       .name           = "cascade",
1461 +};
1462 +
1463 +static struct irqaction spurious_irq  = {
1464 +       .handler        = spurious_irq_handler,
1465 +       .flags          = SA_INTERRUPT,
1466 +       .name           = "spurious_irq",
1467 +};
1468 +
1469 +static struct irqaction spurious_misc  = {
1470 +       .handler        = spurious_misc_handler,
1471 +       .flags          = SA_INTERRUPT,
1472 +       .name           = "spurious_misc",
1473 +};
1474 +
1475 +static struct irqaction ar531x_ahb_proc_interrupt  = {
1476 +       .handler        = ar531x_ahb_proc_handler,
1477 +       .flags          = SA_INTERRUPT,
1478 +       .name           = "ar531x_ahb_proc_interrupt",
1479 +};
1480 +
1481 +/*
1482 + * Called when an interrupt is received, this function
1483 + * determines exactly which interrupt it was, and it
1484 + * invokes the appropriate handler.
1485 + *
1486 + * Implicitly, we also define interrupt priority by
1487 + * choosing which to dispatch first.
1488 + */
1489 +asmlinkage void plat_irq_dispatch(void)
1490 +{
1491 +       int pending = read_c0_status() & read_c0_cause();
1492 +
1493 +       if (pending & CAUSEF_IP3)
1494 +               do_IRQ(AR531X_IRQ_WLAN0_INTRS);
1495 +       else if (pending & CAUSEF_IP4)
1496 +               do_IRQ(AR531X_IRQ_ENET0_INTRS);
1497 +       else if (pending & CAUSEF_IP2) {
1498 +               unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
1499 +
1500 +           if (ar531x_misc_intrs & ISR_TIMER)
1501 +                       do_IRQ(AR531X_MISC_IRQ_TIMER);
1502 +               else if (ar531x_misc_intrs & ISR_AHB)
1503 +                       do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1504 +               else if (ar531x_misc_intrs & ISR_GPIO) {
1505 +#if 0
1506 +                       int i;
1507 +                       u32 gpioIntPending;
1508 +
1509 +                       gpioIntPending = sysRegRead(AR5315_GPIO_DI) & gpioIntMask;
1510 +                       for (i=0; i<AR531X_GPIO_IRQ_COUNT; i++) {
1511 +                               if (gpioIntPending & (1 << i))
1512 +                                       do_IRQ(AR531X_GPIO_IRQ_BASE+i);
1513 +                       }
1514 +#endif
1515 +                       sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~ISR_GPIO);
1516 +               } else if (ar531x_misc_intrs & ISR_UART0)
1517 +                       do_IRQ(AR531X_MISC_IRQ_UART0);
1518 +               else if (ar531x_misc_intrs & ISR_WD)
1519 +                       do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1520 +               else
1521 +                       do_IRQ(AR531X_MISC_IRQ_NONE);
1522 +       } else if (pending & CAUSEF_IP7)
1523 +               do_IRQ(AR531X_IRQ_CPU_CLOCK);
1524 +       else
1525 +               do_IRQ(AR531X_IRQ_NONE);
1526 +}
1527 +
1528 +void __init arch_init_irq(void)
1529 +{
1530 +       clear_c0_status(ST0_IM);
1531 +       mips_cpu_irq_init(0);
1532 +
1533 +       /* Initialize interrupt controllers */
1534 +       ar531x_misc_intr_init(AR531X_MISC_IRQ_BASE);
1535 +#if 0
1536 +       ar531x_gpio_intr_init(AR531X_GPIO_IRQ_BASE);
1537 +#endif
1538 +       setup_irq(AR531X_IRQ_MISC_INTRS, &cascade);
1539 +       /*
1540 +        * AR531X_IRQ_CPU_CLOCK is setup by ar531x_timer_setup.
1541 +        */
1542 +
1543 +       /* Default "spurious interrupt" handlers */
1544 +       setup_irq(AR531X_IRQ_NONE, &spurious_irq);
1545 +       setup_irq(AR531X_MISC_IRQ_NONE, &spurious_misc);
1546 +       setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar531x_ahb_proc_interrupt);
1547 +       setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
1548 +}
1549 diff -urN linux.old/arch/mips/ar531x/Makefile linux.dev/arch/mips/ar531x/Makefile
1550 --- linux.old/arch/mips/ar531x/Makefile 1970-01-01 01:00:00.000000000 +0100
1551 +++ linux.dev/arch/mips/ar531x/Makefile 2006-12-16 03:51:47.000000000 +0100
1552 @@ -0,0 +1,18 @@
1553 +#
1554 +# This file is subject to the terms and conditions of the GNU General Public
1555 +# License.  See the file "COPYING" in the main directory of this archive
1556 +# for more details.
1557 +#
1558 +# Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
1559 +# Copyright (C) 2006 FON Technology, SL.
1560 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1561 +# Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1562 +#
1563 +
1564 +# Makefile for Atheros ar531x boards
1565 +#
1566 +# Note! Dependencies are done automagically by 'make dep', which also
1567 +# removes any old dependencies. DON'T put your own dependencies here
1568 +# unless it's something special (ie not a .c file).
1569 +#
1570 +obj-y := setup.o prom.o irq.o devices.o
1571 diff -urN linux.old/arch/mips/ar531x/prom.c linux.dev/arch/mips/ar531x/prom.c
1572 --- linux.old/arch/mips/ar531x/prom.c   1970-01-01 01:00:00.000000000 +0100
1573 +++ linux.dev/arch/mips/ar531x/prom.c   2006-12-16 04:50:30.000000000 +0100
1574 @@ -0,0 +1,50 @@
1575 +/*
1576 + * This file is subject to the terms and conditions of the GNU General Public
1577 + * License.  See the file "COPYING" in the main directory of this archive
1578 + * for more details.
1579 + *
1580 + * Copyright MontaVista Software Inc
1581 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
1582 + * Copyright (C) 2006 FON Technology, SL.
1583 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1584 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1585 + */
1586 +
1587 +/*
1588 + * Prom setup file for ar531x
1589 + */
1590 +
1591 +#include <linux/init.h>
1592 +#include <linux/autoconf.h>
1593 +#include <linux/kernel.h>
1594 +#include <linux/string.h>
1595 +#include <linux/mm.h>
1596 +#include <linux/bootmem.h>
1597 +
1598 +#include <asm/bootinfo.h>
1599 +#include <asm/addrspace.h>
1600 +
1601 +#include "ar531xlnx.h"
1602 +
1603 +void __init prom_init(void)
1604 +{
1605 +       u32 memsize, memcfg;
1606 +
1607 +    mips_machgroup = MACH_GROUP_AR531X;
1608 +    mips_machtype = MACH_ATHEROS_AP51;
1609 +
1610 +       memcfg = sysRegRead(AR5315_MEM_CFG);
1611 +       memsize   = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
1612 +       memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
1613 +       memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
1614 +       memsize <<= 3;
1615 +    add_memory_region(0, memsize, BOOT_MEM_RAM);
1616 +
1617 +    strcpy(arcs_cmdline, "console=ttyS0,9600 rootfstype=squashfs,jffs2");
1618 +}
1619 +
1620 +void __init prom_free_prom_memory(void)
1621 +{
1622 +}
1623 +
1624 +
1625 diff -urN linux.old/arch/mips/ar531x/setup.c linux.dev/arch/mips/ar531x/setup.c
1626 --- linux.old/arch/mips/ar531x/setup.c  1970-01-01 01:00:00.000000000 +0100
1627 +++ linux.dev/arch/mips/ar531x/setup.c  2006-12-16 03:51:47.000000000 +0100
1628 @@ -0,0 +1,198 @@
1629 +/*
1630 + * This file is subject to the terms and conditions of the GNU General Public
1631 + * License.  See the file "COPYING" in the main directory of this archive
1632 + * for more details.
1633 + *
1634 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
1635 + * Copyright (C) 2006 FON Technology, SL.
1636 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1637 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1638 + */
1639 +
1640 +/*
1641 + * Initialization for ar531x SOC.
1642 + */
1643 +
1644 +#include <linux/autoconf.h>
1645 +#include <linux/init.h>
1646 +#include <linux/module.h>
1647 +#include <linux/delay.h>
1648 +#include <linux/irq.h>
1649 +#include <linux/interrupt.h>
1650 +#include <linux/pm.h>
1651 +#include <linux/serial.h>
1652 +#include <linux/serial_core.h>
1653 +#include <linux/types.h>
1654 +#include <linux/string.h>
1655 +
1656 +#include <asm/reboot.h>
1657 +#include <asm/io.h>
1658 +#include <asm/time.h>
1659 +#include <asm/pgtable.h>
1660 +#include <asm/processor.h>
1661 +#include <asm/reboot.h>
1662 +#include <asm/system.h>
1663 +#include <asm/serial.h>
1664 +
1665 +#include "ar531xlnx.h"
1666 +
1667 +void
1668 +ar531x_restart(char *command)
1669 +{
1670 +        for(;;) {
1671 +                /*
1672 +                ** Cold reset does not work,work around is to use the GPIO reset bit.
1673 +                */
1674 +                unsigned int reg;
1675 +
1676 +                /* AR2317 reset */
1677 +                sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
1678 +
1679 +                reg = sysRegRead(AR5315_GPIO_DO);
1680 +                reg &= ~(1 << AR5315_RESET_GPIO);
1681 +                sysRegWrite(AR5315_GPIO_DO, reg);
1682 +                (void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
1683 +        }
1684 +}
1685 +
1686 +void
1687 +ar531x_halt(void)
1688 +{
1689 +        printk(KERN_NOTICE "\n** You can safely turn off the power\n");
1690 +        while (1);
1691 +}
1692 +
1693 +void
1694 +ar531x_power_off(void)
1695 +{
1696 +        ar531x_halt();
1697 +}
1698 +
1699 +char *get_system_type(void)
1700 +{
1701 +       return "Atheros AR5315";
1702 +}
1703 +
1704 +/*
1705 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1706 + * to determine the predevisor value.
1707 + */
1708 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
1709 +    1,
1710 +    2,
1711 +    4,
1712 +    5
1713 +};
1714 +
1715 +static int __initdata PLLC_DIVIDE_TABLE[5] = {
1716 +    2,
1717 +    3,
1718 +    4,
1719 +    6,
1720 +    3
1721 +};
1722 +
1723 +static unsigned int __init
1724 +ar531x_sys_clk(unsigned int clockCtl)
1725 +{
1726 +    unsigned int pllcCtrl,cpuDiv;
1727 +    unsigned int pllcOut,refdiv,fdiv,divby2;
1728 +       unsigned int clkDiv;
1729 +
1730 +    pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
1731 +    refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
1732 +    refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
1733 +    fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
1734 +    divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
1735 +    divby2 += 1;
1736 +    pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
1737 +
1738 +
1739 +    /* clkm input selected */
1740 +       switch(clockCtl & CPUCLK_CLK_SEL_M) {
1741 +               case 0:
1742 +               case 1:
1743 +                       clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
1744 +                       break;
1745 +               case 2:
1746 +                       clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
1747 +                       break;
1748 +               default:
1749 +                       pllcOut = 40000000;
1750 +                       clkDiv = 1;
1751 +                       break;
1752 +       }
1753 +       cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
1754 +       cpuDiv = cpuDiv * 2 ?: 1;
1755 +       return (pllcOut/(clkDiv * cpuDiv));
1756 +}
1757 +
1758 +static inline unsigned int ar531x_cpu_frequency(void)
1759 +{
1760 +    return ar531x_sys_clk(sysRegRead(AR5315_CPUCLK));
1761 +}
1762 +
1763 +static inline unsigned int ar531x_apb_frequency(void)
1764 +{
1765 +    return ar531x_sys_clk(sysRegRead(AR5315_AMBACLK));
1766 +}
1767 +
1768 +
1769 +void __init serial_setup(void)
1770 +{
1771 +       struct uart_port s;
1772 +
1773 +       memset(&s, 0, sizeof(s));
1774 +
1775 +       s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
1776 +       s.iotype = UPIO_MEM;
1777 +       s.uartclk = AR5315_UART_CLOCK_RATE;
1778 +       s.irq = AR531X_MISC_IRQ_UART0;
1779 +       s.regshift = 2;
1780 +       s.mapbase = KSEG1ADDR(AR5315_UART0);
1781 +       s.membase = (void __iomem *)s.mapbase;
1782 +
1783 +       early_serial_setup(&s);
1784 +}
1785 +
1786 +void __init plat_timer_setup(struct irqaction *irq)
1787 +{
1788 +       unsigned int count;
1789 +
1790 +       /* Usually irq is timer_irqaction (timer_interrupt) */
1791 +       setup_irq(AR531X_IRQ_CPU_CLOCK, irq);
1792 +
1793 +       /* to generate the first CPU timer interrupt */
1794 +       count = read_c0_count();
1795 +       write_c0_compare(count + 1000);
1796 +}
1797 +
1798 +static void __init
1799 +ar531x_time_init(void)
1800 +{
1801 +       mips_hpt_frequency = ar531x_cpu_frequency() / 2;
1802 +}
1803 +
1804 +void __init plat_mem_setup(void)
1805 +{
1806 +       unsigned int config = read_c0_config();
1807 +
1808 +       /* Clear any lingering AHB errors */
1809 +       write_c0_config(config & ~0x3);
1810 +       sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
1811 +       sysRegRead(AR5315_AHB_ERR1);
1812 +       sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
1813 +
1814 +       /* Disable data watchpoints */
1815 +       write_c0_watchlo0(0);
1816 +
1817 +       board_time_init = ar531x_time_init;
1818 +
1819 +       _machine_restart = ar531x_restart;
1820 +       _machine_halt = ar531x_halt;
1821 +       pm_power_off = ar531x_power_off;
1822 +
1823 +       serial_setup();
1824 +}
1825 +
1826 +EXPORT_SYMBOL(get_system_type);
1827 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
1828 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
1829 +++ linux.dev/arch/mips/Kconfig 2006-12-16 03:51:47.000000000 +0100
1830 @@ -145,6 +145,19 @@
1831           note that a kernel built with this option selected will not be
1832           able to run on normal units.
1833
1834 +config AR531X
1835 +       bool 'Atheros AR531x/AR231x WiSoC (EXPERIMENTAL)'
1836 +       depends on EXPERIMENTAL
1837 +       select DMA_NONCOHERENT
1838 +       select IRQ_CPU
1839 +       select SYS_HAS_CPU_MIPS32_R1
1840 +       select HAVE_STD_PC_SERIAL_PORT
1841 +       select AR531X_COBRA
1842 +       select AR5315
1843 +       select AP51
1844 +       select SYS_SUPPORTS_BIG_ENDIAN
1845 +       select SYS_SUPPORTS_32BIT_KERNEL
1846 +
1847  config MIPS_COBALT
1848         bool "Cobalt Server"
1849         select DMA_NONCOHERENT
1850 @@ -864,6 +877,18 @@
1851  config MIPS_DISABLE_OBSOLETE_IDE
1852         bool
1853
1854 +config AR531X_COBRA
1855 +       bool
1856 +
1857 +config AR5315
1858 +       bool
1859 +
1860 +config AR5317
1861 +       bool
1862 +
1863 +config AP51
1864 +       bool
1865 +
1866  #
1867  # Endianess selection.  Suffiently obscure so many users don't know what to
1868  # answer,so we try hard to limit the available choices.  Also the use of a
1869 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
1870 --- linux.old/arch/mips/Makefile        2006-12-14 23:53:29.000000000 +0100
1871 +++ linux.dev/arch/mips/Makefile        2006-12-16 04:45:48.000000000 +0100
1872 @@ -267,6 +267,13 @@
1873  load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000
1874
1875  #
1876 +# Atheros AR5312/AR2312 WiSoC
1877 +#
1878 +core-$(CONFIG_AR531X)     += arch/mips/ar531x/
1879 +cflags-$(CONFIG_AR531X)   += -Iinclude/asm-mips/mach-atheros
1880 +load-$(CONFIG_AR531X)     += 0xffffffff80041000
1881 +
1882 +#
1883  # Cobalt Server
1884  #
1885  core-$(CONFIG_MIPS_COBALT)     += arch/mips/cobalt/
1886 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1887 --- linux.old/include/asm-mips/bootinfo.h       2006-11-29 22:57:37.000000000 +0100
1888 +++ linux.dev/include/asm-mips/bootinfo.h       2006-12-16 03:51:47.000000000 +0100
1889 @@ -212,6 +212,19 @@
1890  #define MACH_GROUP_NEC_EMMA2RH 25      /* NEC EMMA2RH (was 23)         */
1891  #define  MACH_NEC_MARKEINS     0       /* NEC EMMA2RH Mark-eins        */
1892
1893 +/*
1894 + * Valid machtype for group AR531X
1895 + */
1896 +#define MACH_GROUP_AR531X      23
1897 +#define MACH_ATHEROS_UNUSED     0
1898 +#define MACH_ATHEROS_AP30       1       /* AP30 */
1899 +#define MACH_ATHEROS_AP33       2       /* AP33 */
1900 +#define MACH_ATHEROS_AP38       3       /* AP38 */
1901 +#define MACH_ATHEROS_AP43       4       /* AP43 */
1902 +#define MACH_ATHEROS_AP48       5       /* AP48 */
1903 +#define MACH_ATHEROS_PB32       6       /* PB32 */
1904 +#define MACH_ATHEROS_AP51       7       /* AP51 */
1905 +
1906  #define CL_SIZE                        COMMAND_LINE_SIZE
1907
1908  const char *get_system_type(void);
1909 diff -urN linux.old/include/asm-mips/mach-atheros/ar531x_platform.h linux.dev/include/asm-mips/mach-atheros/ar531x_platform.h
1910 --- linux.old/include/asm-mips/mach-atheros/ar531x_platform.h   1970-01-01 01:00:00.000000000 +0100
1911 +++ linux.dev/include/asm-mips/mach-atheros/ar531x_platform.h   2006-12-16 04:27:21.000000000 +0100
1912 @@ -0,0 +1,14 @@
1913 +#ifndef __AR531X_PLATFORM_H
1914 +#define __AR531X_PLATFORM_H
1915 +
1916 +struct ar531x_eth {
1917 +       int phy;
1918 +       int mac;
1919 +       u32 reset_base;
1920 +       u32 reset_mac;
1921 +       u32 reset_phy;
1922 +       char *board_config;
1923 +};
1924 +
1925 +#endif /* __AR531X_PLATFORM_H */
1926 +