target/linux/ppc40x/patches/004-acadia_cuboot.patch

   1 diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
   2 index 6403275..5f4a59c 100644
   3 --- a/arch/powerpc/boot/Makefile
   4 +++ b/arch/powerpc/boot/Makefile
   5 @@ -68,7 +68,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
   6                 fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
   7                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
   8                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
   9 -               virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c
  10 +               virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
  11 +               cuboot-acadia.c
  12  src-boot := $(src-wlib) $(src-plat) empty.c
  13
  14  src-boot := $(addprefix $(obj)/, $(src-boot))
  15 @@ -211,6 +212,7 @@ image-$(CONFIG_DEFAULT_UIMAGE)              += uImage
  16  # Board ports in arch/powerpc/platform/40x/Kconfig
  17  image-$(CONFIG_EP405)                  += dtbImage.ep405
  18  image-$(CONFIG_WALNUT)                 += treeImage.walnut
  19 +image-$(CONFIG_ACADIA)                 += cuImage.acadia
  20
  21  # Board ports in arch/powerpc/platform/44x/Kconfig
  22  image-$(CONFIG_EBONY)                  += treeImage.ebony cuImage.ebony
  23 diff --git a/arch/powerpc/boot/cuboot-acadia.c b/arch/powerpc/boot/cuboot-acadia.c
  24 new file mode 100644
  25 index 0000000..0634aba
  26 --- /dev/null
  27 +++ b/arch/powerpc/boot/cuboot-acadia.c
  28 @@ -0,0 +1,174 @@
  29 +/*
  30 + * Old U-boot compatibility for Acadia
  31 + *
  32 + * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
  33 + *
  34 + * Copyright 2008 IBM Corporation
  35 + *
  36 + * This program is free software; you can redistribute it and/or modify it
  37 + * under the terms of the GNU General Public License version 2 as published
  38 + * by the Free Software Foundation.
  39 + */
  40 +
  41 +#include "ops.h"
  42 +#include "io.h"
  43 +#include "dcr.h"
  44 +#include "stdio.h"
  45 +#include "4xx.h"
  46 +#include "44x.h"
  47 +#include "cuboot.h"
  48 +
  49 +#define TARGET_4xx
  50 +#include "ppcboot.h"
  51 +
  52 +static bd_t bd;
  53 +
  54 +#define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
  55 +
  56 +#define PLLC_SRC_MASK         0x20000000     /* PLL feedback source */
  57 +
  58 +#define PLLD_FBDV_MASK        0x1F000000     /* PLL feedback divider value */
  59 +#define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
  60 +#define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
  61 +
  62 +#define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
  63 +#define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
  64 +#define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
  65 +#define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
  66 +
  67 +#define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
  68 +#define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
  69 +#define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
  70 +#define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
  71 +
  72 +static void get_clocks(void)
  73 +{
  74 +       unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
  75 +       unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
  76 +       unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
  77 +       unsigned long div;              /* total divisor udiv * bdiv */
  78 +       unsigned long umin;             /* minimum udiv */
  79 +       unsigned short diff;            /* smallest diff */
  80 +       unsigned long udiv;             /* best udiv */
  81 +       unsigned short idiff;           /* current diff */
  82 +       unsigned short ibdiv;           /* current bdiv */
  83 +       unsigned long est;              /* current estimate */
  84 +       unsigned long baud;
  85 +       void *np;
  86 +
  87 +       /* read the sysclk value from the CPLD */
  88 +       sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
  89 +
  90 +       /*
  91 +        * Read PLL Mode registers
  92 +        */
  93 +       cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
  94 +       cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
  95 +
  96 +       /*
  97 +        * Determine forward divider A
  98 +        */
  99 +       pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
 100 +
 101 +       /*
 102 +        * Determine forward divider B
 103 +        */
 104 +       pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
 105 +       if (pllFwdDivB == 0)
 106 +               pllFwdDivB = 8;
 107 +
 108 +       /*
 109 +        * Determine FBK_DIV.
 110 +        */
 111 +       pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
 112 +       if (pllFbkDiv == 0)
 113 +               pllFbkDiv = 256;
 114 +
 115 +       /*
 116 +        * Read CPR_PRIMAD register
 117 +        */
 118 +       cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
 119 +
 120 +       /*
 121 +        * Determine PLB_DIV.
 122 +        */
 123 +       pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
 124 +       if (pllPlbDiv == 0)
 125 +               pllPlbDiv = 16;
 126 +
 127 +       /*
 128 +        * Determine EXTBUS_DIV.
 129 +        */
 130 +       pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
 131 +       if (pllExtBusDiv == 0)
 132 +               pllExtBusDiv = 16;
 133 +
 134 +       /*
 135 +        * Determine OPB_DIV.
 136 +        */
 137 +       pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
 138 +       if (pllOpbDiv == 0)
 139 +               pllOpbDiv = 16;
 140 +
 141 +       /* There is a bug in U-Boot that prevents us from using
 142 +        * bd.bi_opbfreq because U-Boot doesn't populate it for
 143 +        * 405EZ.  We get to calculate it, yay!
 144 +        */
 145 +       freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
 146 +
 147 +       freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
 148 +
 149 +       plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
 150 +                                          pllFwdDivB : pllFwdDiv) *
 151 +                   pllFbkDiv) / pllFwdDivB);
 152 +
 153 +       np = find_node_by_alias("serial0");
 154 +       if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
 155 +               fatal("no current-speed property\n\r");
 156 +
 157 +       udiv = 256;                     /* Assume lowest possible serial clk */
 158 +       div = plloutb / (16 * baud); /* total divisor */
 159 +       umin = (plloutb / freqOPB) << 1;        /* 2 x OPB divisor */
 160 +       diff = 256;                     /* highest possible */
 161 +
 162 +       /* i is the test udiv value -- start with the largest
 163 +        * possible (256) to minimize serial clock and constrain
 164 +        * search to umin.
 165 +        */
 166 +       for (i = 256; i > umin; i--) {
 167 +               ibdiv = div / i;
 168 +               est = i * ibdiv;
 169 +               idiff = (est > div) ? (est-div) : (div-est);
 170 +               if (idiff == 0) {
 171 +                       udiv = i;
 172 +                       break;      /* can't do better */
 173 +               } else if (idiff < diff) {
 174 +                       udiv = i;       /* best so far */
 175 +                       diff = idiff;   /* update lowest diff*/
 176 +               }
 177 +       }
 178 +       freqUART = plloutb / udiv;
 179 +
 180 +       dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
 181 +       dt_fixup_clock("/plb/ebc", freqEBC);
 182 +       dt_fixup_clock("/plb/opb", freqOPB);
 183 +       dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
 184 +       dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
 185 +}
 186 +
 187 +static void acadia_fixups(void)
 188 +{
 189 +       dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
 190 +       get_clocks();
 191 +       dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
 192 +}
 193 +
 194 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 195 +               unsigned long r6, unsigned long r7)
 196 +{
 197 +       CUBOOT_INIT();
 198 +       platform_ops.fixups = acadia_fixups;
 199 +       platform_ops.exit = ibm40x_dbcr_reset;
 200 +       fdt_init(_dtb_start);
 201 +       serial_console_init();
 202 +}