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ar71xx: add WMAC initialization code for the AR933X SoCs
[openwrt.git]
/
target
/
linux
/
ar71xx
/
files
/
arch
/
mips
/
include
/
asm
/
mach-ar71xx
/
ar71xx.h
diff --git
a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index
759c8e6
..
7c99dba
100644
(file)
--- a/
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@
-72,6
+72,8
@@
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
@@
-455,6
+457,8
@@
static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
#define AR91XX_GPIO_COUNT 22
#define AR91XX_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+
#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
@@
-504,6
+508,11
@@
void ar71xx_gpio_function_setup(u32 set, u32 clear);
#define AR91XX_DDR_REG_FLUSH_USB 0x84
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
#define AR91XX_DDR_REG_FLUSH_USB 0x84
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+
#define AR934X_DDR_REG_FLUSH_GE0 0x9c
#define AR934X_DDR_REG_FLUSH_GE1 0xa0
#define AR934X_DDR_REG_FLUSH_USB 0xa4
#define AR934X_DDR_REG_FLUSH_GE0 0x9c
#define AR934X_DDR_REG_FLUSH_GE1 0xa0
#define AR934X_DDR_REG_FLUSH_USB 0xa4
@@
-597,6
+606,7
@@
void ar71xx_ddr_flush(u32 reg);
#define AR724X_RESET_REG_RESET_MODULE 0x1c
#define AR724X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
@@
-661,6
+671,11
@@
void ar71xx_ddr_flush(u32 reg);
#define AR724X_RESET_USB_PHY BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
#define AR724X_RESET_USB_PHY BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_GE0_MAC BIT(9)
+
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
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