diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
---- linux.old/arch/mips/Kconfig 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/arch/mips/Kconfig 2006-06-18 17:18:16.000000000 +0200
-@@ -742,6 +742,19 @@
+--- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
++++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
+@@ -728,6 +728,19 @@
select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS
config TOSHIBA_RBTX4927
bool "Toshiba TBTX49[23]7 board"
select DMA_NONCOHERENT
-@@ -1028,7 +1041,7 @@
+@@ -1015,7 +1028,7 @@
config MIPS_L1_CACHE_SHIFT
int
default "5"
diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
---- linux.old/arch/mips/Makefile 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/arch/mips/Makefile 2006-06-18 17:18:16.000000000 +0200
-@@ -580,6 +580,13 @@
+--- linux.old/arch/mips/Makefile 2006-12-14 03:13:55.000000000 +0100
++++ linux.dev/arch/mips/Makefile 2006-12-14 04:09:50.000000000 +0100
+@@ -586,6 +586,13 @@
load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
#
# Toshiba RBTX4927 board or
# Toshiba RBTX4937 board
#
-diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
---- linux.old/arch/mips/mm/tlbex.c 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/arch/mips/mm/tlbex.c 2006-06-18 17:18:16.000000000 +0200
-@@ -876,7 +876,6 @@
- case CPU_R10000:
- case CPU_R12000:
- case CPU_R14000:
-- case CPU_4KC:
- case CPU_SB1:
- case CPU_SB1A:
- case CPU_4KSC:
-@@ -904,6 +903,7 @@
- tlbw(p);
- break;
-
-+ case CPU_4KC:
- case CPU_4KEC:
- case CPU_24K:
- case CPU_34K:
diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
--- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-06-18 17:18:16.000000000 +0200
++++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-12-14 04:09:50.000000000 +0100
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+}
+
diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
---- linux.old/arch/mips/pci/Makefile 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/arch/mips/pci/Makefile 2006-06-18 17:18:16.000000000 +0200
-@@ -57,3 +57,4 @@
- obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
+--- linux.old/arch/mips/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
++++ linux.dev/arch/mips/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
+@@ -53,3 +53,4 @@
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
+ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
+obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
--- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,195 @@
++++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,218 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * pci_ops for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
++ * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ **************************************************************************
+ */
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+ int where, u32 * val)
+{
+ int ret;
-+
++ int delay = 1;
++
++ if (bus->number == 0 && PCI_SLOT(devfn) > 21)
++ return 0;
++
++retry:
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
++
++ /* PCI scan: check for invalid values, device may not have
++ * finished initializing */
++
++ if (where == PCI_VENDOR_ID) {
++ if (ret == 0xffffffff || ret == 0x00000000 ||
++ ret == 0x0000ffff || ret == 0xffff0000) {
++
++ if (delay > 4)
++ return 0;
++
++ delay *= 2;
++ msleep(delay);
++ goto retry;
++ }
++ }
++
+ return ret;
+}
+
+};
diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
--- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-06-18 17:18:16.000000000 +0200
++++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-12-14 04:09:50.000000000 +0100
@@ -0,0 +1,234 @@
+/**************************************************************************
+ *
+ **************************************************************************
+ */
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+
diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
--- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/devices.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,211 @@
++++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,210 @@
++/*
++ * RouterBoard 500 Platform devices
++ *
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * $Id$
++ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+ .num_resources = ARRAY_SIZE(cf_slot0_res),
+};
+
++/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
++static struct resource nand_slot0_res[] = {
++ {
++ .name = "nand_membase",
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct platform_device nand_slot0 = {
++ .id = 0,
++ .name = "rb500-nand",
++ .resource = nand_slot0_res,
++ .num_resources = ARRAY_SIZE(nand_slot0_res),
++};
+
+
+static struct platform_device *rb500_devs[] = {
+ &korina_dev0,
++ &nand_slot0,
+ &cf_slot0
+};
+
+
+/* DEVICE CONTROLLER 1 */
+#define CFG_DC_DEV1 (void*)0xb8010010
++#define CFG_DC_DEV2 (void*)0xb8010020
+#define CFG_DC_DEVBASE 0x0
+#define CFG_DC_DEVMASK 0x4
+#define CFG_DC_DEVC 0x8
+ cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
+ cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
+ }
++
++ /* There is always a NAND device */
++ nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
++ nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
+
+ return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
+}
+arch_initcall(plat_setup_devices);
+
+
-+#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
-+extern void block2mtd_setup(char *initstr);
-+extern void mount_devfs_fs(void);
-+
-+static int __init setup_mtd(void)
-+{
-+ struct hd_struct **part;
-+ int num = 0, i;
-+ char initstr[64];
-+
-+ if (cf_slot0_data.gd == NULL)
-+ return 0;
-+
-+ /* count partitions */
-+ part = cf_slot0_data.gd->part;
-+ while (part[num] != NULL) {
-+ num++;
-+ }
-+
-+ if (num < 2)
-+ return 0;
-+
-+ mount_devfs_fs();
-+ printk("Setting up block2mtd devices\n");
-+
-+ block2mtd_setup("/dev/cf/card0/part1,131072,kernel");
-+ block2mtd_setup("/dev/cf/card0/part2,131072,rootfs");
-+
-+ for (i = 2; part[i]; i++) {
-+ sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1);
-+ block2mtd_setup(initstr);
-+ }
-+
-+ return 0;
-+}
-+
-+late_initcall(setup_mtd);
-+#endif
-diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
---- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/early_serial.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,199 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * EB434 specific polling driver for 16550 UART.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * Copyright (C) 2000 by Lineo, Inc.
-+ * Written by Quinn Jensen (jensenq@lineo.com)
-+ **************************************************************************
-+ * P. Sadik Oct 20, 2003
-+ *
-+ * DIVISOR is made a function of idt_cpu_freq
-+ **************************************************************************
-+ * P. Sadik Oct 30, 2003
-+ *
-+ * added reset_cons_port
-+ **************************************************************************
-+ */
-+
-+#include <linux/serial_reg.h>
-+
-+/* turn this on to watch the debug protocol echoed on the console port */
-+#define DEBUG_REMOTE_DEBUG
-+
-+#define CONS_BAUD 115200
-+
-+extern unsigned int idt_cpu_freq;
-+
-+#define EXT_FREQ 24000000
-+#define INT_FREQ idt_cpu_freq
-+
-+#define EXT_PORT 0xb9800000u
-+#define EXT_SHIFT 0
-+
-+#ifdef __MIPSEB__
-+#define INT_PORT 0xb8058003u
-+#else
-+#define INT_PORT 0xb8058000u
-+#endif
-+#define INT_SHIFT 2
-+
-+#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
-+#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
-+
-+typedef struct
-+{
-+ volatile unsigned char *base;
-+ unsigned int shift;
-+ unsigned int freq;
-+ unsigned int fcr;
-+} ser_port;
-+
-+ser_port ports[2] =
-+{
-+ { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
-+ { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
-+};
-+
-+#define CONS_PORT 0
-+
-+void cons_putc(char c);
-+int port_getc(int port);
-+void port_putc(int port, char c);
-+
-+int cons_getc(void)
-+{
-+ return port_getc(CONS_PORT);
-+}
-+
-+void cons_putc(char c)
-+{
-+ port_putc(CONS_PORT, c);
-+}
-+
-+void cons_puts(char *s)
-+{
-+ while(*s) {
-+ if(*s == '\n') cons_putc('\r');
-+ cons_putc(*s);
-+ s++;
-+ }
-+}
-+
-+void cons_do_putn(int n)
-+{
-+ if(n) {
-+ cons_do_putn(n / 10);
-+ cons_putc(n % 10 + '0');
-+ }
-+}
-+
-+void cons_putn(int n)
-+{
-+ if(n < 0) {
-+ cons_putc('-');
-+ n = -n;
-+ }
-+
-+ if (n == 0) {
-+ cons_putc('0');
-+ } else {
-+ cons_do_putn(n);
-+ }
-+}
-+
-+int port_getc(int p)
-+{
-+ volatile unsigned char *port = ports[p].base;
-+ int s = ports[p].shift;
-+ int c;
-+
-+ while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
-+ continue;
-+ }
-+
-+ c = *(port + (UART_RX << s));
-+
-+ return c;
-+}
-+
-+int port_getc_ready(int p)
-+{
-+ volatile unsigned char *port = ports[p].base;
-+ int s = ports[p].shift;
-+
-+ return *(port + (UART_LSR << s)) & UART_LSR_DR;
-+}
-+
-+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
-+
-+void port_putc(int p, char c)
-+{
-+ volatile unsigned char *port = ports[p].base;
-+ int s = ports[p].shift;
-+ volatile unsigned char *lsr = port + (UART_LSR << s);
-+
-+ while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
-+ continue;
-+ }
-+
-+ *(port + (UART_TX << s)) = c;
-+}
-+
-+void reset_cons_port(void)
-+{
-+ volatile unsigned char *port = ports[CONS_PORT].base;
-+ unsigned int s = ports[CONS_PORT].shift;
-+ unsigned int DIVISOR;
-+
-+ if (ports[CONS_PORT].freq)
-+ DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
-+ else
-+ DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
-+
-+ /* reset the port */
-+ *(port + (UART_CSR << s)) = 0;
-+
-+ /* clear and enable the FIFOs */
-+ *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
-+
-+ /* set the baud rate */
-+ *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
-+
-+ *(port + (UART_DLL << s)) = DIVISOR;
-+ *(port + (UART_DLM << s)) = DIVISOR >> 8;
-+ /* set the line control stuff and disable DLL, DLM regs */
-+
-+ *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
-+ UART_LCR_WLEN8; /* 8 bit word length */
-+
-+ /* leave interrupts off */
-+ *(port + (UART_IER << s)) = 0;
-+
-+ /* the modem controls don't leave the chip on this port, so leave them alone */
-+ *(port + (UART_MCR << s)) = 0;
-+}
diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
--- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/irq.c 2006-06-18 17:31:37.000000000 +0200
++++ linux.dev/arch/mips/rb500/irq.c 2006-12-14 04:14:16.000000000 +0100
@@ -0,0 +1,264 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
-+ irq_desc[i].handler = &rc32434_irq_type;
++ irq_desc[i].chip = &rc32434_irq_type;
+ spin_lock_init(&irq_desc[i].lock);
+ }
+}
+
+/* Main Interrupt dispatcher */
-+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
++asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int ip, pend, group;
+ volatile unsigned int *addr;
+ unsigned int cp0_cause = read_c0_cause() & read_c0_status();
+
+ if (cp0_cause & CAUSEF_IP7) {
-+ ll_timer_interrupt(7, regs);
++ ll_timer_interrupt(7);
+ } else if ((ip = (cp0_cause & 0x7c00))) {
+ group = 21 - rc32434_clz(ip);
+
+ pend = READ_PEND(addr);
+ pend &= ~READ_MASK(addr); // only unmasked interrupts
+ pend = 39 - rc32434_clz(pend);
-+ do_IRQ((group << 5) + pend, regs);
++ do_IRQ((group << 5) + pend);
+ }
+}
diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
--- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/Makefile 2006-06-18 17:36:48.000000000 +0200
++++ linux.dev/arch/mips/rb500/Makefile 2006-12-14 04:09:50.000000000 +0100
@@ -0,0 +1,5 @@
+#
+# Makefile for the RB500 board specific parts of the kernel
+#
+
-+obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
++obj-y += irq.o time.o setup.o serial.o prom.o misc.o devices.o
diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
--- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/misc.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,54 @@
++++ linux.dev/arch/mips/rb500/misc.c 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,56 @@
+#include <linux/module.h>
+#include <linux/kernel.h> /* printk() */
+#include <linux/types.h> /* size_t */
+#define GPIO_BADDR 0xb8050000
+
+
-+static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030);
++static volatile unsigned char *devCtl3Base = 0;
+static unsigned char latchU5State = 0;
+static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
+
+ unsigned flags;
+ spin_lock_irqsave(&clu5Lock, flags);
+ latchU5State = (latchU5State | orMask) & ~nandMask;
++ if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
++ KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
+ *devCtl3Base = latchU5State;
+ spin_unlock_irqrestore(&clu5Lock, flags);
+}
+EXPORT_SYMBOL(changeLatchU5);
diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
--- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/prom.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,181 @@
++++ linux.dev/arch/mips/rb500/prom.c 2006-12-14 05:15:05.000000000 +0100
+@@ -0,0 +1,161 @@
+/*
+* prom.c
+**********************************************************************
+
+*/
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
+extern void __init setup_serial_port(void);
-+extern void cons_putc(char c);
-+extern void cons_puts(char *s);
+
+unsigned int idt_cpu_freq = 132000000;
+EXPORT_SYMBOL(idt_cpu_freq);
+
+void __init prom_setup_cmdline(void);
+
-+#ifdef DEBUG_DDR
-+void cons_puthex4(u32 h){
-+ h&=0x0f;
-+ if (h>=10)
-+ cons_putc((h-10)+'a');
-+ else
-+ cons_putc(h+'0');
-+}
-+
-+void cons_putreg32(u32 reg){
-+ char c;
-+ cons_putc('0');
-+ cons_putc('x');
-+ for (c=28;c>=0;c-=4)
-+ cons_puthex4(reg>>c);
-+}
-+#endif
-+
+void __init prom_init(void)
+{
+ DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
+
diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
--- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/serial.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,79 @@
++++ linux.dev/arch/mips/rb500/serial.c 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,77 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ */
+
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+{
+ serial_req.uartclk = idt_cpu_freq;
+
-+ if (early_serial_setup(&serial_req)){
-+ cons_puts("Serial setup failed!\n");
++ if (early_serial_setup(&serial_req))
+ return -ENODEV;
-+ }
+
+ return(0);
+}
diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
--- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/setup.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,84 @@
++++ linux.dev/arch/mips/rb500/setup.c 2006-12-14 04:51:12.000000000 +0100
+@@ -0,0 +1,81 @@
+/*
+ * setup.c - boot time setup code
+ */
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
-+#include <asm/bootinfo.h>
-+#include <asm/io.h>
+#include <linux/ioport.h>
++#include <linux/pm.h>
++#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h> /* for KSEG1ADDR() */
++#include <asm/time.h>
++#include <asm/io.h>
+#include <asm/rc32434/rc32434.h>
-+#include <linux/pm.h>
+#include <asm/rc32434/pci.h>
+
-+extern void (*board_time_init)(void);
-+extern void (*board_timer_setup)(struct irqaction *irq);
-+extern void rc32434_time_init(void);
-+extern void rc32434_timer_setup(struct irqaction *irq);
+#ifdef CONFIG_PCI
++extern void *rc32434_time_init(void);
+extern int __init rc32434_pcibridge_init(void);
+#endif
+
+}
+#endif
+
-+void __init plat_setup(void)
++void __init plat_mem_setup(void)
+{
+ unsigned int pciCntlVal;
+
+ board_time_init = rc32434_time_init;
-+ board_timer_setup = rc32434_timer_setup;
+
+#ifdef CONFIG_CPU_HAS_WB
+ __wbflush = rb_write_buffer_flush;
+}
diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
--- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/rb500/time.c 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,94 @@
++++ linux.dev/arch/mips/rb500/time.c 2006-12-14 04:48:33.000000000 +0100
+@@ -0,0 +1,93 @@
+/*
+****************************************************************************
+* Carsten Langgaard, carstenl@mips.com
+****************************************************************************
+*/
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+static unsigned long r4k_cur; /* What counter should be at next timer irq */
-+extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
+extern unsigned int mips_hpt_frequency;
+extern unsigned int idt_cpu_freq;
+
+ local_irq_restore(flags);
+}
+
-+void __init rc32434_timer_setup(struct irqaction *irq)
++void __init plat_timer_setup(struct irqaction *irq)
+{
+ /* we are using the cpu counter for timer interrupts */
+ setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+ write_c0_compare(r4k_cur);
+}
+
-diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
---- linux.old/drivers/mtd/devices/block2mtd.c 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-06-18 17:18:16.000000000 +0200
-@@ -26,7 +26,6 @@
- #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
- #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
-
--
- /* Info for the block device */
- struct block2mtd_dev {
- struct list_head list;
-@@ -62,10 +61,8 @@
- read_lock_irq(&mapping->tree_lock);
- for (i = 0; i < PAGE_READAHEAD; i++) {
- pagei = index + i;
-- if (pagei > end_index) {
-- INFO("Overrun end of disk in cache readahead\n");
-+ if (pagei > end_index)
- break;
-- }
- page = radix_tree_lookup(&mapping->page_tree, pagei);
- if (page && (!i))
- break;
-@@ -106,7 +103,7 @@
-
- while (pages) {
- page = page_readahead(mapping, index);
-- if (!page)
-+ if (!page || !page_address(page))
- return -ENOMEM;
- if (IS_ERR(page))
- return PTR_ERR(page);
-@@ -285,7 +282,7 @@
-
-
- /* FIXME: ensure that mtd->size % erase_size == 0 */
--static struct block2mtd_dev *add_device(char *devname, int erase_size)
-+static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
- {
- struct block_device *bdev;
- struct block2mtd_dev *dev;
-@@ -315,14 +312,15 @@
-
- /* Setup the MTD structure */
- /* make the name contain the block device in */
-- dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
-+ dev->mtd.name = kmalloc(strlen((alias ?: devname)),
- GFP_KERNEL);
- if (!dev->mtd.name)
- goto devinit_err;
-
-- sprintf(dev->mtd.name, "block2mtd: %s", devname);
-+ strcpy(dev->mtd.name, (alias ?: devname));
-
- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
-+ dev->mtd.size -= dev->mtd.size % erase_size;
- dev->mtd.erasesize = erase_size;
- dev->mtd.type = MTD_RAM;
- dev->mtd.flags = MTD_CAP_RAM;
-@@ -341,7 +339,7 @@
- }
- list_add(&dev->list, &blkmtd_device_list);
- INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
-- dev->mtd.name + strlen("blkmtd: "),
-+ dev->mtd.name,
- dev->mtd.erasesize >> 10, dev->mtd.erasesize);
- return dev;
-
-@@ -416,7 +414,7 @@
- return 0; \
- } while (0)
-
--static int block2mtd_setup(const char *val, struct kernel_param *kp)
-+int block2mtd_setup(const char *val, struct kernel_param *kp)
- {
- char buf[80+12], *str=buf; /* 80 for device, 12 for erase size */
- char *token[2];
-@@ -430,7 +428,7 @@
- strcpy(str, val);
- kill_final_newline(str);
-
-- for (i=0; i<2; i++)
-+ for (i=0; i<3; i++)
- token[i] = strsep(&str, ",");
-
- if (str)
-@@ -453,7 +451,7 @@
- parse_err("illegal erase size");
- }
-
-- add_device(name, erase_size);
-+ add_device(name, erase_size, token[2]);
-
- return 0;
- }
-@@ -461,6 +459,7 @@
-
- module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
- MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
-+EXPORT_SYMBOL(block2mtd_setup);
-
- static int __init block2mtd_init(void)
- {
diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
---- linux.old/drivers/pci/Makefile 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/drivers/pci/Makefile 2006-06-18 17:18:16.000000000 +0200
-@@ -27,6 +27,7 @@
- obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
- obj-$(CONFIG_X86_VISWS) += setup-irq.o
+--- linux.old/drivers/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
++++ linux.dev/drivers/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
+@@ -16,6 +16,7 @@
+
+ # Build the PCI MSI interrupt support
obj-$(CONFIG_PCI_MSI) += msi.o
+obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
- #
- # ACPI Related PCI FW Functions
+ # Build the Hypertransport interrupt support
+ obj-$(CONFIG_HT_IRQ) += htirq.o
diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
---- linux.old/include/asm-mips/bootinfo.h 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/include/asm-mips/bootinfo.h 2006-06-18 17:18:16.000000000 +0200
-@@ -218,6 +218,8 @@
- #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
- #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
+--- linux.old/include/asm-mips/bootinfo.h 2006-11-29 22:57:37.000000000 +0100
++++ linux.dev/include/asm-mips/bootinfo.h 2006-12-14 04:09:50.000000000 +0100
+@@ -212,6 +212,8 @@
+ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
+ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
+#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
+
const char *get_system_type(void);
diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
---- linux.old/include/asm-mips/cpu.h 2006-06-18 17:31:54.000000000 +0200
-+++ linux.dev/include/asm-mips/cpu.h 2006-06-18 17:18:16.000000000 +0200
+--- linux.old/include/asm-mips/cpu.h 2006-11-29 22:57:37.000000000 +0100
++++ linux.dev/include/asm-mips/cpu.h 2006-12-14 04:09:50.000000000 +0100
@@ -200,7 +200,8 @@
#define CPU_SB1A 62
#define CPU_74K 63
/*
* ISA Level encodings
-diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
---- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/crom.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,98 @@
-+#ifndef __IDT_CROM_H__
-+#define __IDT_CROM_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Configuration ROM register definitions.
-+ *
-+ * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020118
-+ * Update :
-+ * $Log: crom.h,v $
-+ * Revision 1.2 2002/06/06 18:34:03 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:21 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ CROM0_PhysicalAddress = 0x100b8000,
-+ CROM_PhysicalAddress = CROM0_PhysicalAddress,
-+
-+ CROM0_VirtualAddress = 0xb00b8000,
-+ CROM_VirtualAddress = CROM0_VirtualAddress,
-+} ;
-+
-+typedef struct CROM_s
-+{
-+ U32 cromw0 ; // use CROMW0_
-+ U32 cromw1 ; // use CROMW1_
-+ U32 cromw2 ; // use CROMW2_
-+} volatile * CROM_t ;
-+
-+enum
-+{
-+ CROMW0_xloc_b = 0,
-+ CROMW0_xloc_m = 0x0000003f,
-+ CROMW0_yloc_b = 8,
-+ CROMW0_yloc_m = 0x00003f00,
-+ CROMW0_speed_b = 16,
-+ CROMW0_speed_m = 0x01ff0000,
-+ CROMW1_wafer_b = 0,
-+ CROMW1_wafer_m = 0x0000001f,
-+ CROMW1_lot_b = 8,
-+ CROMW1_lot_m = 0x0fffff00,
-+ CROMW1_fab_b = 28,
-+ CROMW1_fab_m = 0xf0000000,
-+ CROMW2_pci_b = 0,
-+ CROMW2_pci_m = 0x00000001,
-+ CROMW2_eth0_b = 1,
-+ CROMW2_eth0_m = 0x00000002,
-+ CROMW2_eth1_b = 2,
-+ CROMW2_eth1_m = 0x00000004
-+ CROMW2_i2c_b = 3,
-+ CROMW2_i2c_m = 0x00000008,
-+ CROMW2_rng_b = 4,
-+ CROMW2_rng_m = 0x00000010,
-+ CROMW2_se_b = 5,
-+ CROMW2_se_m = 0x00000020,
-+ CROMW2_des_b = 6,
-+ CROMW2_des_m = 0x00000040,
-+ CROMW2_tdes_b = 7,
-+ CROMW2_tdes_m = 0x00000080,
-+ CROMW2_a128_b = 8,
-+ CROMW2_a128_m = 0x00000100,
-+ CROMW2_a192_b = 9,
-+ CROMW2_a192_m = 0x00000200,
-+ CROMW2_a256_b = 10,
-+ CROMW2_a256_m = 0x00000400,
-+ CROMW2_md5_b = 11,
-+ CROMW2_md5_m = 0x00000800,
-+ CROMW2_s1_b = 12,
-+ CROMW2_s1_m = 0x00001000,
-+ CROMW2_s256_b = 13,
-+ CROMW2_s256_m = 0x00002000,
-+ CROMW2_pka_b = 14,
-+ CROMW2_pka_m = 0x00004000,
-+ CROMW2_exp_b = 15,
-+ CROMW2_exp_m = 0x00018000,
-+ CROMW2_exp_8192_v = 0,
-+ CROMW2_exp_1536_v = 1,
-+ CROMW2_exp_1024_v = 2,
-+ CROMW2_exp_512_v = 3,
-+ CROMW2_rocfg_b = 17,
-+ CROMW2_rocfg_m = 0x000e0000,
-+} ;
-+
-+#endif // __IDT_CROM_H__
diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
--- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,175 @@
++++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,173 @@
+#ifndef __IDT_DDR_H__
+#define __IDT_DDR_H__
+
+ *
+ ******************************************************************************/
+
-+#include <asm/rc32434/types.h>
-+
+enum
+{
+ DDR0_PhysicalAddress = 0x18018000,
+
+typedef struct DDR_s
+{
-+ U32 ddrbase ;
-+ U32 ddrmask ;
-+ U32 res1;
-+ U32 res2;
-+ U32 ddrc ;
-+ U32 ddrabase ;
-+ U32 ddramask ;
-+ U32 ddramap ;
-+ U32 ddrcust;
-+ U32 ddrrdc;
-+ U32 ddrspare;
++ u32 ddrbase ;
++ u32 ddrmask ;
++ u32 res1;
++ u32 res2;
++ u32 ddrc ;
++ u32 ddrabase ;
++ u32 ddramask ;
++ u32 ddramap ;
++ u32 ddrcust;
++ u32 ddrrdc;
++ u32 ddrspare;
+} volatile *DDR_t ;
+
+enum
+} ;
+
+#endif // __IDT_DDR_H__
-diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
---- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/dev.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,134 @@
-+#ifndef __IDT_DEV_H__
-+#define __IDT_DEV_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Device Controller register definition.
-+ *
-+ * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
-+ *
-+ * Author : John.Ahrens@idt.com
-+ * Date : 200112013
-+ * Update :
-+ * $Log: dev.h,v $
-+ * Revision 1.2 2002/06/06 18:34:03 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:21 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ DEV0_PhysicalAddress = 0x18010000,
-+ DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
-+
-+ DEV0_VirtualAddress = 0xb8010000,
-+ DEV_VirtualAddress = DEV0_VirtualAddress, // Default
-+} ;
-+
-+typedef struct DEVICE_s
-+{
-+ U32 devbase ; // Device Base
-+ U32 devmask ; // Device Mask
-+ U32 devc ; // Device Control
-+ U32 devtc ; // Device Timing Control
-+} volatile *DEVICE_t ;
-+
-+enum
-+{
-+ DEV_Count = 3,
-+} ;
-+
-+typedef struct DEV_s
-+{
-+ struct DEVICE_s dev [DEV_Count] ;
-+ U32 btcs ; // Bus timeout control / status
-+ U32 btcompare ; // Compare
-+ U32 btaddr ; // Timeout address.
-+ U32 devdacs ; // Decoupled access control.
-+ U32 devdaa ; // Decoupled access address.
-+ U32 devdad ; // Decoupled access address.
-+ U32 devspare ; // spare.
-+} volatile *DEV_t ;
-+
-+enum
-+{
-+ DEVBASE_baseaddr_b = 16,
-+ DEVBASE_baseaddr_m = 0xffff0000,
-+ DEVMASK_mask_b = 16,
-+ DEVMASK_mask_m = 0xffff0000,
-+
-+ DEVC_ds_b = 0,
-+ DEVC_ds_m = 0x00000003,
-+ DEVC_ds_8_v = 0, // 8-bit device.
-+ DEVC_ds_16_v = 1, // reserved
-+ DEVC_ds_res_v = 2, // reserved.
-+ DEVC_ds_res2_v = 3, // reserved.
-+ DEVC_be_b = 2,
-+ DEVC_be_m = 0x00000004,
-+ DEVC_wp_b = 3,
-+ DEVC_wp_m = 0x00000008,
-+ DEVC_csd_b = 4,
-+ DEVC_csd_m = 0x000000f0,
-+ DEVC_oed_b = 8,
-+ DEVC_oed_m = 0x00000f00,
-+ DEVC_bwd_b = 12,
-+ DEVC_bwd_m = 0x0000f000,
-+ DEVC_rws_b = 16,
-+ DEVC_rws_m = 0x003f0000,
-+ DEVC_wws_b = 22,
-+ DEVC_wws_m = 0x0fc00000,
-+ DEVC_bre_b = 28,
-+ DEVC_bre_m = 0x10000000,
-+ DEVC_bwe_b = 29,
-+ DEVC_bwe_m = 0x20000000,
-+ DEVC_wam_b = 30,
-+ DEVC_wam_m = 0x40000000,
-+
-+ DEVTC_prd_b = 0,
-+ DEVTC_prd_m = 0x0000000f,
-+ DEVTC_pwd_b = 4,
-+ DEVTC_pwd_m = 0x000000f0,
-+ DEVTC_wdh_b = 8,
-+ DEVTC_wdh_m = 0x00000700,
-+ DEVTC_csh_b = 11,
-+ DEVTC_csh_m = 0x00001800,
-+
-+ BTCS_tt_b = 0,
-+ BTCS_tt_m = 0x00000001,
-+ BTCS_tt_write = 0,
-+ BTCS_tt_read = 1,
-+ BTCS_bto_b = 1, // In btcs
-+ BTCS_bto_m = 0x00000002, // In btcs
-+ BTCS_bte_b = 2, // In btcs
-+ BTCS_bte_m = 0x00000004, // In btcs
-+
-+ BTCOMPARE_compare_b = 0, // In btcompare
-+ BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
-+
-+ DEVDACS_op_b = 0, // In devdacs
-+ DEVDACS_op_m = 0x00000001, // In devdacs
-+ DEVDACS_op_write_v = 0,
-+ DEVDACS_op_read_v = 1,
-+ DEVDACS_size_b = 1, // In devdacs
-+ DEVDACS_size_m = 0x00000006, // In devdacs
-+ DEVDACS_size_byte_v = 0,
-+ DEVDACS_size_halfword = 1,
-+ DEVDACS_size_triplebyte = 2,
-+ DEVDACS_size_word = 3,
-+ DEVDACS_err_b = 3, // In devdacs
-+ DEVDACS_err_m = 0x00000008, // In devdacs
-+ DEVDACS_f_b = 4, // In devdacs
-+ DEVDACS_f_m = 0x00000010, // In devdacs
-+} ;
-+
-+#endif //__IDT_DEV_H__
-+
diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
--- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/dma.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,202 @@
++++ linux.dev/include/asm-mips/rc32434/dma.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,168 @@
+#ifndef __IDT_DMA_H__
+#define __IDT_DMA_H__
+
+ *
+ ******************************************************************************/
+
-+#include <asm/rc32434/types.h>
+enum
+{
+ DMA0_PhysicalAddress = 0x18040000,
+
+typedef struct DMAD_s
+{
-+ U32 control ; // Control. use DMAD_*
-+ U32 ca ; // Current Address.
-+ U32 devcs ; // Device control and status.
-+ U32 link ; // Next descriptor in chain.
++ u32 control ; // Control. use DMAD_*
++ u32 ca ; // Current Address.
++ u32 devcs ; // Device control and status.
++ u32 link ; // Next descriptor in chain.
+} volatile *DMAD_t ;
+
+enum
+
+struct DMA_Chan_s
+{
-+ U32 dmac ; // Control.
-+ U32 dmas ; // Status.
-+ U32 dmasm ; // Mask.
-+ U32 dmadptr ; // Descriptor pointer.
-+ U32 dmandptr ; // Next descriptor pointer.
++ u32 dmac ; // Control.
++ u32 dmas ; // Status.
++ u32 dmasm ; // Mask.
++ u32 dmadptr ; // Descriptor pointer.
++ u32 dmandptr ; // Next descriptor pointer.
+};
+
+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
+ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
+} volatile *DMA_t ;
+
-+
-+/*
-+ * External DMA parameters
-+*/
-+#if 0
-+enum
-+{
-+ DMADEVCMD_ts_b = 0, // ts field in devcmd
-+ DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
-+ DMADEVCMD_ts_byte_v = 0,
-+ DMADEVCMD_ts_halfword_v = 1,
-+ DMADEVCMD_ts_word_v = 2,
-+ DMADEVCMD_ts_2word_v = 3,
-+ DMADEVCMD_ts_4word_v = 4,
-+ DMADEVCMD_ts_6word_v = 5,
-+ DMADEVCMD_ts_8word_v = 6,
-+ DMADEVCMD_ts_16word_v = 7
-+};
-+#endif
-+
-+#if 1 // aws - Compatibility.
-+# define EXTDMA_ts_b DMADEVCMD_ts_b
-+# define EXTDMA_ts_m DMADEVCMD_ts_m
-+# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
-+# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
-+# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
-+# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
-+# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
-+# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
-+# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
-+# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
-+#endif // aws - Compatibility.
-+
+#endif // __IDT_DMA_H__
+
diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
--- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,73 @@
++++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,72 @@
+#ifndef __IDT_DMA_V_H__
+#define __IDT_DMA_V_H__
+
+ *
+ *
+ ******************************************************************************/
-+#include <asm/rc32434/types.h>
+#include <asm/rc32434/dma.h>
+#include <asm/rc32434/rc32434.h>
+#define DMA_CHAN_OFFSET 0x14
+
diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
--- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/eth.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,322 @@
++++ linux.dev/include/asm-mips/rc32434/eth.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,320 @@
+#ifndef __IDT_ETH_H__
+#define __IDT_ETH_H__
+
+ *
+ ******************************************************************************/
+
-+#include <asm/rc32434/types.h>
-+
+enum
+{
+ ETH0_PhysicalAddress = 0x18060000,
+
+typedef struct
+{
-+ U32 ethintfc ;
-+ U32 ethfifott ;
-+ U32 etharc ;
-+ U32 ethhash0 ;
-+ U32 ethhash1 ;
-+ U32 ethu0 [4] ; // Reserved.
-+ U32 ethpfs ;
-+ U32 ethmcp ;
-+ U32 eth_u1 [10] ; // Reserved.
-+ U32 ethspare ;
-+ U32 eth_u2 [42] ; // Reserved.
-+ U32 ethsal0 ;
-+ U32 ethsah0 ;
-+ U32 ethsal1 ;
-+ U32 ethsah1 ;
-+ U32 ethsal2 ;
-+ U32 ethsah2 ;
-+ U32 ethsal3 ;
-+ U32 ethsah3 ;
-+ U32 ethrbc ;
-+ U32 ethrpc ;
-+ U32 ethrupc ;
-+ U32 ethrfc ;
-+ U32 ethtbc ;
-+ U32 ethgpf ;
-+ U32 eth_u9 [50] ; // Reserved.
-+ U32 ethmac1 ;
-+ U32 ethmac2 ;
-+ U32 ethipgt ;
-+ U32 ethipgr ;
-+ U32 ethclrt ;
-+ U32 ethmaxf ;
-+ U32 eth_u10 ; // Reserved.
-+ U32 ethmtest ;
-+ U32 miimcfg ;
-+ U32 miimcmd ;
-+ U32 miimaddr ;
-+ U32 miimwtd ;
-+ U32 miimrdd ;
-+ U32 miimind ;
-+ U32 eth_u11 ; // Reserved.
-+ U32 eth_u12 ; // Reserved.
-+ U32 ethcfsa0 ;
-+ U32 ethcfsa1 ;
-+ U32 ethcfsa2 ;
++ u32 ethintfc ;
++ u32 ethfifott ;
++ u32 etharc ;
++ u32 ethhash0 ;
++ u32 ethhash1 ;
++ u32 ethu0 [4] ; // Reserved.
++ u32 ethpfs ;
++ u32 ethmcp ;
++ u32 eth_u1 [10] ; // Reserved.
++ u32 ethspare ;
++ u32 eth_u2 [42] ; // Reserved.
++ u32 ethsal0 ;
++ u32 ethsah0 ;
++ u32 ethsal1 ;
++ u32 ethsah1 ;
++ u32 ethsal2 ;
++ u32 ethsah2 ;
++ u32 ethsal3 ;
++ u32 ethsah3 ;
++ u32 ethrbc ;
++ u32 ethrpc ;
++ u32 ethrupc ;
++ u32 ethrfc ;
++ u32 ethtbc ;
++ u32 ethgpf ;
++ u32 eth_u9 [50] ; // Reserved.
++ u32 ethmac1 ;
++ u32 ethmac2 ;
++ u32 ethipgt ;
++ u32 ethipgr ;
++ u32 ethclrt ;
++ u32 ethmaxf ;
++ u32 eth_u10 ; // Reserved.
++ u32 ethmtest ;
++ u32 miimcfg ;
++ u32 miimcmd ;
++ u32 miimaddr ;
++ u32 miimwtd ;
++ u32 miimrdd ;
++ u32 miimind ;
++ u32 eth_u11 ; // Reserved.
++ u32 eth_u12 ; // Reserved.
++ u32 ethcfsa0 ;
++ u32 ethcfsa1 ;
++ u32 ethcfsa2 ;
+} volatile *ETH_t;
+
+enum
+
diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
--- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,64 @@
++++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,63 @@
+#ifndef __IDT_ETH_V_H__
+#define __IDT_ETH_V_H__
+
+ *
+ ******************************************************************************/
+
-+#include <asm/rc32434/types.h>
+#include <asm/rc32434/eth.h>
+
+#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
+
diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
--- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,182 @@
++++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,181 @@
+#ifndef __IDT_GPIO_H__
+#define __IDT_GPIO_H__
+
+ *
+ ******************************************************************************/
+
-+#include <asm/rc32434/types.h>
+enum
+{
+ GPIO0_PhysicalAddress = 0x18050000,
+
+typedef struct
+{
-+ U32 gpiofunc; /* GPIO Function Register
++ u32 gpiofunc; /* GPIO Function Register
+ * gpiofunc[x]==0 bit = gpio
+ * func[x]==1 bit = altfunc
+ */
-+ U32 gpiocfg; /* GPIO Configuration Register
++ u32 gpiocfg; /* GPIO Configuration Register
+ * gpiocfg[x]==0 bit = input
+ * gpiocfg[x]==1 bit = output
+ */
-+ U32 gpiod; /* GPIO Data Register
++ u32 gpiod; /* GPIO Data Register
+ * gpiod[x] read/write gpio pinX status
+ */
-+ U32 gpioilevel; /* GPIO Interrupt Status Register
++ u32 gpioilevel; /* GPIO Interrupt Status Register
+ * interrupt level (see gpioistat)
+ */
-+ U32 gpioistat; /* Gpio Interrupt Status Register
++ u32 gpioistat; /* Gpio Interrupt Status Register
+ * istat[x] = (gpiod[x] == level[x])
+ * cleared in ISR (STICKY bits)
+ */
-+ U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
++ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
+} volatile * GPIO_t ;
+
+typedef enum
+
+#endif // __IDT_GPIO_H__
+
-diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
---- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,147 @@
-+#ifndef __IDT_I2C_H__
-+#define __IDT_I2C_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * I2C register definitions.
-+ *
-+ * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020120
-+ * Update :
-+ * $Log: i2c.h,v $
-+ * Revision 1.2 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:22 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ I2C0_PhysicalAddress = 0x18068000,
-+ I2C_PhysicalAddress = I2C0_PhysicalAddress,
-+
-+ I2C0_VirtualAddress = 0xb8068000,
-+ I2C_VirtualAddress = I2C0_VirtualAddress,
-+} ;
-+
-+typedef struct
-+{
-+ U32 i2cc ;
-+ U32 i2cdi ;
-+ U32 i2cdo ;
-+ U32 i2ccp ; // I2C clk = ICLK / div / 8
-+ U32 i2cmcmd ;
-+ U32 i2cms ;
-+ U32 i2cmsm ;
-+ U32 i2css ;
-+ U32 i2cssm ;
-+ U32 i2csaddr ;
-+ U32 i2csack ;
-+} volatile * I2C_t ;
-+enum
-+{
-+ I2CC_men_b = 0, // In I2C-> i2cc
-+ I2CC_men_m = 0x00000001,
-+ I2CC_sen_b = 1, // In I2C-> i2cc
-+ I2CC_sen_m = 0x00000002,
-+ I2CC_iom_b = 2, // In I2C-> i2cc
-+ I2CC_iom_m = 0x00000004,
-+
-+ I2CDI_data_b = 0, // In I2C-> i2cdi
-+ I2CDI_data_m = 0x000000ff,
-+
-+ I2CDO_data_b = 0, // In I2C-> i2cdo
-+ I2CDO_data_m = 0x000000ff,
-+
-+ I2CCP_div_b = 0, // In I2C-> i2ccp
-+ I2CCP_div_m = 0x0000ffff,
-+
-+ I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
-+ I2CMCMD_cmd_m = 0x0000000f,
-+ I2CMCMD_cmd_nop_v = 0,
-+ I2CMCMD_cmd_start_v = 1,
-+ I2CMCMD_cmd_stop_v = 2,
-+ I2CMCMD_cmd_res3_v = 3,
-+ I2CMCMD_cmd_rd_v = 4,
-+ I2CMCMD_cmd_rdack_v = 5,
-+ I2CMCMD_cmd_wd_v = 6,
-+ I2CMCMD_cmd_wdack_v = 7,
-+ I2CMCMD_cmd_res8_v = 8,
-+ I2CMCMD_cmd_res9_v = 9,
-+ I2CMCMD_cmd_res10_v = 10,
-+ I2CMCMD_cmd_res11_v = 11,
-+ I2CMCMD_cmd_res12_v = 12,
-+ I2CMCMD_cmd_res13_v = 13,
-+ I2CMCMD_cmd_res14_v = 14,
-+ I2CMCMD_cmd_res15_v = 15,
-+
-+ I2CMS_d_b = 0, // In I2C-> i2cms
-+ I2CMS_d_m = 0x00000001,
-+ I2CMS_na_b = 1, // In I2C-> i2cms
-+ I2CMS_na_m = 0x00000002,
-+ I2CMS_la_b = 2, // In I2C-> i2cms
-+ I2CMS_la_m = 0x00000004,
-+ I2CMS_err_b = 3, // In I2C-> i2cms
-+ I2CMS_err_m = 0x00000008,
-+
-+ I2CMSM_d_b = 0, // In I2C-> i2cmsm
-+ I2CMSM_d_m = 0x00000001,
-+ I2CMSM_na_b = 1, // In I2C-> i2cmsm
-+ I2CMSM_na_m = 0x00000002,
-+ I2CMSM_la_b = 2, // In I2C-> i2cmsm
-+ I2CMSM_la_m = 0x00000004,
-+ I2CMSM_err_b = 3, // In I2C-> i2cmsm
-+ I2CMSM_err_m = 0x00000008,
-+
-+ I2CSS_rr_b = 0, // In I2C-> i2css
-+ I2CSS_rr_m = 0x00000001,
-+ I2CSS_wr_b = 1, // In I2C-> i2css
-+ I2CSS_wr_m = 0x00000002,
-+ I2CSS_sa_b = 2, // In I2C-> i2css
-+ I2CSS_sa_m = 0x00000004,
-+ I2CSS_tf_b = 3, // In I2C-> i2css
-+ I2CSS_tf_m = 0x00000008,
-+ I2CSS_gc_b = 4, // In I2C-> i2css
-+ I2CSS_gc_m = 0x00000010,
-+ I2CSS_na_b = 5, // In I2C-> i2css
-+ I2CSS_na_m = 0x00000020,
-+ I2CSS_err_b = 6, // In I2C-> i2css
-+ I2CSS_err_m = 0x00000040,
-+
-+ I2CSSM_rr_b = 0, // In I2C-> i2cssm
-+ I2CSSM_rr_m = 0x00000001,
-+ I2CSSM_wr_b = 1, // In I2C-> i2cssm
-+ I2CSSM_wr_m = 0x00000002,
-+ I2CSSM_sa_b = 2, // In I2C-> i2cssm
-+ I2CSSM_sa_m = 0x00000004,
-+ I2CSSM_tf_b = 3, // In I2C-> i2cssm
-+ I2CSSM_tf_m = 0x00000008,
-+ I2CSSM_gc_b = 4, // In I2C-> i2cssm
-+ I2CSSM_gc_m = 0x00000010,
-+ I2CSSM_na_b = 5, // In I2C-> i2cssm
-+ I2CSSM_na_m = 0x00000020,
-+ I2CSSM_err_b = 6, // In I2C-> i2cssm
-+ I2CSSM_err_m = 0x00000040,
-+
-+ I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
-+ I2CSADDR_addr_m = 0x000003ff,
-+ I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
-+ I2CSADDR_a_gc_m = 0x00000400,
-+ I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
-+ I2CSADDR_a10_m = 0x00000800,
-+
-+ I2CSACK_ack_b = 0, // In I2C-> i2csack
-+ I2CSACK_ack_m = 0x00000001,
-+
-+} ;
-+#endif // __IDT_I2C_H__
-diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
---- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/integ.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,78 @@
-+#ifndef __IDT_INTEG_H__
-+#define __IDT_INTEG_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * System Integrity register definition.
-+ *
-+ * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : ryan.holmQVist@idt.com
-+ * Date : 20011005
-+ * Update :
-+ * $Log: integ.h,v $
-+ * Revision 1.3 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/05 18:32:33 astichte
-+ * Removed IDTField
-+ *
-+ * Revision 1.1 2002/05/29 17:33:22 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ INTEG0_PhysicalAddress = 0x18030000,
-+ INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
-+
-+ INTEG0_VirtualAddress = 0xb8030000,
-+ INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
-+} ;
-+
-+// if you are looing for CEA, try rst.h
-+typedef struct
-+{
-+ U32 filler [0xc] ; // 0x30 bytes unused.
-+ U32 errcs ; // sticky use ERRCS_
-+ U32 wtcount ; // Watchdog timer count reg.
-+ U32 wtcompare ; // Watchdog timer timeout value.
-+ U32 wtc ; // Watchdog timer control. use WTC_
-+} volatile *INTEG_t ;
-+
-+enum
-+{
-+ ERRCS_wto_b = 0, // In INTEG_t -> errcs
-+ ERRCS_wto_m = 0x00000001,
-+ ERRCS_wne_b = 1, // In INTEG_t -> errcs
-+ ERRCS_wne_m = 0x00000002,
-+ ERRCS_ucw_b = 2, // In INTEG_t -> errcs
-+ ERRCS_ucw_m = 0x00000004,
-+ ERRCS_ucr_b = 3, // In INTEG_t -> errcs
-+ ERRCS_ucr_m = 0x00000008,
-+ ERRCS_upw_b = 4, // In INTEG_t -> errcs
-+ ERRCS_upw_m = 0x00000010,
-+ ERRCS_upr_b = 5, // In INTEG_t -> errcs
-+ ERRCS_upr_m = 0x00000020,
-+ ERRCS_udw_b = 6, // In INTEG_t -> errcs
-+ ERRCS_udw_m = 0x00000040,
-+ ERRCS_udr_b = 7, // In INTEG_t -> errcs
-+ ERRCS_udr_m = 0x00000080,
-+ ERRCS_sae_b = 8, // In INTEG_t -> errcs
-+ ERRCS_sae_m = 0x00000100,
-+ ERRCS_wre_b = 9, // In INTEG_t -> errcs
-+ ERRCS_wre_m = 0x00000200,
-+
-+ WTC_en_b = 0, // In INTEG_t -> wtc
-+ WTC_en_m = 0x00000001,
-+ WTC_to_b = 1, // In INTEG_t -> wtc
-+ WTC_to_m = 0x00000002,
-+} ;
-+
-+#endif // __IDT_INTEG_H__
-diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
---- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/int.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,167 @@
-+#ifndef __IDT_INT_H__
-+#define __IDT_INT_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Interrupt Controller register definition.
-+ *
-+ * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : ryan.holmqvist@idt.com
-+ * Date : 20011005
-+ * Update :
-+ * $Log: int.h,v $
-+ * Revision 1.3 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/05 18:47:33 astichte
-+ * Removed IDTField
-+ *
-+ * Revision 1.1 2002/05/29 17:33:22 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ INT0_PhysicalAddress = 0x18038000,
-+ INT_PhysicalAddress = INT0_PhysicalAddress, // Default
-+
-+ INT0_VirtualAddress = 0xb8038000,
-+ INT_VirtualAddress = INT0_VirtualAddress, // Default
-+} ;
-+
-+struct INT_s
-+{
-+ U32 ipend ; //Pending interrupts. use INT?_
-+ U32 itest ; //Test bits. use INT?_
-+ U32 imask ; //Interrupt disabled when set. use INT?_
-+} ;
-+
-+enum
-+{
-+ IPEND2 = 0, // HW 2 interrupt to core. use INT2_
-+ IPEND3 = 1, // HW 3 interrupt to core. use INT3_
-+ IPEND4 = 2, // HW 4 interrupt to core. use INT4_
-+ IPEND5 = 3, // HW 5 interrupt to core. use INT5_
-+ IPEND6 = 4, // HW 6 interrupt to core. use INT6_
-+
-+ IPEND_count, // must be last (used in loops)
-+ IPEND_min = IPEND2 // min IPEND (used in loops)
-+};
-+
-+typedef struct INTC_s
-+{
-+ struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
-+ U32 nmips ; // use NMIPS_
-+} volatile *INT_t ;
-+
-+enum
-+{
-+ INT2_timer0_b = 0,
-+ INT2_timer0_m = 0x00000001,
-+ INT2_timer1_b = 1,
-+ INT2_timer1_m = 0x00000002,
-+ INT2_timer2_b = 2,
-+ INT2_timer2_m = 0x00000004,
-+ INT2_refresh_b = 3,
-+ INT2_refresh_m = 0x00000008,
-+ INT2_watchdogTimeout_b = 4,
-+ INT2_watchdogTimeout_m = 0x00000010,
-+ INT2_undecodedCpuWrite_b = 5,
-+ INT2_undecodedCpuWrite_m = 0x00000020,
-+ INT2_undecodedCpuRead_b = 6,
-+ INT2_undecodedCpuRead_m = 0x00000040,
-+ INT2_undecodedPciWrite_b = 7,
-+ INT2_undecodedPciWrite_m = 0x00000080,
-+ INT2_undecodedPciRead_b = 8,
-+ INT2_undecodedPciRead_m = 0x00000100,
-+ INT2_undecodedDmaWrite_b = 9,
-+ INT2_undecodedDmaWrite_m = 0x00000200,
-+ INT2_undecodedDmaRead_b = 10,
-+ INT2_undecodedDmaRead_m = 0x00000400,
-+ INT2_ipBusSlaveAckError_b = 11,
-+ INT2_ipBusSlaveAckError_m = 0x00000800,
-+
-+ INT3_dmaChannel0_b = 0,
-+ INT3_dmaChannel0_m = 0x00000001,
-+ INT3_dmaChannel1_b = 1,
-+ INT3_dmaChannel1_m = 0x00000002,
-+ INT3_dmaChannel2_b = 2,
-+ INT3_dmaChannel2_m = 0x00000004,
-+ INT3_dmaChannel3_b = 3,
-+ INT3_dmaChannel3_m = 0x00000008,
-+ INT3_dmaChannel4_b = 4,
-+ INT3_dmaChannel4_m = 0x00000010,
-+ INT3_dmaChannel5_b = 5,
-+ INT3_dmaChannel5_m = 0x00000020,
-+
-+ INT5_uartGeneral0_b = 0,
-+ INT5_uartGeneral0_m = 0x00000001,
-+ INT5_uartTxrdy0_b = 1,
-+ INT5_uartTxrdy0_m = 0x00000002,
-+ INT5_uartRxrdy0_b = 2,
-+ INT5_uartRxrdy0_m = 0x00000004,
-+ INT5_pci_b = 3,
-+ INT5_pci_m = 0x00000008,
-+ INT5_pciDecoupled_b = 4,
-+ INT5_pciDecoupled_m = 0x00000010,
-+ INT5_spi_b = 5,
-+ INT5_spi_m = 0x00000020,
-+ INT5_deviceDecoupled_b = 6,
-+ INT5_deviceDecoupled_m = 0x00000040,
-+ INT5_i2cMaster_b = 7,
-+ INT5_i2cMaster_m = 0x00000080,
-+ INT5_i2cSlave_b = 8,
-+ INT5_i2cSlave_m = 0x00000100,
-+ INT5_ethOvr_b = 9,
-+ INT5_ethOvr_m = 0x00000200,
-+ INT5_ethUnd_b = 10,
-+ INT5_ethUnd_m = 0x00000400,
-+ INT5_ethPfd_b = 11,
-+ INT5_ethPfd_m = 0x00000800,
-+ INT5_nvram_b = 12,
-+ INT5_nvram_m = 0x00001000,
-+
-+ INT6_gpio0_b = 0,
-+ INT6_gpio0_m = 0x00000001,
-+ INT6_gpio1_b = 1,
-+ INT6_gpio1_m = 0x00000002,
-+ INT6_gpio2_b = 2,
-+ INT6_gpio2_m = 0x00000004,
-+ INT6_gpio3_b = 3,
-+ INT6_gpio3_m = 0x00000008,
-+ INT6_gpio4_b = 4,
-+ INT6_gpio4_m = 0x00000010,
-+ INT6_gpio5_b = 5,
-+ INT6_gpio5_m = 0x00000020,
-+ INT6_gpio6_b = 6,
-+ INT6_gpio6_m = 0x00000040,
-+ INT6_gpio7_b = 7,
-+ INT6_gpio7_m = 0x00000080,
-+ INT6_gpio8_b = 8,
-+ INT6_gpio8_m = 0x00000100,
-+ INT6_gpio9_b = 9,
-+ INT6_gpio9_m = 0x00000200,
-+ INT6_gpio10_b = 10,
-+ INT6_gpio10_m = 0x00000400,
-+ INT6_gpio11_b = 11,
-+ INT6_gpio11_m = 0x00000800,
-+ INT6_gpio12_b = 12,
-+ INT6_gpio12_m = 0x00001000,
-+ INT6_gpio13_b = 13,
-+ INT6_gpio13_m = 0x00002000,
-+
-+ NMIPS_gpio_b = 0,
-+ NMIPS_gpio_m = 0x00000001,
-+} ;
-+
-+#endif // __IDT_INT_H__
-+
-+
-diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
---- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,95 @@
-+#ifndef __IDT_IPARB_H__
-+#define __IDT_IPARB_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * IP Arbiter register definitions.
-+ *
-+ * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020120
-+ * Update :
-+ * $Log: iparb.h,v $
-+ * Revision 1.3 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/05 19:01:42 astichte
-+ * Removed IDTField
-+ *
-+ * Revision 1.1 2002/05/29 17:33:23 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ IPARB0_PhysicalAddress = 0x18048000,
-+ IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
-+
-+ IPARB0_VirtualAddress = 0xb8048000,
-+ IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ IPABMXC_ethernetReceive = 0,
-+ IPABMXC_ethernetTransmit = 1,
-+ IPABMXC_memoryToHoldFifo = 2,
-+ IPABMXC_holdFifoToMemory = 3,
-+ IPABMXC_pciToMemory = 4,
-+ IPABMXC_memoryToPci = 5,
-+ IPABMXC_pciTarget = 6,
-+ IPABMXC_pciTargetStart = 7,
-+ IPABMXC_cpuToIpBus = 8,
-+
-+ IPABMXC_Count, // Must be last in list !
-+ IPABMXC_Min = IPABMXC_ethernetReceive,
-+
-+ IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
-+} ;
-+
-+typedef struct
-+{
-+ U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
-+ U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
-+ U32 ipac ; // use IPAC_
-+ U32 ipaitcc; // use IPAITCC_
-+ U32 ipaspare ;
-+} volatile * IPARB_t ;
-+
-+enum
-+{
-+ IPAC_dwm_b = 2,
-+ IPAC_dwm_m = 0x00000004,
-+ IPAC_drm_b = 3,
-+ IPAC_drm_m = 0x00000008,
-+ IPAC_msk_b = 4,
-+ IPAC_msk_m = 0x00000010,
-+
-+ IPAPC_ptc_b = 0,
-+ IPAPC_ptc_m = 0x00003fff,
-+ IPAPC_mf_b = 14,
-+ IPAPC_mf_m = 0x00004000,
-+ IPAPC_cptc_b = 16,
-+ IPAPC_cptc_m = 0x3fff0000,
-+
-+ IPAITCC_itcc = 0,
-+ IPAITCC_itcc, = 0x000001ff,
-+
-+ IPABMC_mtc_b = 0,
-+ IPABMC_mtc_m = 0x00000fff,
-+ IPABMC_p_b = 12,
-+ IPABMC_p_m = 0x00003000,
-+ IPABMC_msk_b = 14,
-+ IPABMC_msk_m = 0x00004000,
-+ IPABMC_cmtc_b = 16,
-+ IPABMC_cmtc_m = 0x0fff0000,
-+};
-+
-+#endif // __IDT_IPARB_H__
-diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
---- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/irm.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,55 @@
-+#ifndef __IDT_IRM_H__
-+#define __IDT_IRM_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Internal Register Map
-+ *
-+ * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020605
-+ * Update :
-+ * $Log: irm.h,v $
-+ * Revision 1.2 2002/06/05 14:51:06 astichte
-+ * *** empty log message ***
-+ *
-+ * Revision 1.1 2002/05/29 17:33:23 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ ******************************************************************************/
-+
-+/*
-+ * NOTE --
-+ * This file is here for backwards compatibility.
-+ * DO NOT USE !!!!
-+ */
-+
-+typedef enum
-+{
-+ IRM_Physical = 0x18000000, // Internal Reg. map physical.
-+ RST_Offset = 0x00000000, // Includes sysid and RST.
-+ DEV_Offset = 0x00010000, // Device Controller 0.
-+ DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
-+ PMARB_Offset = 0x00020000, // PM bus arbiter.
-+ TIM_Offset = 0x00028000, // Counter / timer.
-+ INTEG_Offset = 0x00030000, // System Integrity.
-+ INT_Offset = 0x00038000, // Interrupt controller.
-+ DMA_Offset = 0x00040000, // DMA.
-+ IPARB_Offset = 0x00044000, // IP bus arbiter.
-+ GPIO_Offset = 0x00050000, // GPIO.
-+ UART_Offset = 0x00058000, // UART
-+ ETH_Offset = 0x00060000, // Ethernet 1.
-+ I2C_Offset = 0x00068000, // I2C interface.
-+ SPI_Offset = 0x00070000, // Serial Peripheral Interface.
-+ NVRAM_Offset = 0x00078000, // NVRAM interface
-+ AUTH_Offset = 0x0007c000, // Authorization unit
-+ PCI_Offset = 0x00080000,
-+ CROM_Offset = 0x000b8000, // Configuration ROM.
-+ IRM_Size = 0x00200000, // Internal Reg. map size.
-+} IRM_Offset_t ;
-+
-+#endif // __IDT_IRM_H__
diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
--- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/irq.h 2006-06-18 17:18:16.000000000 +0200
++++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+
+#define NR_IRQS 256
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
-diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
---- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,97 @@
-+#ifndef __IDT_NVRAM_H
-+#define __IDT_NVRAM_H
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * IP Arbiter register definitions.
-+ *
-+ * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
-+ *
-+ * Author : kiran.rao@idt.com
-+ * Date : 20030724
-+ * Update :
-+ * $Log: nvram.h,v $
-+ *
-+ *
-+ ******************************************************************************/
-+#include <asm/rc32434/tpes.h>
-+
-+
-+enum
-+{
-+ NVRAM0_PhysicalAddress = 0xba000000,
-+ NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
-+
-+ NVRAM0_VirtualAddress = 0xba000000,
-+ NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ NVRCMD_cmd_b = 0,
-+ NVRCMD_cmd_m = 0x0000007f,
-+
-+ NVRS_r_b = 0,
-+ NVRS_r_m = 0x00000001,
-+ NVRS_e_b = 1,
-+ NVRS_e_m = 0x00000002,
-+ NVRS_k_b = 2,
-+ NVRS_k_m = 0x00000004,
-+
-+ NVRSM_r_b = 0,
-+ NVRSM_r_m = 0x00000001,
-+ NVRSM_e_b = 1,
-+ NVRSM_e_m = 0x00000002,
-+ NVRSM_k_b = 2,
-+ NVRSM_k_m = 0x00000004,
-+
-+ NVRCFG0_pwidth_b = 0,
-+ NVRCFG0_pwidth_m = 0x00000003,
-+ NVRCFG0_nmax_b = 2,
-+ NVRCFG0_nmax_m = 0x0000000C,
-+ NVRCFG0_vppl_b = 4,
-+ NVRCFG0_vppl_m = 0x000000f0,
-+ NVRCFG0_vppm_b = 8,
-+ NVRCFG0_vppm_m = 0x00000300,
-+ NVRCFG0_dvpp_b = 10,
-+ NVRCFG0_dvpp_m = 0x00000c00,
-+ NVRCFG0_x_b = 12,
-+ NVRCFG0_x_m = 0x00007000,
-+
-+ NVRCFG1_t1tecc_b = 0,
-+ NVRCFG1_t1tecc_m = 0x00000003,
-+ NVRCFG1_t1mrcl_b = 2,
-+ NVRCFG1_t1mrcl_m = 0x0000000c,
-+ NVRCFG1_t1bias_b = 4,
-+ NVRCFG1_t1bias_m = 0x00000030,
-+ NVRCFG1_t2tecc_b = 6,
-+ NVRCFG1_t2tecc_m = 0x000000c0,
-+ NVRCFG1_t2mrcl_b = 8,
-+ NVRCFG1_t2mrcl_m = 0x00000300,
-+ NVRCFG1_t2bias_b = 10,
-+ NVRCFG1_t2bias_m = 0x00000c00,
-+ NVRCFG1_t3tecc_b = 12,
-+ NVRCFG1_t3tecc_m = 0x00003000,
-+ NVRCFG1_t3mrcl_b = 14,
-+ NVRCFG1_t3mrcl_m = 0x0000c000,
-+ NVRCFG1_t3bias_b = 16,
-+ NVRCFG1_t3bias_m = 0x00030000,
-+ NVRCFG1_t4tecc_b = 18,
-+ NVRCFG1_t4tecc_m = 0x000c0000,
-+ NVRCFG1_t4mrcl_b = 20,
-+ NVRCFG1_t4mrcl_m = 0x00300000,
-+ NVRCFG1_t4bias_b = 22,
-+ NVRCFG1_t4bias_m = 0x00c00000,
-+ NVRCFG1_t5tecc_b = 24,
-+ NVRCFG1_t5tecc_m = 0x03000000,
-+ NVRCFG1_t5mrcl_b = 26,
-+ NVRCFG1_t5mrcl_m = 0x0c000000,
-+ NVRCFG1_t5bias_b = 28,
-+ NVRCFG1_t5bias_m = 0x30000000,
-+}
-+
-+#endif // __IDT_NVRAM_H__
-+
diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
--- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/pci.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,695 @@
++++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,692 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+#define PCIM_H_EA 0x3
+#define PCIM_H_IA_FIX 0x4
+#define PCIM_H_IA_RR 0x5
-+#if 0
-+#define PCI_ADDR_START 0x13000000
-+#endif
+
+#define PCI_ADDR_START 0x50000000
+
+
+
+
-diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
---- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,209 @@
-+/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
+diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
+--- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/rc32434/rb.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (C) 2004 IDT Inc.
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
+ */
-+#ifndef _PCIKORINA_H
-+#define _PCIKORINA_H
++#ifndef __MIPS_RB_H__
++#define __MIPS_RB_H__
++#include <linux/genhd.h>
+
++#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
++#define DEV0BASE 0x010000
++#define DEV0MASK 0x010004
++#define DEV0C 0x010008
++#define DEV0TC 0x01000C
++#define DEV1BASE 0x010010
++#define DEV1MASK 0x010014
++#define DEV1C 0x010018
++#define DEV1TC 0x01001C
++#define DEV2BASE 0x010020
++#define DEV2MASK 0x010024
++#define DEV2C 0x010028
++#define DEV2TC 0x01002C
++#define DEV3BASE 0x010030
++#define DEV3MASK 0x010034
++#define DEV3C 0x010038
++#define DEV3TC 0x01003C
++#define BTCS 0x010040
++#define BTCOMPARE 0x010044
++#define GPIOFUNC 0x050000
++#define GPIOCFG 0x050004
++#define GPIOD 0x050008
++#define GPIOILEVEL 0x05000C
++#define GPIOISTAT 0x050010
++#define GPIONMIEN 0x050014
++#define IMASK6 0x038038
+
-+#define PCI_MSG_VirtualAddress 0xB8088010
-+#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
-+#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
++#define LO_WPX (1 << 0)
++#define LO_ALE (1 << 1)
++#define LO_CLE (1 << 2)
++#define LO_CEX (1 << 3)
++#define LO_FOFF (1 << 5)
++#define LO_SPICS (1 << 6)
++#define LO_ULED (1 << 7)
+
-+#define PCIM_SHFT 0x6
-+#define PCIM_BIT_LEN 0x7
-+#define PCIM_H_EA 0x3
-+#define PCIM_H_IA_FIX 0x4
-+#define PCIM_H_IA_RR 0x5
-+#if 0
-+#define PCI_ADDR_START 0x13000000
-+#endif
++typedef enum {
++ FUNC = 0x00,
++ CFG = 0x04,
++ DATA = 0x08,
++ ILEVEL = 0x0c,
++ ISTAT = 0x10,
++ NMIEN = 0x14
++} gpio_func;
+
-+#define PCI_ADDR_START 0x50000000
-+
-+#define CPUTOPCI_MEM_WIN 0x02000000
-+#define CPUTOPCI_IO_WIN 0x00100000
-+#define PCILBA_SIZE_SHFT 2
-+#define PCILBA_SIZE_MASK 0x1F
-+#define SIZE_256MB 0x1C
-+#define SIZE_128MB 0x1B
-+#define SIZE_64MB 0x1A
-+#define SIZE_32MB 0x19
-+#define SIZE_16MB 0x18
-+#define SIZE_4MB 0x16
-+#define SIZE_2MB 0x15
-+#define SIZE_1MB 0x14
-+#define KORINA_CONFIG0_ADDR 0x80000000
-+#define KORINA_CONFIG1_ADDR 0x80000004
-+#define KORINA_CONFIG2_ADDR 0x80000008
-+#define KORINA_CONFIG3_ADDR 0x8000000C
-+#define KORINA_CONFIG4_ADDR 0x80000010
-+#define KORINA_CONFIG5_ADDR 0x80000014
-+#define KORINA_CONFIG6_ADDR 0x80000018
-+#define KORINA_CONFIG7_ADDR 0x8000001C
-+#define KORINA_CONFIG8_ADDR 0x80000020
-+#define KORINA_CONFIG9_ADDR 0x80000024
-+#define KORINA_CONFIG10_ADDR 0x80000028
-+#define KORINA_CONFIG11_ADDR 0x8000002C
-+#define KORINA_CONFIG12_ADDR 0x80000030
-+#define KORINA_CONFIG13_ADDR 0x80000034
-+#define KORINA_CONFIG14_ADDR 0x80000038
-+#define KORINA_CONFIG15_ADDR 0x8000003C
-+#define KORINA_CONFIG16_ADDR 0x80000040
-+#define KORINA_CONFIG17_ADDR 0x80000044
-+#define KORINA_CONFIG18_ADDR 0x80000048
-+#define KORINA_CONFIG19_ADDR 0x8000004C
-+#define KORINA_CONFIG20_ADDR 0x80000050
-+#define KORINA_CONFIG21_ADDR 0x80000054
-+#define KORINA_CONFIG22_ADDR 0x80000058
-+#define KORINA_CONFIG23_ADDR 0x8000005C
-+#define KORINA_CONFIG24_ADDR 0x80000060
-+#define KORINA_CONFIG25_ADDR 0x80000064
-+#define KORINA_CMD (PCFG04_command_ioena_m | \
-+ PCFG04_command_memena_m | \
-+ PCFG04_command_bmena_m | \
-+ PCFG04_command_mwinv_m | \
-+ PCFG04_command_parena_m | \
-+ PCFG04_command_serrena_m )
-+
-+#define KORINA_STAT (PCFG04_status_mdpe_m | \
-+ PCFG04_status_sta_m | \
-+ PCFG04_status_rta_m | \
-+ PCFG04_status_rma_m | \
-+ PCFG04_status_sse_m | \
-+ PCFG04_status_pe_m)
-+
-+#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
-+
-+#define KORINA_REVID 0
-+#define KORINA_CLASS_CODE 0
-+#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
-+ KORINA_REVID)
-+
-+#define KORINA_CACHE_LINE_SIZE 4
-+#define KORINA_MASTER_LAT 0x3c
-+#define KORINA_HEADER_TYPE 0
-+#define KORINA_BIST 0
-+
-+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
-+ (KORINA_HEADER_TYPE<<16) | \
-+ (KORINA_MASTER_LAT<<8) | \
-+ KORINA_CACHE_LINE_SIZE )
-+
-+#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
-+#define KORINA_BAR1 0x18800001 /* 1 MB IO */
-+#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia
-+ internal Registers */
-+#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
-+
-+#define KORINA_CNFG4 KORINA_BAR0
-+#define KORINA_CNFG5 KORINA_BAR1
-+#define KORINA_CNFG6 KORINA_BAR2
-+#define KORINA_CNFG7 KORINA_BAR3
-+
-+#define KORINA_SUBSYS_VENDOR_ID 0
-+#define KORINA_SUBSYSTEM_ID 0
-+#define KORINA_CNFG8 0
-+#define KORINA_CNFG9 0
-+#define KORINA_CNFG10 0
-+#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
-+ KORINA_SUBSYSTEM_ID)
-+#define KORINA_INT_LINE 1
-+#define KORINA_INT_PIN 1
-+#define KORINA_MIN_GNT 8
-+#define KORINA_MAX_LAT 0x38
-+#define KORINA_CNFG12 0
-+#define KORINA_CNFG13 0
-+#define KORINA_CNFG14 0
-+#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
-+ (KORINA_MIN_GNT<<16) | \
-+ (KORINA_INT_PIN<<8) | \
-+ KORINA_INT_LINE)
-+#define KORINA_RETRY_LIMIT 0x80
-+#define KORINA_TRDY_LIMIT 0x80
-+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
-+ KORINA_TRDY_LIMIT)
-+#define PCI_PBAxC_R 0x0
-+#define PCI_PBAxC_RL 0x1
-+#define PCI_PBAxC_RM 0x2
-+#define SIZE_SHFT 2
-+
-+#ifdef __MIPSEB__
-+#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
-+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_32MB<<SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#else
-+#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
-+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_32MB<<SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#endif
-+
-+#if 0
-+
-+#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
-+ ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
-+ (SIZE_128MB<<SIZE_SHFT))
-+#endif
-+#define KORINA_CNFG17 KORINA_PBA0C
-+#define KORINA_PBA0M 0x0
-+#define KORINA_CNFG18 KORINA_PBA0M
-+
-+#ifdef __MIPSEB__
-+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
-+
-+#endif
-+
-+#define KORINA_CNFG19 KORINA_PBA1C
-+#define KORINA_PBA1M 0x0
-+#define KORINA_CNFG20 KORINA_PBA1M
-+
-+#ifdef __MIPSEB__
-+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
-+
-+#endif
-+#define KORINA_CNFG21 KORINA_PBA2C
-+#define KORINA_PBA2M 0x18000000
-+#define KORINA_CNFG22 KORINA_PBA2M
-+#define KORINA_PBA3C 0
-+#define KORINA_CNFG23 KORINA_PBA3C
-+#define KORINA_PBA3M 0
-+#define KORINA_CNFG24 KORINA_PBA3M
-+
-+
-+
-+#define PCITC_DTIMER_VAL 8
-+#define PCITC_RTIMER_VAL 0x10
-+
-+
-+#endif /* _PCIKORINA_H */
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
---- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,8 @@
-+/* Override the default address space for this arch
-+*/
-+
-+#include <linux/pci_regs.h>
-+
-+//#undef PCI_BASE_ADDRESS_SPACE
-+//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
-+
-diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
---- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/rb.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,69 @@
-+#ifndef __MIPS_RB_H__
-+#define __MIPS_RB_H__
-+#include <linux/genhd.h>
-+
-+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
-+#define DEV0BASE 0x010000
-+#define DEV0MASK 0x010004
-+#define DEV0C 0x010008
-+#define DEV0TC 0x01000C
-+#define DEV1BASE 0x010010
-+#define DEV1MASK 0x010014
-+#define DEV1C 0x010018
-+#define DEV1TC 0x01001C
-+#define DEV2BASE 0x010020
-+#define DEV2MASK 0x010024
-+#define DEV2C 0x010028
-+#define DEV2TC 0x01002C
-+#define DEV3BASE 0x010030
-+#define DEV3MASK 0x010034
-+#define DEV3C 0x010038
-+#define DEV3TC 0x01003C
-+#define BTCS 0x010040
-+#define BTCOMPARE 0x010044
-+#define GPIOFUNC 0x050000
-+#define GPIOCFG 0x050004
-+#define GPIOD 0x050008
-+#define GPIOILEVEL 0x05000C
-+#define GPIOISTAT 0x050010
-+#define GPIONMIEN 0x050014
-+#define IMASK6 0x038038
-+
-+#define LO_WPX (1 << 0)
-+#define LO_ALE (1 << 1)
-+#define LO_CLE (1 << 2)
-+#define LO_CEX (1 << 3)
-+#define LO_FOFF (1 << 5)
-+#define LO_SPICS (1 << 6)
-+#define LO_ULED (1 << 7)
-+
-+typedef enum {
-+ FUNC = 0x00,
-+ CFG = 0x04,
-+ DATA = 0x08,
-+ ILEVEL = 0x0c,
-+ ISTAT = 0x10,
-+ NMIEN = 0x14
-+} gpio_func;
-+
-+extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
-+extern unsigned get434Reg(unsigned regOffs);
-+extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
-+extern void gpio_set(gpio_func func, u32 mask, u32 value);
-+extern u32 gpio_get(gpio_func func);
++extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
++extern unsigned get434Reg(unsigned regOffs);
++extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
++extern void gpio_set(gpio_func func, u32 mask, u32 value);
++extern u32 gpio_get(gpio_func func);
+
+#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
+
+#endif
diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
--- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,126 @@
++++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-12-14 04:09:50.000000000 +0100
+@@ -0,0 +1,122 @@
+/*
+ ***************************************************************************
+ * Definitions for IDT RC323434 CPU.
+#ifndef _RC32434_H_
+#define _RC32434_H_
+
-+#include <linux/config.h>
++#include <linux/autoconf.h>
+#include <linux/delay.h>
+#include <asm/io.h>
-+#include <asm/rc32434/timer.h>
+
+#define RC32434_REG_BASE 0x18000000
+
+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
-+#define timer ((volatile TIM_t) TIM0_VirtualAddress)
+#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
+
++
+#define IDT_CLOCK_MULT 2
+#define MIPS_CPU_TIMER_IRQ 7
+/* Interrupt Controller */
+ return ret;
+}
+
-+extern void cons_putc(char c);
-+extern void cons_puts(char *s);
-+
+#endif /* _RC32434_H_ */
-diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
---- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/rst.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,105 @@
-+#ifndef __IDT_RST_H__
-+#define __IDT_RST_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Reset register definitions.
-+ *
-+ * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020118
-+ * Update :
-+ * $Log: rst.h,v $
-+ * Revision 1.2 2002/06/06 18:34:05 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:24 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ RST0_PhysicalAddress = 0x18000000,
-+ RST_PhysicalAddress = RST0_PhysicalAddress, // Default
-+
-+ RST0_VirtualAddress = 0xb8000000,
-+ RST_VirtualAddress = RST0_VirtualAddress, // Default
-+} ;
-+
-+typedef struct RST_s
-+{
-+ U32 filler [0x0006] ;
-+ U32 sysid ;
-+ U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
-+ U32 reset ;
-+ U32 bcv ;
-+ U32 cea ;
-+} volatile * RST_t ;
-+
-+enum
-+{
-+ SYSID_rev_b = 0,
-+ SYSID_rev_m = 0x000000ff,
-+ SYSID_imp_b = 8,
-+ SYSID_imp_m = 0x000fff00,
-+ SYSID_vendor_b = 20,
-+ SYSID_vendor_m = 0xfff00000,
-+
-+ BCV_pll_b = 0,
-+ BCV_pll_m = 0x0000000f,
-+ BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
-+ BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
-+ BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
-+ BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK.
-+ BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK.
-+ BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK.
-+ BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK.
-+ BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
-+ BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK.
-+ BCV_pll_Res5_v = 0x9,
-+ BCV_pll_Res6_v = 0xa,
-+ BCV_pll_Res7_v = 0xb,
-+ BCV_pll_Res8_v = 0xc,
-+ BCV_pll_Res13_v = 0xd,
-+ BCV_pll_Res14_v = 0xe,
-+ BCV_pll_Res15_v = 0xf,
-+ BCV_clkDiv_b = 4,
-+ BCV_clkDiv_m = 0x00000030,
-+ BCV_clkDiv_Div1_v = 0x0,
-+ BCV_clkDiv_Div2_v = 0x1,
-+ BCV_clkDiv_Div4_v = 0x2,
-+ BCV_clkDiv_Res3_v = 0x3,
-+ BCV_bigEndian_b = 6,
-+ BCV_bigEndian_m = 0x00000040,
-+ BCV_resetFast_b = 7,
-+ BCV_resetFast_m = 0x00000080,
-+ BCV_pciMode_b = 8,
-+ BCV_pciMode_m = 0x00000100,
-+ BCV_pciMode_disabled_v = 0, // PCI is disabled.
-+ BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
-+ BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
-+ BCV_pciMode_external_v = 3, // host, external arbiter.
-+ BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
-+ BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
-+ BCV_pciMode_res6_v = 6,
-+ BCV_pciMode_res7_v = 7,
-+ BCV_watchDisable_b = 11,
-+ BCV_watchDisable_m = 0x00000800,
-+ BCV_pllTest_b = 12,
-+ BCV_pllTest_m = 0x00001000,
-+ BCV_nvramInit_b = 13,
-+ BCV_nvramInit_m = 0x00002000,
-+ BCV_clksyncTstMd_b = 14,
-+ BCV_clksyncTstMd_m = 0x00004000,
-+ BCV_delayBypass_b = 15,
-+ BCV_delayByPass_m = 0x00008000,
-+} ;
-+#endif // __IDT_RST_H__
-diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
---- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/spi.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,100 @@
-+#ifndef __IDT_SPI_H__
-+#define __IDT_SPI_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Serial Peripheral Interface register definitions.
-+ *
-+ * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
-+ *
-+ * Author : ryan.holmQVist@idt.com
-+ * Date : 20011005
-+ * Update :
-+ * $Log: spi.h,v $
-+ * Revision 1.2 2002/06/06 18:34:05 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:25 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ SPI0_PhysicalAddress = 0x18070000,
-+ SPI_PhysicalAddress = SPI0_PhysicalAddress,
-+
-+ SPI0_VirtualAddress = 0xb8070000,
-+ SPI_VirtualAddress = SPI0_VirtualAddress,
-+} ;
-+
-+typedef struct
-+{
-+ U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
-+ U32 spc ; // spi control reg use SPC_
-+ U32 sps ; // spi status reg use SPS_
-+ U32 spd ; // spi data reg use SPD_
-+ U32 siofunc ; // serial IO function use SIOFUNC_
-+ U32 siocfg ; // serial IO config use SIOCFG_
-+ U32 siod; // serial IO data use SIOD_
-+} volatile *SPI_t ;
-+
-+enum
-+{
-+ SPCP_div_b = 0,
-+ SPCP_div_m = 0x000000ff,
-+ SPC_spr_b = 0,
-+ SPC_spr_m = 0x00000003,
-+ SPC_spr_div2_v = 0,
-+ SPC_spr_div4_v = 1,
-+ SPC_spr_div16_v = 2,
-+ SPC_spr_div32_v = 3,
-+ SPC_cpha_b = 2,
-+ SPC_cpha_m = 0x00000004,
-+ SPC_cpol_b = 3,
-+ SPC_cpol_m = 0x00000008,
-+ SPC_mstr_b = 4,
-+ SPC_mstr_m = 0x00000010,
-+ SPC_spe_b = 6,
-+ SPC_spe_m = 0x00000040,
-+ SPC_spie_b = 7,
-+ SPC_spie_m = 0x00000080,
-+
-+ SPS_modf_b = 4,
-+ SPS_modf_m = 0x00000010,
-+ SPS_wcol_b = 6,
-+ SPS_wcol_m = 0x00000040,
-+ SPS_spif_b = 7,
-+ SPS_spif_m = 0x00000070,
-+
-+ SPD_data_b = 0,
-+ SPD_data_m = 0x000000ff,
-+
-+ SIOFUNC_sdo_b = 0,
-+ SIOFUNC_sdo_m = 0x00000001,
-+ SIOFUNC_sdi_b = 1,
-+ SIOFUNC_sdi_m = 0x00000002,
-+ SIOFUNC_sck_b = 2,
-+ SIOFUNC_sck_m = 0x00000004,
-+
-+ SIOCFG_sdo_b = 0,
-+ SIOCFG_sdo_m = 0x00000001,
-+ SIOCFG_sdi_b = 1,
-+ SIOCFG_sdi_m = 0x00000002,
-+ SIOCFG_sck_b = 2,
-+ SIOCFG_sck_m = 0x00000004,
-+
-+ SIOD_sdo_b = 0,
-+ SIOD_sdo_m = 0x00000001,
-+ SIOD_sdi_b = 1,
-+ SIOD_sdi_m = 0x00000002,
-+ SIOD_sck_b = 2,
-+ SIOD_sck_m = 0x00000004,
-+} ;
-+#endif // __IDT_SPI_H__
-diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
---- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/timer.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,91 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for timer registers
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt,neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
-+
-+#ifndef __IDT_TIM_H__
-+#define __IDT_TIM_H__
-+
-+enum
-+{
-+ TIM0_PhysicalAddress = 0x18028000,
-+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
-+
-+ TIM0_VirtualAddress = 0xb8028000,
-+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ TIM_Count = 3,
-+} ;
-+
-+struct TIM_CNTR_s
-+{
-+ u32 count ;
-+ u32 compare ;
-+ u32 ctc ; //use CTC_
-+} ;
-+
-+typedef struct TIM_s
-+{
-+ struct TIM_CNTR_s tim [TIM_Count] ;
-+ u32 rcount ; //use RCOUNT_
-+ u32 rcompare ; //use RCOMPARE_
-+ u32 rtc ; //use RTC_
-+} volatile * TIM_t ;
-+
-+enum
-+{
-+ CTC_en_b = 0,
-+ CTC_en_m = 0x00000001,
-+ CTC_to_b = 1,
-+ CTC_to_m = 0x00000002,
-+
-+ RCOUNT_count_b = 0,
-+ RCOUNT_count_m = 0x0000ffff,
-+ RCOMPARE_compare_b = 0,
-+ RCOMPARE_compare_m = 0x0000ffff,
-+ RTC_ce_b = 0,
-+ RTC_ce_m = 0x00000001,
-+ RTC_to_b = 1,
-+ RTC_to_m = 0x00000002,
-+ RTC_rqe_b = 2,
-+ RTC_rqe_m = 0x00000004,
-+
-+} ;
-+#endif // __IDT_TIM_H__
-+
-diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
---- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/tim.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,78 @@
-+#ifndef __IDT_TIM_H__
-+#define __IDT_TIM_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Timer register definition.
-+ *
-+ * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
-+ *
-+ * Author : ryan.holmQVist@idt.com
-+ * Date : 20011005
-+ * Update :
-+ * $Log: tim.h,v $
-+ * Revision 1.2 2002/06/06 18:34:05 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.1 2002/05/29 17:33:25 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ TIM0_PhysicalAddress = 0x18028000,
-+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
-+
-+ TIM0_VirtualAddress = 0xb8028000,
-+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ TIM_Count = 3,
-+} ;
-+
-+struct TIM_CNTR_s
-+{
-+ U32 count ;
-+ U32 compare ;
-+ U32 ctc ; //use CTC_
-+} ;
-+
-+typedef struct TIM_s
-+{
-+ struct TIM_CNTR_s tim [TIM_Count] ;
-+ U32 rcount ; //use RCOUNT_
-+ U32 rcompare ; //use RCOMPARE_
-+ U32 rtc ; //use RTC_
-+} volatile * TIM_t ;
-+
-+enum
-+{
-+ CTC_en_b = 0,
-+ CTC_en_m = 0x00000001,
-+ CTC_to_b = 1,
-+ CTC_to_m = 0x00000002,
-+
-+ RCOUNT_count_b = 0,
-+ RCOUNT_count_m = 0x0000ffff,
-+ RCOMPARE_compare_b = 0,
-+ RCOMPARE_compare_m = 0x0000ffff,
-+ RTC_ce_b = 0,
-+ RTC_ce_m = 0x00000001,
-+ RTC_to_b = 1,
-+ RTC_to_m = 0x00000002,
-+ RTC_rqe_b = 2,
-+ RTC_rqe_m = 0x00000004,
-+
-+} ;
-+#endif // __IDT_TIM_H__
-+
-diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
---- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/types.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,39 @@
-+#ifndef __IDT_TYPES_H__
-+#define __IDT_TYPES_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Common typedefs used in IDT-generated code.
-+ *
-+ * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020606
-+ * Update :
-+ * $Log: types.h,v $
-+ * Revision 1.1 2002/06/06 16:16:56 astichte
-+ * Added
-+ *
-+ *
-+ ******************************************************************************/
-+
-+typedef unsigned char U8 ;
-+typedef signed char S8 ;
-+
-+typedef unsigned short U16 ;
-+typedef signed short S16 ;
-+
-+typedef unsigned int U32 ;
-+typedef signed int S32 ;
-+
-+typedef unsigned long long U64 ;
-+typedef signed long long S64 ;
-+
-+#ifndef __cplusplus
-+ typedef U32 bool ; // (false == 0), (true is != false)
-+#endif // __cplusplus
-+
-+#endif // __IDT_TYPES_H__
-diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
---- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/uart.h 2006-06-18 17:18:16.000000000 +0200
-@@ -0,0 +1,178 @@
-+#ifndef __IDT_UART_H__
-+#define __IDT_UART_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * UART register definitions.
-+ *
-+ * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020118
-+ * Update :
-+ * $Log: uart.h,v $
-+ * Revision 1.3 2002/06/06 18:34:05 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/04 17:37:52 astichte
-+ * Updated register definitions.
-+ *
-+ * Revision 1.1 2002/05/29 17:33:25 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ UART_PhysicalAddress = 0x18058000,
-+ UART_PhysicalAddress = UART_PhysicalAddress, // Default
-+
-+ UART_VirtualAddress = 0xb8058000,
-+ UART_VirtualAddress = UART_VirtualAddress, // Default
-+} ;
-+
-+/*
-+ * Register definitions are in bytes so we can handle endian problems.
-+ */
-+
-+typedef struct UART_s
-+{
-+ union
-+ {
-+ U32 const uartrb ; // 0x00 - DLAB=0, read.
-+ U32 uartth ; // 0x00 - DLAB=0, write.
-+ U32 uartdll ; // 0x00 - DLAB=1, read/write.
-+ } ;
-+
-+ union
-+ {
-+ U32 uartie ; // 0x04 - DLAB=0, read/write.
-+ U32 uartdlh ; // 0x04 - DLAB=1, read/write.
-+ } ;
-+ union
-+ {
-+ U32 const uartii ; // 0x08 - DLAB=0, read.
-+ U32 uartfc ; // 0x08 - DLAB=0, write.
-+ } ;
-+
-+ U32 uartlc ; // 0x0c
-+ U32 uartmc ; // 0x10
-+ U32 uartls ; // 0x14
-+ U32 uartms ; // 0x18
-+ U32 uarts ; // 0x1c
-+} volatile *UART_t ;
-+
-+// Reset registers.
-+typedef U32 volatile *UARTRR_t ;
-+
-+enum
-+{
-+ UARTIE_rda_b = 0,
-+ UARTIE_rda_m = 0x00000001,
-+ UARTIE_the_b = 1,
-+ UARTIE_the_m = 0x00000002,
-+ UARTIE_rls_b = 2,
-+ UARTIE_rls_m = 0x00000004,
-+ UARTIE_ems_b = 3,
-+ UARTIE_ems_m = 0x00000008,
-+
-+ UARTII_pi_b = 0,
-+ UARTII_pi_m = 0x00000001,
-+ UARTII_iid_b = 1,
-+ UARTII_iid_m = 0x0000000e,
-+ UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
-+ UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
-+ UARTII_iid_rda_v = 2, // Receive data available
-+ UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
-+ UARTII_iid_res4_v = 4, // reserved.
-+ UARTII_iid_res5_v = 5, // reserved.
-+ UARTII_iid_cto_v = 6, // Character timeout.
-+ UARTII_iid_res7_v = 7, // reserved.
-+
-+ UARTFC_en_b = 0,
-+ UARTFC_en_m = 0x00000001,
-+ UARTFC_rr_b = 1,
-+ UARTFC_rr_m = 0x00000002,
-+ UARTFC_tr_b = 2,
-+ UARTFC_tr_m = 0x00000004,
-+ UARTFC_dms_b = 3,
-+ UARTFC_dms_m = 0x00000008,
-+ UARTFC_rt_b = 6,
-+ UARTFC_rt_m = 0x000000c0,
-+ UARTFC_rt_1Byte_v = 0,
-+ UARTFC_rt_4Byte_v = 1,
-+ UARTFC_rt_8Byte_v = 2,
-+ UARTFC_rt_14Byte_v = 3,
-+
-+ UARTLC_wls_b = 0,
-+ UARTLC_wls_m = 0x00000003,
-+ UARTLC_wls_5Bits_v = 0,
-+ UARTLC_wls_6Bits_v = 1,
-+ UARTLC_wls_7Bits_v = 2,
-+ UARTLC_wls_8Bits_v = 3,
-+ UARTLC_stb_b = 2,
-+ UARTLC_stb_m = 0x00000004,
-+ UARTLC_pen_b = 3,
-+ UARTLC_pen_m = 0x00000008,
-+ UARTLC_eps_b = 4,
-+ UARTLC_eps_m = 0x00000010,
-+ UARTLC_sp_b = 5,
-+ UARTLC_sp_m = 0x00000020,
-+ UARTLC_sb_b = 6,
-+ UARTLC_sb_m = 0x00000040,
-+ UARTLC_dlab_b = 7,
-+ UARTLC_dlab_m = 0x00000080,
-+
-+ UARTMC_dtr_b = 0,
-+ UARTMC_dtr_m = 0x00000001,
-+ UARTMC_rts_b = 1,
-+ UARTMC_rts_m = 0x00000002,
-+ UARTMC_o1_b = 2,
-+ UARTMC_o1_m = 0x00000004,
-+ UARTMC_o2_b = 3,
-+ UARTMC_o2_m = 0x00000008,
-+ UARTMC_lp_b = 4,
-+ UARTMC_lp_m = 0x00000010,
-+
-+ UARTLS_dr_b = 0,
-+ UARTLS_dr_m = 0x00000001,
-+ UARTLS_oe_b = 1,
-+ UARTLS_oe_m = 0x00000002,
-+ UARTLS_pe_b = 2,
-+ UARTLS_pe_m = 0x00000004,
-+ UARTLS_fe_b = 3,
-+ UARTLS_fe_m = 0x00000008,
-+ UARTLS_bi_b = 4,
-+ UARTLS_bi_m = 0x00000010,
-+ UARTLS_thr_b = 5,
-+ UARTLS_thr_m = 0x00000020,
-+ UARTLS_te_b = 6,
-+ UARTLS_te_m = 0x00000040,
-+ UARTLS_rfe_b = 7,
-+ UARTLS_rfe_m = 0x00000080,
-+
-+ UARTMS_dcts_b = 0,
-+ UARTMS_dcts_m = 0x00000001,
-+ UARTMS_ddsr_b = 1,
-+ UARTMS_ddsr_m = 0x00000002,
-+ UARTMS_teri_b = 2,
-+ UARTMS_teri_m = 0x00000004,
-+ UARTMS_ddcd_b = 3,
-+ UARTMS_ddcd_m = 0x00000008,
-+ UARTMS_cts_b = 4,
-+ UARTMS_cts_m = 0x00000010,
-+ UARTMS_dsr_b = 5,
-+ UARTMS_dsr_m = 0x00000020,
-+ UARTMS_ri_b = 6,
-+ UARTMS_ri_m = 0x00000040,
-+ UARTMS_dcd_b = 7,
-+ UARTMS_dcd_m = 0x00000080,
-+} ;
-+
-+#endif // __IDT_UART_H__
+
projects / openwrt.git / blobdiff