#include <asm/io.h>
#include "rt2x00.h"
+#include "rt2x00lib.h"
#include "rt2x00pci.h"
#include "rt2500pci.h"
u32 rf2 = value;
u32 rf3 = rt2x00dev->rf3;
u32 rf4 = rt2x00dev->rf4;
+ u8 r70;
if (rt2x00_rf(&rt2x00dev->chip, RF2525) ||
rt2x00_rf(&rt2x00dev->chip, RF2525E))
/*
* Channel 14 requires the Japan filter bit to be set.
*/
- rt2500pci_bbp_write(rt2x00dev, 70, (channel == 14) ? 0x4e : 0x46);
+ r70 = 0x46;
+ rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
+ rt2500pci_bbp_write(rt2x00dev, 70, r70);
msleep(1);
/*
* Link tuning
*/
-static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, int rssi)
+static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
{
+ int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
u32 reg;
u8 r17;
*/
if (rssi < -80 && rt2x00dev->link.count > 20) {
if (r17 >= 0x41) {
- r17 = rt2x00dev->link.curr_noise;
+ r17 = rt2x00dev->rx_status.noise;
rt2500pci_bbp_write(rt2x00dev, 17, r17);
}
return;
* to the dynamic tuning range.
*/
if (r17 >= 0x41) {
- rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.curr_noise);
+ rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->rx_status.noise);
return;
}
if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
- rt2x00dev->link.curr_noise = r17;
+ rt2x00dev->rx_status.noise = r17;
} else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
rt2500pci_bbp_write(rt2x00dev, 17, --r17);
- rt2x00dev->link.curr_noise = r17;
+ rt2x00dev->rx_status.noise = r17;
}
}
return -EBUSY;
rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
- rt2x00pci_register_write(rt2x00dev, PCICSR, 0x000003b8);
+
+ rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
+ rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
+ rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
+ rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
+ rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
+ rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
+ rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
+ rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
+ rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}
-static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
+static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled)
{
u32 reg;
+ /*
+ * When interrupts are being enabled, the interrupt registers
+ * should clear the register to assure a clean state.
+ */
+ if (enabled) {
+ rt2x00pci_register_read(rt2x00dev, CSR7, ®);
+ rt2x00pci_register_write(rt2x00dev, CSR7, reg);
+ }
+
+ /*
+ * Only toggle the interrupts bits we are going to use.
+ * Non-checked interrupt bits are disabled by default.
+ */
+ rt2x00pci_register_read(rt2x00dev, CSR8, ®);
+ rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, !enabled);
+ rt2x00_set_field32(®, CSR8_TXDONE_TXRING, !enabled);
+ rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, !enabled);
+ rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, !enabled);
+ rt2x00_set_field32(®, CSR8_RXDONE, !enabled);
+ rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+}
+
+static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
+{
/*
* Initialize all registers.
*/
return -EIO;
}
- /*
- * Clear interrupts.
- */
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
/*
* Enable interrupts.
*/
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
- rt2x00_set_field32(®, CSR8_RXDONE, 0);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+ rt2500pci_toggle_irq(rt2x00dev, 1);
/*
* Enable LED
/*
* Disable interrupts.
*/
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 1);
- rt2x00_set_field32(®, CSR8_RXDONE, 1);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+ rt2500pci_toggle_irq(rt2x00dev, 0);
}
static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
}
/*
- * Interrupt functions.
+ * RX control handlers
*/
-static void rt2500pci_rxdone(struct rt2x00_dev *rt2x00dev)
+static int rt2500pci_fill_rxdone(struct data_entry *entry,
+ int *signal, int *rssi, int *ofdm)
{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_entry *entry;
- struct data_desc *rxd;
+ struct data_desc *rxd = entry->priv;
u32 word0;
u32 word2;
- int signal;
- int rssi;
- int ofdm;
- u16 size;
-
- while (1) {
- entry = rt2x00_get_data_entry(ring);
- rxd = entry->priv;
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 2, &word2);
-
- if (rt2x00_get_field32(word0, RXD_W0_OWNER_NIC))
- break;
- /*
- * TODO: Don't we need to keep statistics
- * updated about events like CRC and physical errors?
- */
- if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
- rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
- goto skip_entry;
+ rt2x00_desc_read(rxd, 0, &word0);
+ rt2x00_desc_read(rxd, 2, &word2);
- /*
- * Obtain the status about this packet.
- */
- size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
- signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
- rssi = rt2x00_get_field32(word2, RXD_W2_RSSI);
- ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
-
- /*
- * Send the packet to upper layer.
- */
- rt2x00lib_rxdone(entry, entry->data_addr, size,
- signal, rssi, ofdm);
+ /*
+ * TODO: Don't we need to keep statistics
+ * updated about these errors?
+ */
+ if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
+ rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
+ return -EINVAL;
-skip_entry:
- if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
- rt2x00_set_field32(&word0, RXD_W0_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word0);
- }
+ *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
+ *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
+ entry->ring->rt2x00dev->rssi_offset;
+ *ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
- rt2x00_ring_index_inc(ring);
- }
+ return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
}
+/*
+ * Interrupt functions.
+ */
static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
{
struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
* 2 - Rx ring done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_RXDONE))
- rt2500pci_rxdone(rt2x00dev);
+ rt2x00pci_rxdone(rt2x00dev);
/*
* 3 - Atim ring transmit done interrupt.
struct eeprom_93cx6 eeprom;
u32 reg;
u16 word;
+ u8 *mac;
/*
* Allocate the eeprom memory, check the eeprom width
/*
* Start validation of the data that has been read.
*/
+ mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
+ if (!is_valid_ether_addr(mac)) {
+ random_ether_addr(mac);
+ EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
+ }
+
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
if (word == 0xffff) {
rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
if (word == 0xffff) {
rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
- MAX_RX_SSI);
+ DEFAULT_RSSI_OFFSET);
rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
}
* Read the RSSI <-> dBm offset information.
*/
rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
- rt2x00dev->hw->max_rssi =
+ rt2x00dev->rssi_offset =
rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
return 0;
IEEE80211_HW_WEP_INCLUDE_IV |
IEEE80211_HW_DATA_NULLFUNC_ACK |
IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
- IEEE80211_HW_MONITOR_DURING_OPER;
+ IEEE80211_HW_MONITOR_DURING_OPER |
+ IEEE80211_HW_NO_PROBE_FILTERING;
rt2x00dev->hw->extra_tx_headroom = 0;
rt2x00dev->hw->max_rssi = MAX_RX_SSI;
rt2x00dev->hw->max_noise = MAX_RX_NOISE;
rt2x00dev->hw->queues = 2;
- /*
- * This device supports ATIM
- */
- __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
+ SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
+ SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
+ rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
/*
* Set device specific, but channel independent RF values.
/*
* Initialize hw_mode information.
*/
- spec->mac_addr = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
spec->num_modes = 2;
spec->num_rates = 12;
spec->num_channels = 14;
*/
rt2500pci_init_hw_mode(rt2x00dev);
+ /*
+ * This device supports ATIM
+ */
+ __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
+
return 0;
}
static const struct ieee80211_ops rt2500pci_mac80211_ops = {
.tx = rt2x00lib_tx,
.reset = rt2x00lib_reset,
- .open = rt2x00lib_open,
- .stop = rt2x00lib_stop,
.add_interface = rt2x00lib_add_interface,
.remove_interface = rt2x00lib_remove_interface,
.config = rt2x00lib_config,
.write_tx_desc = rt2500pci_write_tx_desc,
.write_tx_data = rt2x00pci_write_tx_data,
.kick_tx_queue = rt2500pci_kick_tx_queue,
+ .fill_rxdone = rt2500pci_fill_rxdone,
.config_type = rt2500pci_config_type,
.config_phymode = rt2500pci_config_phymode,
.config_channel = rt2500pci_config_channel,
static int __init rt2500pci_init(void)
{
- printk(KERN_INFO "Loading module: %s - %s by %s.\n",
- DRV_NAME, DRV_VERSION, DRV_PROJECT);
return pci_register_driver(&rt2500pci_driver);
}
static void __exit rt2500pci_exit(void)
{
- printk(KERN_INFO "Unloading module: %s.\n", DRV_NAME);
pci_unregister_driver(&rt2500pci_driver);
}
projects / openwrt.git / blobdiff