uml: this patch went upstream

[openwrt.git] / package / uboot-ifxmips / files / board / ifx / danube / ddr_settings_r111.h

diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
index 385f7e4..fd15597 100644 (file)
--- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
+++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */\r
-#define MC_DC21_VALUE  0x1200\r
-#define MC_DC22_VALUE  0x1212\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE  0x1200
+#define MC_DC22_VALUE  0x1212
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0