ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
- DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
| MAC_CFG1_STX)
+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
static void ag71xx_hw_init(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
desc = &ring->descs[i];
spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
spin_unlock_irqrestore(&ag->lock, flags);
if (!ag71xx_desc_empty(desc))
DBG("%s: processing TX ring\n", ag->dev->name);
#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
#endif
sent = 0;
#ifndef AG71XX_NAPI_TX
spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
spin_unlock_irqrestore(&ag->lock, flags);
#endif
int done;
#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
ag71xx_tx_packets(ag);
#endif