+static inline void sw_int_mask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t |= mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_unmask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t &= ~mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_ack(u32 mask)
+{
+ sw_write_reg(SWITCH_REG_INT_STATUS, mask);
+}
+
+static inline u32 sw_int_status(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
+ return t;
+}
+
+static inline u32 desc_get_srcport(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
+}
+
+static inline u32 desc_get_pktlen(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
+}
+
+static inline int desc_ipcsum_fail(struct dma_desc *desc)
+{
+ return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
+{
+ u32 t;
+
+ SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
+
+ t = desc->buf1;
+ SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
+ t & DESC_ADDR_MASK,
+ desc->buflen,
+ (t & DESC_OWN) ? "SWITCH" : "CPU",
+ (t & DESC_EOR) ? " RE" : "");
+
+ t = desc->buf2;
+ SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
+ t & DESC_ADDR_MASK,
+ (t & DESC_BUF2_EN) ? " EN" : "");
+
+ t = desc->misc;
+ if (tx)
+ SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
+ (t & DESC_CSUM) ? " CSUM" : "",
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
+ t & DESC_VLAN_MASK);
+ else
+ SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
+ t,
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
+ (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
+ (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
+ (t & DESC_VLAN_TAG) ? " VLAN" : "",
+ (t & DESC_TYPE_MASK));
+}
+
+static void sw_dump_intr_mask(char *label, u32 mask)
+{
+ SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ label, mask,
+ (mask & SWITCH_INT_SHD) ? " SHD" : "",
+ (mask & SWITCH_INT_SLD) ? " SLD" : "",
+ (mask & SWITCH_INT_RHD) ? " RHD" : "",
+ (mask & SWITCH_INT_RLD) ? " RLD" : "",
+ (mask & SWITCH_INT_HDF) ? " HDF" : "",
+ (mask & SWITCH_INT_LDF) ? " LDF" : "",
+ (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
+ (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
+ (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
+ (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
+ (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
+ (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
+ (mask & SWITCH_INT_GQF) ? " GQF" : "",
+ (mask & SWITCH_INT_MD) ? " MD" : "",
+ (mask & SWITCH_INT_BCS) ? " BCS" : "",
+ (mask & SWITCH_INT_PSC) ? " PSC" : "",
+ (mask & SWITCH_INT_ID) ? " ID" : "",
+ (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
+ (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
+ (mask & SWITCH_INT_RDE) ? " RDE" : "",
+ (mask & SWITCH_INT_SDE) ? " SDE" : "",
+ (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
+}
+
+static void sw_dump_regs(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_PHY_STATUS);
+ SW_DBG("phy_status: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ SW_DBG("cpup_conf: %08X%s%s%s\n", t,
+ (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
+ (t & CPUP_CONF_CRCP) ? " CRCP" : "",
+ (t & CPUP_CONF_BTM) ? " BTM" : "");
+
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ SW_DBG("port_conf0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF1);
+ SW_DBG("port_conf1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF2);
+ SW_DBG("port_conf2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_VLAN_G1);
+ SW_DBG("vlan g1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_VLAN_G2);
+ SW_DBG("vlan g2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_BW_CNTL0);
+ SW_DBG("bw_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_BW_CNTL1);
+ SW_DBG("bw_cntl1: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
+ SW_DBG("phy_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
+ SW_DBG("phy_cntl1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
+ SW_DBG("phy_cntl2: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
+ SW_DBG("phy_cntl3: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
+ SW_DBG("phy_cntl4: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ sw_dump_intr_mask("int_status: ", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ sw_dump_intr_mask("int_mask: ", t);
+
+ t = sw_read_reg(SWITCH_REG_SHDA);
+ SW_DBG("shda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_SLDA);
+ SW_DBG("slda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RHDA);
+ SW_DBG("rhda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RLDA);
+ SW_DBG("rlda: %08X\n", t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static inline void adm5120_rx_dma_update(struct dma_desc *desc,
projects / openwrt.git / blobdiff