++ ctlhi = block_size >> req->width;
++ ctllo = ((req->direction << 20)
++ // | (1 << 14) | (1 << 11) // source/dest burst trans len
++ | (req->width << 4) | (req->width << 1)
++ | (1 << 0)); // interrupt enable
++
++ if (nr_blocks == 1) {
++ /* Only one block: No need to use block chaining */
++ if (direction == DMA_TO_DEVICE) {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->sg->dma_address);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->data_reg);
++ ctllo |= 2 << 7; // no dst increment
++ } else {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->data_reg);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->sg->dma_address);
++ ctllo |= 2 << 9; // no src increment
++ }
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
++ dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
++ pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
++ } else {
++ struct dw_dma_lli *lli, *lli_prev = NULL;
++ int j = 0, offset = 0;
++
++ ret = -ENOMEM;
++ chan->block = allocate_blocks(dmac, nr_blocks);
++ if (!chan->block)
++ goto out_unclaim_channel;
++
++ if (direction == DMA_TO_DEVICE)
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
++ else
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
++
++ /*
++ * Map scatterlist items to blocks. One scatterlist
++ * item may need more than one block for the reasons
++ * mentioned above.
++ */
++ for (i = 0; i < nr_blocks; i++) {
++ lli = chan->block[i].lli_vaddr;
++ if (lli_prev) {
++ lli_prev->llp = chan->block[i].lli_dma_addr;
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
++ }
++ lli->llp = 0;
++ lli->ctllo = ctllo;
++ lli->ctlhi = ctlhi;
++ if (direction == DMA_TO_DEVICE) {
++ lli->sar = req->sg[j].dma_address + offset;
++ lli->dar = req->data_reg;
++ } else {
++ lli->sar = req->data_reg;
++ lli->dar = req->sg[j].dma_address + offset;
++ }
++ lli_prev = lli;
++
++ offset += block_size;
++ if (offset > req->sg[j].length) {
++ j++;
++ offset = 0;
++ }
++ }
++
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
++
++ /*
++ * SAR, DAR and CTL are initialized from the LLI. We
++ * only have to enable the LLI bits in CTL.
++ */
++ dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
++ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
++ chan->block[0].lli_dma_addr);
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
++ }
++
++ set_channel_bit(dmac, MASK_XFER, req->req.channel);
++ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
++ if (req->req.block_complete)
++ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++ else
++ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++
++ return 0;
++
++out_unclaim_channel:
++ chan->state = CH_STATE_ALLOCATED;
++ return ret;
++}
++
++static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
++ struct dma_request_cyclic *req)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long ctlhi, ctllo, cfghi, cfglo;
++ unsigned long block_size;
++ int ret, i, direction;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dmac->lock, flags);
++
++ block_size = (req->buffer_size/req->periods) >> req->width;
++
++ ret = -EINVAL;
++ if (req->req.channel >= DMAC_NR_CHANNELS
++ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
++ || (req->periods == 0)
++ || block_size > DMAC_MAX_BLOCKSIZE) {
++ spin_unlock_irqrestore(&dmac->lock, flags);
++ return -EINVAL;
++ }
++
++ chan = &dmac->channel[req->req.channel];
++ chan->state = CH_STATE_BUSY;
++ chan->is_cyclic = 1;
++ chan->req_cyclic = req;
++
++ /*
++ * We have marked the channel as busy, so no need to keep the
++ * lock as long as we only touch the channel-specific
++ * registers
++ */
++ spin_unlock_irqrestore(&dmac->lock, flags);
++
++ /*
++ Setup
++ */
++ BUG_ON(req->buffer_size % req->periods);
++ /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
++
++ chan->nr_blocks = req->periods;
++
++ ret = -EINVAL;
++ cfglo = cfghi = 0;
++ switch (req->direction) {
++ case DMA_DIR_MEM_TO_PERIPH:
++ direction = DMA_TO_DEVICE;
++ cfghi = req->periph_id << (43 - 32);
++ break;
++
++ case DMA_DIR_PERIPH_TO_MEM:
++ direction = DMA_FROM_DEVICE;
++ cfghi = req->periph_id << (39 - 32);
++ break;
++ default:
++ goto out_unclaim_channel;
++ }
++
++ chan->direction = direction;
++
++ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
++ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
++
++ ctlhi = block_size;
++ ctllo = ((req->direction << 20)
++ | (req->width << 4) | (req->width << 1)
++ | (1 << 0)); // interrupt enable
++
++ {
++ struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
++
++ ret = -ENOMEM;
++ chan->block = allocate_blocks(dmac, req->periods);
++ if (!chan->block)
++ goto out_unclaim_channel;
++
++ if (direction == DMA_TO_DEVICE)
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
++ else
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
++
++ /*
++ * Set up a linked list items where each period gets
++ * an item. The linked list item for the last period
++ * points back to the star of the buffer making a
++ * cyclic buffer.
++ */
++ for (i = 0; i < req->periods; i++) {
++ lli = chan->block[i].lli_vaddr;
++ if (lli_prev) {
++ lli_prev->llp = chan->block[i].lli_dma_addr;
++ /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);*/
++ }
++ lli->llp = 0;
++ lli->ctllo = ctllo;
++ lli->ctlhi = ctlhi;
++ if (direction == DMA_TO_DEVICE) {
++ lli->sar = req->buffer_start + i*(block_size << req->width);
++ lli->dar = req->data_reg;
++ } else {
++ lli->sar = req->data_reg;
++ lli->dar = req->buffer_start + i*(block_size << req->width);
++ }
++ lli_prev = lli;
++ }
++ lli->llp = chan->block[0].lli_dma_addr;
++
++ /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi); */
++
++ /*
++ * SAR, DAR and CTL are initialized from the LLI. We
++ * only have to enable the LLI bits in CTL.
++ */
++ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
++ chan->block[0].lli_dma_addr);
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
++ }
++
++ clear_channel_bit(dmac, MASK_XFER, req->req.channel);
++ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
++ if (req->req.block_complete)
++ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++ else
++ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++
++ return 0;
++
++out_unclaim_channel:
++ chan->state = CH_STATE_ALLOCATED;
++ return ret;
++}
++
++static int dmac_start_request(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ set_channel_bit(dmac, CH_EN, channel);
++
++ return 0;
++}
++
++static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ dma_addr_t current_pos;
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ chan = &dmac->channel[channel];
++
++ switch (chan->direction) {
++ case DMA_TO_DEVICE:
++ current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
++ break;
++ case DMA_FROM_DEVICE:
++ current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
++ break;
++ default:
++ return 0;
++ }
++
++
++ if (!current_pos) {
++ if (chan->is_cyclic) {
++ current_pos = chan->req_cyclic->buffer_start;
++ } else {
++ current_pos = chan->req_sg->sg->dma_address;
++ }
++ }
++
++ return current_pos;
++}
++
++
++static int dmac_stop_request(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ chan = &dmac->channel[channel];
++ pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
++ chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
++ dmac_chan_readl_lo(dmac, channel, DAR),
++ dmac_chan_readl_lo(dmac, channel, LLP),
++ dmac_chan_readl_hi(dmac, channel, CTL),
++ dmac_chan_readl_lo(dmac, channel, CTL));
++
++ if (chan->state == CH_STATE_BUSY) {
++ clear_channel_bit(dmac, CH_EN, channel);
++ cleanup_channel(dmac, &dmac->channel[channel]);
++ }
++
++ return 0;
++}
++
++
++static void dmac_block_complete(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_BLOCK);
++
++ while (status) {
++ struct dma_request *req;
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ if (chan->is_cyclic) {
++ BUG_ON(!chan->req_cyclic
++ || !chan->req_cyclic->req.block_complete);
++ req = &chan->req_cyclic->req;
++ } else {
++ BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
++ req = &chan->req_sg->req;
++ }
++ dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
++ req->block_complete(req);
++ status = dmac_readl_lo(dmac, STATUS_BLOCK);
++ }
++}
++
++static void dmac_xfer_complete(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ struct dma_request *req;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++
++ while (status) {
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
++
++ req = &chan->req_sg->req;
++ BUG_ON(!req);
++ cleanup_channel(dmac, chan);
++ if (req->xfer_complete)
++ req->xfer_complete(req);
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++ }
++}
++
++static void dmac_error(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_ERROR);
++
++ while (status) {
++ struct dma_request *req;
++
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
++ clear_channel_bit(dmac, CH_EN, chanid);
++
++ if (chan->is_cyclic) {
++ BUG_ON(!chan->req_cyclic);
++ req = &chan->req_cyclic->req;
++ } else {
++ BUG_ON(!chan->req_sg);
++ req = &chan->req_sg->req;
++ }
++
++ cleanup_channel(dmac, chan);
++ if (req->error)
++ req->error(req);
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++ }
++}
++
++static irqreturn_t dmac_interrupt(int irq, void *dev_id)
++{
++ struct dw_dma_controller *dmac = dev_id;
++ unsigned long status;
++ int ret = IRQ_NONE;
++
++ spin_lock(&dmac->lock);
++
++ status = dmac_readl_lo(dmac, STATUS_INT);
++
++ while (status) {
++ ret = IRQ_HANDLED;
++ if (status & 0x10)
++ dmac_error(dmac);
++ if (status & 0x02)
++ dmac_block_complete(dmac);
++ if (status & 0x01)
++ dmac_xfer_complete(dmac);
++
++ status = dmac_readl_lo(dmac, STATUS_INT);
++ }
++
++ spin_unlock(&dmac->lock);
++ return ret;
++}
++
++static int __devinit dmac_probe(struct platform_device *pdev)
++{
++ struct dw_dma_controller *dmac;
++ struct resource *regs;
++ int ret;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++
++ dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
++ if (!dmac)
++ return -ENOMEM;
++ memset(dmac, 0, sizeof(*dmac));
++
++ dmac->hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(dmac->hclk)) {
++ ret = PTR_ERR(dmac->hclk);
++ goto out_free_dmac;
++ }
++ clk_enable(dmac->hclk);
++
++ ret = -ENOMEM;
++ dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
++ sizeof(struct dw_dma_lli), 4, 0);
++ if (!dmac->lli_pool)
++ goto out_disable_clk;
++
++ spin_lock_init(&dmac->lock);
++ dmac->dma.dev = &pdev->dev;
++ dmac->dma.alloc_channel = dmac_alloc_channel;
++ dmac->dma.release_channel = dmac_release_channel;
++ dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
++ dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
++ dmac->dma.start_request = dmac_start_request;
++ dmac->dma.stop_request = dmac_stop_request;
++ dmac->dma.get_current_pos = dmac_get_current_pos;
++
++ dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!dmac->regs)
++ goto out_free_pool;
++
++ ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
++ IRQF_SAMPLE_RANDOM, pdev->name, dmac);
++ if (ret)
++ goto out_unmap_regs;
++
++ /* Enable the DMA controller */
++ dmac_writel_lo(dmac, CFG, 1);
++
++ register_dma_controller(&dmac->dma);
++
++ printk(KERN_INFO
++ "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
++ dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
++
++ return 0;
++
++out_unmap_regs:
++ iounmap(dmac->regs);
++out_free_pool:
++ dma_pool_destroy(dmac->lli_pool);
++out_disable_clk:
++ clk_disable(dmac->hclk);
++ clk_put(dmac->hclk);
++out_free_dmac:
++ kfree(dmac);
++ return ret;
++}
++
++static struct platform_driver dmac_driver = {
++ .probe = dmac_probe,
++ .driver = {
++ .name = "dmaca",
++ },
++};
++
++static int __init dmac_init(void)
++{
++ return platform_driver_register(&dmac_driver);
++}
++subsys_initcall(dmac_init);
++
++static void __exit dmac_exit(void)
++{
++ platform_driver_unregister(&dmac_driver);
++}
++module_exit(dmac_exit);
++
++MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_LICENSE("GPL");
+diff --git a/arch/avr32/drivers/dw-dmac.h b/arch/avr32/drivers/dw-dmac.h
+new file mode 100644
+index 0000000..1f67921
+--- /dev/null
++++ b/arch/avr32/drivers/dw-dmac.h
+@@ -0,0 +1,42 @@
++/*
++ * Driver for the Synopsys DesignWare DMA Controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __AVR32_DW_DMAC_H__
++#define __AVR32_DW_DMAC_H__
++
++#define DW_DMAC_CFG 0x398
++#define DW_DMAC_CH_EN 0x3a0
++
++#define DW_DMAC_STATUS_XFER 0x2e8
++#define DW_DMAC_STATUS_BLOCK 0x2f0
++#define DW_DMAC_STATUS_ERROR 0x308
++
++#define DW_DMAC_MASK_XFER 0x310
++#define DW_DMAC_MASK_BLOCK 0x318
++#define DW_DMAC_MASK_ERROR 0x330
++
++#define DW_DMAC_CLEAR_XFER 0x338
++#define DW_DMAC_CLEAR_BLOCK 0x340
++#define DW_DMAC_CLEAR_ERROR 0x358
++
++#define DW_DMAC_STATUS_INT 0x360
++
++#define DW_DMAC_CHAN_SAR 0x000
++#define DW_DMAC_CHAN_DAR 0x008
++#define DW_DMAC_CHAN_LLP 0x010
++#define DW_DMAC_CHAN_CTL 0x018
++#define DW_DMAC_CHAN_SSTAT 0x020
++#define DW_DMAC_CHAN_DSTAT 0x028
++#define DW_DMAC_CHAN_SSTATAR 0x030
++#define DW_DMAC_CHAN_DSTATAR 0x038
++#define DW_DMAC_CHAN_CFG 0x040
++#define DW_DMAC_CHAN_SGR 0x048
++#define DW_DMAC_CHAN_DSR 0x050
++
++#endif /* __AVR32_DW_DMAC_H__ */
+diff --git a/arch/avr32/kernel/Makefile b/arch/avr32/kernel/Makefile
+index 2d6d48f..88226b6 100644
+--- a/arch/avr32/kernel/Makefile
++++ b/arch/avr32/kernel/Makefile
+@@ -6,9 +6,11 @@ extra-y := head.o vmlinux.lds
+
+ obj-$(CONFIG_SUBARCH_AVR32B) += entry-avr32b.o
+ obj-y += syscall_table.o syscall-stubs.o irq.o
+-obj-y += setup.o traps.o semaphore.o ptrace.o
++obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
+ obj-y += signal.o sys_avr32.o process.o time.o
+ obj-y += init_task.o switch_to.o cpu.o
++obj-y += dma-controller.o
+ obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
+ obj-$(CONFIG_KPROBES) += kprobes.o
+ obj-$(CONFIG_STACKTRACE) += stacktrace.o
++obj-$(CONFIG_NMI_DEBUGGING) += nmi_debug.o
+diff --git a/arch/avr32/kernel/cpu.c b/arch/avr32/kernel/cpu.c
+index 2714cf6..b8409ca 100644
+--- a/arch/avr32/kernel/cpu.c
++++ b/arch/avr32/kernel/cpu.c
+@@ -13,6 +13,7 @@
+ #include <linux/percpu.h>
+ #include <linux/param.h>
+ #include <linux/errno.h>
++#include <linux/clk.h>
+
+ #include <asm/setup.h>
+ #include <asm/sysreg.h>
+@@ -187,9 +188,20 @@ static int __init topology_init(void)
+
+ subsys_initcall(topology_init);
+
++struct chip_id_map {
++ u16 mid;
++ u16 pn;
++ const char *name;
++};
++
++static const struct chip_id_map chip_names[] = {
++ { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
++};
++#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
++
+ static const char *cpu_names[] = {
+ "Morgan",
+- "AP7000",
++ "AP7",
+ };
+ #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
+
+@@ -206,12 +218,32 @@ static const char *mmu_types[] = {
+ "MPU"
+ };
+
++static const char *cpu_feature_flags[] = {
++ "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
++};
++
++static const char *get_chip_name(struct avr32_cpuinfo *cpu)
++{
++ unsigned int i;
++ unsigned int mid = avr32_get_manufacturer_id(cpu);
++ unsigned int pn = avr32_get_product_number(cpu);
++
++ for (i = 0; i < NR_CHIP_NAMES; i++) {
++ if (chip_names[i].mid == mid && chip_names[i].pn == pn)
++ return chip_names[i].name;
++ }
++
++ return "(unknown)";
++}
++
+ void __init setup_processor(void)
+ {
+ unsigned long config0, config1;
+ unsigned long features;
+ unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
++ unsigned device_id;
+ unsigned tmp;
++ unsigned i;
+
+ config0 = sysreg_read(CONFIG0);
+ config1 = sysreg_read(CONFIG1);
+@@ -221,11 +253,14 @@ void __init setup_processor(void)
+ arch_rev = SYSREG_BFEXT(AR, config0);
+ mmu_type = SYSREG_BFEXT(MMUT, config0);
+
++ device_id = ocd_read(DID);
++
+ boot_cpu_data.arch_type = arch_id;
+ boot_cpu_data.cpu_type = cpu_id;
+ boot_cpu_data.arch_revision = arch_rev;
+ boot_cpu_data.cpu_revision = cpu_rev;
+ boot_cpu_data.tlb_config = mmu_type;
++ boot_cpu_data.device_id = device_id;
+
+ tmp = SYSREG_BFEXT(ILSZ, config1);
+ if (tmp) {
+@@ -247,41 +282,34 @@ void __init setup_processor(void)
+ return;
+ }
+
+- printk ("CPU: %s [%02x] revision %d (%s revision %d)\n",
++ printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
++ avr32_get_chip_revision(&boot_cpu_data) + 'A');
++ printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
+ cpu_names[cpu_id], cpu_id, cpu_rev,
+ arch_names[arch_id], arch_rev);
+ printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
+
+ printk ("CPU: features:");
+ features = 0;
+- if (config0 & SYSREG_BIT(CONFIG0_R)) {
++ if (config0 & SYSREG_BIT(CONFIG0_R))
+ features |= AVR32_FEATURE_RMW;
+- printk(" rmw");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_D)) {
++ if (config0 & SYSREG_BIT(CONFIG0_D))
+ features |= AVR32_FEATURE_DSP;
+- printk(" dsp");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_S)) {
++ if (config0 & SYSREG_BIT(CONFIG0_S))
+ features |= AVR32_FEATURE_SIMD;
+- printk(" simd");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_O)) {
++ if (config0 & SYSREG_BIT(CONFIG0_O))
+ features |= AVR32_FEATURE_OCD;
+- printk(" ocd");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_P)) {
++ if (config0 & SYSREG_BIT(CONFIG0_P))
+ features |= AVR32_FEATURE_PCTR;
+- printk(" perfctr");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_J)) {
++ if (config0 & SYSREG_BIT(CONFIG0_J))
+ features |= AVR32_FEATURE_JAVA;
+- printk(" java");
+- }
+- if (config0 & SYSREG_BIT(CONFIG0_F)) {
++ if (config0 & SYSREG_BIT(CONFIG0_F))
+ features |= AVR32_FEATURE_FPU;
+- printk(" fpu");
+- }
++
++ for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
++ if (features & (1 << i))
++ printk(" %s", cpu_feature_flags[i]);
++
+ printk("\n");
+ boot_cpu_data.features = features;
+ }
+@@ -291,6 +319,8 @@ static int c_show(struct seq_file *m, void *v)
+ {
+ unsigned int icache_size, dcache_size;
+ unsigned int cpu = smp_processor_id();
++ unsigned int freq;
++ unsigned int i;
+
+ icache_size = boot_cpu_data.icache.ways *
+ boot_cpu_data.icache.sets *
+@@ -301,15 +331,21 @@ static int c_show(struct seq_file *m, void *v)
+
+ seq_printf(m, "processor\t: %d\n", cpu);
+
++ seq_printf(m, "chip type\t: %s revision %c\n",
++ get_chip_name(&boot_cpu_data),
++ avr32_get_chip_revision(&boot_cpu_data) + 'A');
+ if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
+- seq_printf(m, "cpu family\t: %s revision %d\n",
++ seq_printf(m, "cpu arch\t: %s revision %d\n",
+ arch_names[boot_cpu_data.arch_type],
+ boot_cpu_data.arch_revision);
+ if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
+- seq_printf(m, "cpu type\t: %s revision %d\n",
++ seq_printf(m, "cpu core\t: %s revision %d\n",
+ cpu_names[boot_cpu_data.cpu_type],
+ boot_cpu_data.cpu_revision);
+
++ freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
++ seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
++
+ seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
+ icache_size >> 10,
+ boot_cpu_data.icache.ways,
+@@ -320,7 +356,13 @@ static int c_show(struct seq_file *m, void *v)
+ boot_cpu_data.dcache.ways,
+ boot_cpu_data.dcache.sets,
+ boot_cpu_data.dcache.linesz);
+- seq_printf(m, "bogomips\t: %lu.%02lu\n",
++
++ seq_printf(m, "features\t:");
++ for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
++ if (boot_cpu_data.features & (1 << i))
++ seq_printf(m, " %s", cpu_feature_flags[i]);
++
++ seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
+ boot_cpu_data.loops_per_jiffy / (500000/HZ),
+ (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
+
+@@ -343,7 +385,7 @@ static void c_stop(struct seq_file *m, void *v)
+
+ }
+
+-struct seq_operations cpuinfo_op = {
++const struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+diff --git a/arch/avr32/kernel/dma-controller.c b/arch/avr32/kernel/dma-controller.c
+new file mode 100644
+index 0000000..fb654b3
+--- /dev/null
++++ b/arch/avr32/kernel/dma-controller.c
+@@ -0,0 +1,34 @@
++/*
++ * Preliminary DMA controller framework for AVR32
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <asm/dma-controller.h>
++
++static LIST_HEAD(controllers);
++
++int register_dma_controller(struct dma_controller *dmac)
++{
++ static int next_id;
++
++ dmac->id = next_id++;
++ list_add_tail(&dmac->list, &controllers);
++
++ return 0;
++}
++EXPORT_SYMBOL(register_dma_controller);
++
++struct dma_controller *find_dma_controller(int id)
++{
++ struct dma_controller *dmac;
++
++ list_for_each_entry(dmac, &controllers, list)
++ if (dmac->id == id)
++ return dmac;
++ return NULL;
++}
++EXPORT_SYMBOL(find_dma_controller);
+diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c
+index 61f2de2..a8e767d 100644
+--- a/arch/avr32/kernel/irq.c
++++ b/arch/avr32/kernel/irq.c
+@@ -25,6 +25,17 @@ void ack_bad_irq(unsigned int irq)
+ printk("unexpected IRQ %u\n", irq);
+ }
+
++/* May be overridden by platform code */
++int __weak nmi_enable(void)
++{
++ return -ENOSYS;
++}
++
++void __weak nmi_disable(void)
++{
++
++}
++
+ #ifdef CONFIG_PROC_FS
+ int show_interrupts(struct seq_file *p, void *v)
+ {
+diff --git a/arch/avr32/kernel/kprobes.c b/arch/avr32/kernel/kprobes.c
+index 799ba89..f820e9f 100644
+--- a/arch/avr32/kernel/kprobes.c
++++ b/arch/avr32/kernel/kprobes.c
+@@ -48,6 +48,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
+ void __kprobes arch_arm_kprobe(struct kprobe *p)
+ {
+ pr_debug("arming kprobe at %p\n", p->addr);
++ ocd_enable(NULL);
+ *p->addr = BREAKPOINT_INSTRUCTION;
+ flush_icache_range((unsigned long)p->addr,
+ (unsigned long)p->addr + sizeof(kprobe_opcode_t));
+@@ -56,6 +57,7 @@ void __kprobes arch_arm_kprobe(struct kprobe *p)
+ void __kprobes arch_disarm_kprobe(struct kprobe *p)
+ {
+ pr_debug("disarming kprobe at %p\n", p->addr);
++ ocd_disable(NULL);
+ *p->addr = p->opcode;
+ flush_icache_range((unsigned long)p->addr,
+ (unsigned long)p->addr + sizeof(kprobe_opcode_t));
+@@ -260,9 +262,6 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+
+ int __init arch_init_kprobes(void)
+ {
+- printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
+- ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
+-
+ /* TODO: Register kretprobe trampoline */
+ return 0;
+ }
+diff --git a/arch/avr32/kernel/nmi_debug.c b/arch/avr32/kernel/nmi_debug.c
+new file mode 100644
+index 0000000..3414b85
+--- /dev/null
++++ b/arch/avr32/kernel/nmi_debug.c
+@@ -0,0 +1,82 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/delay.h>
++#include <linux/kdebug.h>
++#include <linux/notifier.h>
++#include <linux/sched.h>
++
++#include <asm/irq.h>
++
++enum nmi_action {
++ NMI_SHOW_STATE = 1 << 0,
++ NMI_SHOW_REGS = 1 << 1,
++ NMI_DIE = 1 << 2,
++ NMI_DEBOUNCE = 1 << 3,
++};
++
++static unsigned long nmi_actions;
++
++static int nmi_debug_notify(struct notifier_block *self,
++ unsigned long val, void *data)
++{
++ struct die_args *args = data;
++
++ if (likely(val != DIE_NMI))
++ return NOTIFY_DONE;
++
++ if (nmi_actions & NMI_SHOW_STATE)
++ show_state();
++ if (nmi_actions & NMI_SHOW_REGS)
++ show_regs(args->regs);
++ if (nmi_actions & NMI_DEBOUNCE)
++ mdelay(10);
++ if (nmi_actions & NMI_DIE)
++ return NOTIFY_BAD;
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block nmi_debug_nb = {
++ .notifier_call = nmi_debug_notify,
++};
++
++static int __init nmi_debug_setup(char *str)
++{
++ char *p, *sep;
++
++ register_die_notifier(&nmi_debug_nb);
++ if (nmi_enable()) {
++ printk(KERN_WARNING "Unable to enable NMI.\n");
++ return 0;
++ }
++
++ if (*str != '=')
++ return 0;
++
++ for (p = str + 1; *p; p = sep + 1) {
++ sep = strchr(p, ',');
++ if (sep)
++ *sep = 0;
++ if (strcmp(p, "state") == 0)
++ nmi_actions |= NMI_SHOW_STATE;
++ else if (strcmp(p, "regs") == 0)
++ nmi_actions |= NMI_SHOW_REGS;
++ else if (strcmp(p, "debounce") == 0)
++ nmi_actions |= NMI_DEBOUNCE;
++ else if (strcmp(p, "die") == 0)
++ nmi_actions |= NMI_DIE;
++ else
++ printk(KERN_WARNING "NMI: Unrecognized action `%s'\n",
++ p);
++ if (!sep)
++ break;
++ }
++
++ return 0;
++}
++__setup("nmi_debug", nmi_debug_setup);
+diff --git a/arch/avr32/kernel/ocd.c b/arch/avr32/kernel/ocd.c
+new file mode 100644
+index 0000000..c4f0232
+--- /dev/null
++++ b/arch/avr32/kernel/ocd.c
+@@ -0,0 +1,163 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++
++#include <asm/ocd.h>
++
++static long ocd_count;
++static spinlock_t ocd_lock;
++
++/**
++ * ocd_enable - enable on-chip debugging
++ * @child: task to be debugged
++ *
++ * If @child is non-NULL, ocd_enable() first checks if debugging has
++ * already been enabled for @child, and if it has, does nothing.
++ *
++ * If @child is NULL (e.g. when debugging the kernel), or debugging
++ * has not already been enabled for it, ocd_enable() increments the
++ * reference count and enables the debugging hardware.
++ */
++void ocd_enable(struct task_struct *child)
++{
++ u32 dc;
++
++ if (child)
++ pr_debug("ocd_enable: child=%s [%u]\n",
++ child->comm, child->pid);
++ else
++ pr_debug("ocd_enable (no child)\n");
++
++ if (!child || !test_and_set_tsk_thread_flag(child, TIF_DEBUG)) {
++ spin_lock(&ocd_lock);
++ ocd_count++;
++ dc = ocd_read(DC);
++ dc |= (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT);
++ ocd_write(DC, dc);
++ spin_unlock(&ocd_lock);
++ }
++}
++
++/**
++ * ocd_disable - disable on-chip debugging
++ * @child: task that was being debugged, but isn't anymore
++ *
++ * If @child is non-NULL, ocd_disable() checks if debugging is enabled
++ * for @child, and if it isn't, does nothing.
++ *
++ * If @child is NULL (e.g. when debugging the kernel), or debugging is
++ * enabled, ocd_disable() decrements the reference count, and if it
++ * reaches zero, disables the debugging hardware.
++ */
++void ocd_disable(struct task_struct *child)
++{
++ u32 dc;
++
++ if (!child)
++ pr_debug("ocd_disable (no child)\n");
++ else if (test_tsk_thread_flag(child, TIF_DEBUG))
++ pr_debug("ocd_disable: child=%s [%u]\n",
++ child->comm, child->pid);
++
++ if (!child || test_and_clear_tsk_thread_flag(child, TIF_DEBUG)) {
++ spin_lock(&ocd_lock);
++ ocd_count--;
++
++ WARN_ON(ocd_count < 0);
++
++ if (ocd_count <= 0) {
++ dc = ocd_read(DC);
++ dc &= ~((1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
++ ocd_write(DC, dc);
++ }
++ spin_unlock(&ocd_lock);
++ }
++}
++
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++#include <linux/module.h>
++
++static struct dentry *ocd_debugfs_root;
++static struct dentry *ocd_debugfs_DC;
++static struct dentry *ocd_debugfs_DS;
++static struct dentry *ocd_debugfs_count;
++
++static u64 ocd_DC_get(void *data)
++{
++ return ocd_read(DC);
++}
++static void ocd_DC_set(void *data, u64 val)
++{
++ ocd_write(DC, val);
++}
++DEFINE_SIMPLE_ATTRIBUTE(fops_DC, ocd_DC_get, ocd_DC_set, "0x%08llx\n");
++
++static u64 ocd_DS_get(void *data)
++{
++ return ocd_read(DS);
++}
++DEFINE_SIMPLE_ATTRIBUTE(fops_DS, ocd_DS_get, NULL, "0x%08llx\n");
++
++static u64 ocd_count_get(void *data)
++{
++ return ocd_count;
++}
++DEFINE_SIMPLE_ATTRIBUTE(fops_count, ocd_count_get, NULL, "%lld\n");
++
++static void ocd_debugfs_init(void)
++{
++ struct dentry *root;
++
++ root = debugfs_create_dir("ocd", NULL);
++ if (IS_ERR(root) || !root)
++ goto err_root;
++ ocd_debugfs_root = root;
++
++ ocd_debugfs_DC = debugfs_create_file("DC", S_IRUSR | S_IWUSR,
++ root, NULL, &fops_DC);
++ if (!ocd_debugfs_DC)
++ goto err_DC;
++
++ ocd_debugfs_DS = debugfs_create_file("DS", S_IRUSR, root,
++ NULL, &fops_DS);
++ if (!ocd_debugfs_DS)
++ goto err_DS;
++
++ ocd_debugfs_count = debugfs_create_file("count", S_IRUSR, root,
++ NULL, &fops_count);
++ if (!ocd_debugfs_count)
++ goto err_count;
++
++ return;
++
++err_count:
++ debugfs_remove(ocd_debugfs_DS);
++err_DS:
++ debugfs_remove(ocd_debugfs_DC);
++err_DC:
++ debugfs_remove(ocd_debugfs_root);
++err_root:
++ printk(KERN_WARNING "OCD: Failed to create debugfs entries\n");
++}
++#else
++static inline void ocd_debugfs_init(void)
++{
++
++}
++#endif
++
++static int __init ocd_init(void)
++{
++ spin_lock_init(&ocd_lock);
++ ocd_debugfs_init();
++ return 0;
++}
++arch_initcall(ocd_init);
+diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
+index 9d6dac8..eaaa69b 100644
+--- a/arch/avr32/kernel/process.c
++++ b/arch/avr32/kernel/process.c
+@@ -103,7 +103,7 @@ EXPORT_SYMBOL(kernel_thread);
+ */
+ void exit_thread(void)
+ {
+- /* nothing to do */
++ ocd_disable(current);
+ }
+
+ void flush_thread(void)
+@@ -345,6 +345,9 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
+ p->thread.cpu_context.ksp = (unsigned long)childregs;
+ p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
+
++ if ((clone_flags & CLONE_PTRACE) && test_thread_flag(TIF_DEBUG))
++ ocd_enable(p);
++
+ return 0;
+ }
+
+diff --git a/arch/avr32/kernel/ptrace.c b/arch/avr32/kernel/ptrace.c
+index 002369e..1fed38f 100644
+--- a/arch/avr32/kernel/ptrace.c
++++ b/arch/avr32/kernel/ptrace.c
+@@ -58,6 +58,7 @@ void ptrace_disable(struct task_struct *child)
+ {
+ clear_tsk_thread_flag(child, TIF_SINGLE_STEP);
+ clear_tsk_thread_flag(child, TIF_BREAKPOINT);
++ ocd_disable(child);
+ }
+
+ /*
+@@ -144,10 +145,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+ {
+ int ret;
+
+- pr_debug("ptrace: Enabling monitor mode...\n");
+- ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
+- | (1 << OCD_DC_DBE_BIT));
+-
+ switch (request) {
+ /* Read the word at location addr in the child process */
+ case PTRACE_PEEKTEXT:
+diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
+index 4b4c188..488078d 100644
+--- a/arch/avr32/kernel/setup.c
++++ b/arch/avr32/kernel/setup.c
+@@ -273,6 +273,8 @@ static int __init early_parse_fbmem(char *p)
+ printk(KERN_WARNING
+ "Failed to allocate framebuffer memory\n");
+ fbmem_size = 0;
++ } else {
++ memset(__va(fbmem_start), 0, fbmem_size);
+ }
+ }
+
+diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c
+index 0ec1485..5616a00 100644
+--- a/arch/avr32/kernel/signal.c
++++ b/arch/avr32/kernel/signal.c
+@@ -270,19 +270,12 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset, int syscall)
+ if (!user_mode(regs))
+ return 0;
+
+- if (try_to_freeze()) {
+- signr = 0;
+- if (!signal_pending(current))
+- goto no_signal;
+- }
+-
+ if (test_thread_flag(TIF_RESTORE_SIGMASK))
+ oldset = ¤t->saved_sigmask;
+ else if (!oldset)
+ oldset = ¤t->blocked;
+
+ signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+-no_signal:
+ if (syscall) {
+ switch (regs->r12) {
+ case -ERESTART_RESTARTBLOCK:
+diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c
+index 870c075..cf6f686 100644
+--- a/arch/avr32/kernel/traps.c
++++ b/arch/avr32/kernel/traps.c
+@@ -9,6 +9,7 @@
+ #include <linux/bug.h>
+ #include <linux/init.h>
+ #include <linux/kallsyms.h>
++#include <linux/kdebug.h>
+ #include <linux/module.h>
+ #include <linux/notifier.h>
+ #include <linux/sched.h>
+@@ -107,9 +108,23 @@ void _exception(long signr, struct pt_regs *regs, int code,
+
+ asmlinkage void do_nmi(unsigned long ecr, struct pt_regs *regs)
+ {
+- printk(KERN_ALERT "Got Non-Maskable Interrupt, dumping regs\n");
+- show_regs_log_lvl(regs, KERN_ALERT);
+- show_stack_log_lvl(current, regs->sp, regs, KERN_ALERT);
++ int ret;
++
++ nmi_enter();
++
++ ret = notify_die(DIE_NMI, "NMI", regs, 0, ecr, SIGINT);
++ switch (ret) {
++ case NOTIFY_OK:
++ case NOTIFY_STOP:
++ return;
++ case NOTIFY_BAD:
++ die("Fatal Non-Maskable Interrupt", regs, SIGINT);
++ default:
++ break;
++ }
++
++ printk(KERN_ALERT "Got NMI, but nobody cared. Disabling...\n");
++ nmi_disable();
+ }
+
+ asmlinkage void do_critical_exception(unsigned long ecr, struct pt_regs *regs)
+diff --git a/arch/avr32/mach-at32ap/Kconfig b/arch/avr32/mach-at32ap/Kconfig
+index eb30783..0eb590a 100644
+--- a/arch/avr32/mach-at32ap/Kconfig
++++ b/arch/avr32/mach-at32ap/Kconfig
+@@ -3,9 +3,9 @@ if PLATFORM_AT32AP
+ menu "Atmel AVR32 AP options"
+
+ choice
+- prompt "AT32AP7000 static memory bus width"
+- depends on CPU_AT32AP7000
+- default AP7000_16_BIT_SMC
++ prompt "AT32AP700x static memory bus width"
++ depends on CPU_AT32AP700X
++ default AP700X_16_BIT_SMC
+ help
+ Define the width of the AP7000 external static memory interface.
+ This is used to determine how to mangle the address and/or data
+@@ -15,17 +15,24 @@ choice
+ width for all chip selects, excluding the flash (which is using
+ raw access and is thus not affected by any of this.)
+
+-config AP7000_32_BIT_SMC
++config AP700X_32_BIT_SMC
+ bool "32 bit"
+
+-config AP7000_16_BIT_SMC
++config AP700X_16_BIT_SMC
+ bool "16 bit"
+
+-config AP7000_8_BIT_SMC
++config AP700X_8_BIT_SMC
+ bool "8 bit"
+
+ endchoice
+
++config GPIO_DEV
++ bool "GPIO /dev interface"
++ select CONFIGFS_FS
++ default n
++ help
++ Say `Y' to enable a /dev interface to the GPIO pins.
++
+ endmenu
+
+ endif # PLATFORM_AT32AP
+diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
+index a8b4450..0f6162e 100644
+--- a/arch/avr32/mach-at32ap/Makefile
++++ b/arch/avr32/mach-at32ap/Makefile
+@@ -1,4 +1,5 @@
+ obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
+-obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
+-obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
++obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o
++obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
+ obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
++obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
+diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
+deleted file mode 100644
+index 7c4388f..0000000
+--- a/arch/avr32/mach-at32ap/at32ap7000.c
++++ /dev/null
+@@ -1,1730 +0,0 @@
+-/*
+- * Copyright (C) 2005-2006 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-#include <linux/clk.h>
+-#include <linux/fb.h>
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-#include <linux/dma-mapping.h>
+-#include <linux/spi/spi.h>
+-
+-#include <asm/io.h>
+-
+-#include <asm/arch/at32ap7000.h>
+-#include <asm/arch/board.h>
+-#include <asm/arch/portmux.h>
+-
+-#include <video/atmel_lcdc.h>
+-
+-#include "clock.h"
+-#include "hmatrix.h"
+-#include "pio.h"
+-#include "pm.h"
+-
+-
+-#define PBMEM(base) \
+- { \
+- .start = base, \
+- .end = base + 0x3ff, \
+- .flags = IORESOURCE_MEM, \
+- }
+-#define IRQ(num) \
+- { \
+- .start = num, \
+- .end = num, \
+- .flags = IORESOURCE_IRQ, \
+- }
+-#define NAMED_IRQ(num, _name) \
+- { \
+- .start = num, \
+- .end = num, \
+- .name = _name, \
+- .flags = IORESOURCE_IRQ, \
+- }
+-
+-/* REVISIT these assume *every* device supports DMA, but several
+- * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
+- */
+-#define DEFINE_DEV(_name, _id) \
+-static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
+-static struct platform_device _name##_id##_device = { \
+- .name = #_name, \
+- .id = _id, \
+- .dev = { \
+- .dma_mask = &_name##_id##_dma_mask, \
+- .coherent_dma_mask = DMA_32BIT_MASK, \
+- }, \
+- .resource = _name##_id##_resource, \
+- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
+-}
+-#define DEFINE_DEV_DATA(_name, _id) \
+-static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
+-static struct platform_device _name##_id##_device = { \
+- .name = #_name, \
+- .id = _id, \
+- .dev = { \
+- .dma_mask = &_name##_id##_dma_mask, \
+- .platform_data = &_name##_id##_data, \
+- .coherent_dma_mask = DMA_32BIT_MASK, \
+- }, \
+- .resource = _name##_id##_resource, \
+- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
+-}
+-
+-#define select_peripheral(pin, periph, flags) \
+- at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
+-
+-#define DEV_CLK(_name, devname, bus, _index) \
+-static struct clk devname##_##_name = { \
+- .name = #_name, \
+- .dev = &devname##_device.dev, \
+- .parent = &bus##_clk, \
+- .mode = bus##_clk_mode, \
+- .get_rate = bus##_clk_get_rate, \
+- .index = _index, \
+-}
+-
+-static DEFINE_SPINLOCK(pm_lock);
+-
+-unsigned long at32ap7000_osc_rates[3] = {
+- [0] = 32768,
+- /* FIXME: these are ATSTK1002-specific */
+- [1] = 20000000,
+- [2] = 12000000,
+-};
+-
+-static unsigned long osc_get_rate(struct clk *clk)
+-{
+- return at32ap7000_osc_rates[clk->index];
+-}
+-
+-static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
+-{
+- unsigned long div, mul, rate;
+-
+- if (!(control & PM_BIT(PLLEN)))
+- return 0;
+-
+- div = PM_BFEXT(PLLDIV, control) + 1;
+- mul = PM_BFEXT(PLLMUL, control) + 1;
+-
+- rate = clk->parent->get_rate(clk->parent);
+- rate = (rate + div / 2) / div;
+- rate *= mul;
+-
+- return rate;
+-}
+-
+-static unsigned long pll0_get_rate(struct clk *clk)
+-{
+- u32 control;
+-
+- control = pm_readl(PLL0);
+-
+- return pll_get_rate(clk, control);
+-}
+-
+-static unsigned long pll1_get_rate(struct clk *clk)
+-{
+- u32 control;
+-
+- control = pm_readl(PLL1);
+-
+- return pll_get_rate(clk, control);
+-}
+-
+-/*
+- * The AT32AP7000 has five primary clock sources: One 32kHz
+- * oscillator, two crystal oscillators and two PLLs.
+- */
+-static struct clk osc32k = {
+- .name = "osc32k",
+- .get_rate = osc_get_rate,
+- .users = 1,
+- .index = 0,
+-};
+-static struct clk osc0 = {
+- .name = "osc0",
+- .get_rate = osc_get_rate,
+- .users = 1,
+- .index = 1,
+-};
+-static struct clk osc1 = {
+- .name = "osc1",
+- .get_rate = osc_get_rate,
+- .index = 2,
+-};
+-static struct clk pll0 = {
+- .name = "pll0",
+- .get_rate = pll0_get_rate,
+- .parent = &osc0,
+-};
+-static struct clk pll1 = {
+- .name = "pll1",
+- .get_rate = pll1_get_rate,
+- .parent = &osc0,
+-};
+-
+-/*
+- * The main clock can be either osc0 or pll0. The boot loader may
+- * have chosen one for us, so we don't really know which one until we
+- * have a look at the SM.
+- */
+-static struct clk *main_clock;
+-
+-/*
+- * Synchronous clocks are generated from the main clock. The clocks
+- * must satisfy the constraint
+- * fCPU >= fHSB >= fPB
+- * i.e. each clock must not be faster than its parent.
+- */
+-static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
+-{
+- return main_clock->get_rate(main_clock) >> shift;
+-};
+-
+-static void cpu_clk_mode(struct clk *clk, int enabled)
+-{
+- unsigned long flags;
+- u32 mask;
+-
+- spin_lock_irqsave(&pm_lock, flags);
+- mask = pm_readl(CPU_MASK);
+- if (enabled)
+- mask |= 1 << clk->index;
+- else
+- mask &= ~(1 << clk->index);
+- pm_writel(CPU_MASK, mask);
+- spin_unlock_irqrestore(&pm_lock, flags);
+-}
+-
+-static unsigned long cpu_clk_get_rate(struct clk *clk)
+-{
+- unsigned long cksel, shift = 0;
+-
+- cksel = pm_readl(CKSEL);
+- if (cksel & PM_BIT(CPUDIV))
+- shift = PM_BFEXT(CPUSEL, cksel) + 1;
+-
+- return bus_clk_get_rate(clk, shift);
+-}
+-
+-static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
+-{
+- u32 control;
+- unsigned long parent_rate, child_div, actual_rate, div;
+-
+- parent_rate = clk->parent->get_rate(clk->parent);
+- control = pm_readl(CKSEL);
+-
+- if (control & PM_BIT(HSBDIV))
+- child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
+- else
+- child_div = 1;
+-
+- if (rate > 3 * (parent_rate / 4) || child_div == 1) {
+- actual_rate = parent_rate;
+- control &= ~PM_BIT(CPUDIV);
+- } else {
+- unsigned int cpusel;
+- div = (parent_rate + rate / 2) / rate;
+- if (div > child_div)
+- div = child_div;
+- cpusel = (div > 1) ? (fls(div) - 2) : 0;
+- control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
+- actual_rate = parent_rate / (1 << (cpusel + 1));
+- }
+-
+- pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
+- clk->name, rate, actual_rate);
+-
+- if (apply)
+- pm_writel(CKSEL, control);
+-
+- return actual_rate;
+-}
+-
+-static void hsb_clk_mode(struct clk *clk, int enabled)
+-{
+- unsigned long flags;
+- u32 mask;
+-
+- spin_lock_irqsave(&pm_lock, flags);
+- mask = pm_readl(HSB_MASK);
+- if (enabled)
+- mask |= 1 << clk->index;
+- else
+- mask &= ~(1 << clk->index);
+- pm_writel(HSB_MASK, mask);
+- spin_unlock_irqrestore(&pm_lock, flags);
+-}
+-
+-static unsigned long hsb_clk_get_rate(struct clk *clk)
+-{
+- unsigned long cksel, shift = 0;
+-
+- cksel = pm_readl(CKSEL);
+- if (cksel & PM_BIT(HSBDIV))
+- shift = PM_BFEXT(HSBSEL, cksel) + 1;
+-
+- return bus_clk_get_rate(clk, shift);
+-}
+-
+-static void pba_clk_mode(struct clk *clk, int enabled)
+-{
+- unsigned long flags;
+- u32 mask;
+-
+- spin_lock_irqsave(&pm_lock, flags);
+- mask = pm_readl(PBA_MASK);
+- if (enabled)
+- mask |= 1 << clk->index;
+- else
+- mask &= ~(1 << clk->index);
+- pm_writel(PBA_MASK, mask);
+- spin_unlock_irqrestore(&pm_lock, flags);
+-}
+-
+-static unsigned long pba_clk_get_rate(struct clk *clk)
+-{
+- unsigned long cksel, shift = 0;
+-
+- cksel = pm_readl(CKSEL);
+- if (cksel & PM_BIT(PBADIV))
+- shift = PM_BFEXT(PBASEL, cksel) + 1;
+-
+- return bus_clk_get_rate(clk, shift);
+-}
+-
+-static void pbb_clk_mode(struct clk *clk, int enabled)
+-{
+- unsigned long flags;
+- u32 mask;
+-
+- spin_lock_irqsave(&pm_lock, flags);
+- mask = pm_readl(PBB_MASK);
+- if (enabled)
+- mask |= 1 << clk->index;
+- else
+- mask &= ~(1 << clk->index);
+- pm_writel(PBB_MASK, mask);
+- spin_unlock_irqrestore(&pm_lock, flags);
+-}
+-
+-static unsigned long pbb_clk_get_rate(struct clk *clk)
+-{
+- unsigned long cksel, shift = 0;
+-
+- cksel = pm_readl(CKSEL);
+- if (cksel & PM_BIT(PBBDIV))
+- shift = PM_BFEXT(PBBSEL, cksel) + 1;
+-
+- return bus_clk_get_rate(clk, shift);
+-}
+-
+-static struct clk cpu_clk = {
+- .name = "cpu",
+- .get_rate = cpu_clk_get_rate,
+- .set_rate = cpu_clk_set_rate,
+- .users = 1,
+-};
+-static struct clk hsb_clk = {
+- .name = "hsb",
+- .parent = &cpu_clk,
+- .get_rate = hsb_clk_get_rate,
+-};
+-static struct clk pba_clk = {
+- .name = "pba",
+- .parent = &hsb_clk,
+- .mode = hsb_clk_mode,
+- .get_rate = pba_clk_get_rate,
+- .index = 1,
+-};
+-static struct clk pbb_clk = {
+- .name = "pbb",
+- .parent = &hsb_clk,
+- .mode = hsb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .users = 1,
+- .index = 2,
+-};
+-
+-/* --------------------------------------------------------------------
+- * Generic Clock operations
+- * -------------------------------------------------------------------- */
+-
+-static void genclk_mode(struct clk *clk, int enabled)
+-{
+- u32 control;
+-
+- control = pm_readl(GCCTRL(clk->index));
+- if (enabled)
+- control |= PM_BIT(CEN);
+- else
+- control &= ~PM_BIT(CEN);
+- pm_writel(GCCTRL(clk->index), control);
+-}
+-
+-static unsigned long genclk_get_rate(struct clk *clk)
+-{
+- u32 control;
+- unsigned long div = 1;
+-
+- control = pm_readl(GCCTRL(clk->index));
+- if (control & PM_BIT(DIVEN))
+- div = 2 * (PM_BFEXT(DIV, control) + 1);
+-
+- return clk->parent->get_rate(clk->parent) / div;
+-}
+-
+-static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
+-{
+- u32 control;
+- unsigned long parent_rate, actual_rate, div;
+-
+- parent_rate = clk->parent->get_rate(clk->parent);
+- control = pm_readl(GCCTRL(clk->index));
+-
+- if (rate > 3 * parent_rate / 4) {
+- actual_rate = parent_rate;
+- control &= ~PM_BIT(DIVEN);
+- } else {
+- div = (parent_rate + rate) / (2 * rate) - 1;
+- control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
+- actual_rate = parent_rate / (2 * (div + 1));
+- }
+-
+- dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
+- clk->name, rate, actual_rate);
+-
+- if (apply)
+- pm_writel(GCCTRL(clk->index), control);
+-
+- return actual_rate;
+-}
+-
+-int genclk_set_parent(struct clk *clk, struct clk *parent)
+-{
+- u32 control;
+-
+- dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
+- clk->name, parent->name, clk->parent->name);
+-
+- control = pm_readl(GCCTRL(clk->index));
+-
+- if (parent == &osc1 || parent == &pll1)
+- control |= PM_BIT(OSCSEL);
+- else if (parent == &osc0 || parent == &pll0)
+- control &= ~PM_BIT(OSCSEL);
+- else
+- return -EINVAL;
+-
+- if (parent == &pll0 || parent == &pll1)
+- control |= PM_BIT(PLLSEL);
+- else
+- control &= ~PM_BIT(PLLSEL);
+-
+- pm_writel(GCCTRL(clk->index), control);
+- clk->parent = parent;
+-
+- return 0;
+-}
+-
+-static void __init genclk_init_parent(struct clk *clk)
+-{
+- u32 control;
+- struct clk *parent;
+-
+- BUG_ON(clk->index > 7);
+-
+- control = pm_readl(GCCTRL(clk->index));
+- if (control & PM_BIT(OSCSEL))
+- parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
+- else
+- parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
+-
+- clk->parent = parent;
+-}
+-
+-/* --------------------------------------------------------------------
+- * System peripherals
+- * -------------------------------------------------------------------- */
+-static struct resource at32_pm0_resource[] = {
+- {
+- .start = 0xfff00000,
+- .end = 0xfff0007f,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(20),
+-};
+-
+-static struct resource at32ap700x_rtc0_resource[] = {
+- {
+- .start = 0xfff00080,
+- .end = 0xfff000af,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(21),
+-};
+-
+-static struct resource at32_wdt0_resource[] = {
+- {
+- .start = 0xfff000b0,
+- .end = 0xfff000cf,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct resource at32_eic0_resource[] = {
+- {
+- .start = 0xfff00100,
+- .end = 0xfff0013f,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(19),
+-};
+-
+-DEFINE_DEV(at32_pm, 0);
+-DEFINE_DEV(at32ap700x_rtc, 0);
+-DEFINE_DEV(at32_wdt, 0);
+-DEFINE_DEV(at32_eic, 0);
+-
+-/*
+- * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
+- * is always running.
+- */
+-static struct clk at32_pm_pclk = {
+- .name = "pclk",
+- .dev = &at32_pm0_device.dev,
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .users = 1,
+- .index = 0,
+-};
+-
+-static struct resource intc0_resource[] = {
+- PBMEM(0xfff00400),
+-};
+-struct platform_device at32_intc0_device = {
+- .name = "intc",
+- .id = 0,
+- .resource = intc0_resource,
+- .num_resources = ARRAY_SIZE(intc0_resource),
+-};
+-DEV_CLK(pclk, at32_intc0, pbb, 1);
+-
+-static struct clk ebi_clk = {
+- .name = "ebi",
+- .parent = &hsb_clk,
+- .mode = hsb_clk_mode,
+- .get_rate = hsb_clk_get_rate,
+- .users = 1,
+-};
+-static struct clk hramc_clk = {
+- .name = "hramc",
+- .parent = &hsb_clk,
+- .mode = hsb_clk_mode,
+- .get_rate = hsb_clk_get_rate,
+- .users = 1,
+- .index = 3,
+-};
+-
+-static struct resource smc0_resource[] = {
+- PBMEM(0xfff03400),
+-};
+-DEFINE_DEV(smc, 0);
+-DEV_CLK(pclk, smc0, pbb, 13);
+-DEV_CLK(mck, smc0, hsb, 0);
+-
+-static struct platform_device pdc_device = {
+- .name = "pdc",
+- .id = 0,
+-};
+-DEV_CLK(hclk, pdc, hsb, 4);
+-DEV_CLK(pclk, pdc, pba, 16);
+-
+-static struct clk pico_clk = {
+- .name = "pico",
+- .parent = &cpu_clk,
+- .mode = cpu_clk_mode,
+- .get_rate = cpu_clk_get_rate,
+- .users = 1,
+-};
+-
+-static struct resource dmaca0_resource[] = {
+- {
+- .start = 0xff200000,
+- .end = 0xff20ffff,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(2),
+-};
+-DEFINE_DEV(dmaca, 0);
+-DEV_CLK(hclk, dmaca0, hsb, 10);
+-
+-/* --------------------------------------------------------------------
+- * HMATRIX
+- * -------------------------------------------------------------------- */
+-
+-static struct clk hmatrix_clk = {
+- .name = "hmatrix_clk",
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .index = 2,
+- .users = 1,
+-};
+-#define HMATRIX_BASE ((void __iomem *)0xfff00800)
+-
+-#define hmatrix_readl(reg) \
+- __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
+-#define hmatrix_writel(reg,value) \
+- __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
+-
+-/*
+- * Set bits in the HMATRIX Special Function Register (SFR) used by the
+- * External Bus Interface (EBI). This can be used to enable special
+- * features like CompactFlash support, NAND Flash support, etc. on
+- * certain chipselects.
+- */
+-static inline void set_ebi_sfr_bits(u32 mask)
+-{
+- u32 sfr;
+-
+- clk_enable(&hmatrix_clk);
+- sfr = hmatrix_readl(SFR4);
+- sfr |= mask;
+- hmatrix_writel(SFR4, sfr);
+- clk_disable(&hmatrix_clk);
+-}
+-
+-/* --------------------------------------------------------------------
+- * System Timer/Counter (TC)
+- * -------------------------------------------------------------------- */
+-static struct resource at32_systc0_resource[] = {
+- PBMEM(0xfff00c00),
+- IRQ(22),
+-};
+-struct platform_device at32_systc0_device = {
+- .name = "systc",
+- .id = 0,
+- .resource = at32_systc0_resource,
+- .num_resources = ARRAY_SIZE(at32_systc0_resource),
+-};
+-DEV_CLK(pclk, at32_systc0, pbb, 3);
+-
+-/* --------------------------------------------------------------------
+- * PIO
+- * -------------------------------------------------------------------- */
+-
+-static struct resource pio0_resource[] = {
+- PBMEM(0xffe02800),
+- IRQ(13),
+-};
+-DEFINE_DEV(pio, 0);
+-DEV_CLK(mck, pio0, pba, 10);
+-
+-static struct resource pio1_resource[] = {
+- PBMEM(0xffe02c00),
+- IRQ(14),
+-};
+-DEFINE_DEV(pio, 1);
+-DEV_CLK(mck, pio1, pba, 11);
+-
+-static struct resource pio2_resource[] = {
+- PBMEM(0xffe03000),
+- IRQ(15),
+-};
+-DEFINE_DEV(pio, 2);
+-DEV_CLK(mck, pio2, pba, 12);
+-
+-static struct resource pio3_resource[] = {
+- PBMEM(0xffe03400),
+- IRQ(16),
+-};
+-DEFINE_DEV(pio, 3);
+-DEV_CLK(mck, pio3, pba, 13);
+-
+-static struct resource pio4_resource[] = {
+- PBMEM(0xffe03800),
+- IRQ(17),
+-};
+-DEFINE_DEV(pio, 4);
+-DEV_CLK(mck, pio4, pba, 14);
+-
+-void __init at32_add_system_devices(void)
+-{
+- platform_device_register(&at32_pm0_device);
+- platform_device_register(&at32_intc0_device);
+- platform_device_register(&at32ap700x_rtc0_device);
+- platform_device_register(&at32_wdt0_device);
+- platform_device_register(&at32_eic0_device);
+- platform_device_register(&smc0_device);
+- platform_device_register(&pdc_device);
+- platform_device_register(&dmaca0_device);
+-
+- platform_device_register(&at32_systc0_device);
+-
+- platform_device_register(&pio0_device);
+- platform_device_register(&pio1_device);
+- platform_device_register(&pio2_device);
+- platform_device_register(&pio3_device);
+- platform_device_register(&pio4_device);
+-}
+-
+-/* --------------------------------------------------------------------
+- * USART
+- * -------------------------------------------------------------------- */
+-
+-static struct atmel_uart_data atmel_usart0_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-static struct resource atmel_usart0_resource[] = {
+- PBMEM(0xffe00c00),
+- IRQ(6),
+-};
+-DEFINE_DEV_DATA(atmel_usart, 0);
+-DEV_CLK(usart, atmel_usart0, pba, 3);
+-
+-static struct atmel_uart_data atmel_usart1_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-static struct resource atmel_usart1_resource[] = {
+- PBMEM(0xffe01000),
+- IRQ(7),
+-};
+-DEFINE_DEV_DATA(atmel_usart, 1);
+-DEV_CLK(usart, atmel_usart1, pba, 4);
+-
+-static struct atmel_uart_data atmel_usart2_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-static struct resource atmel_usart2_resource[] = {
+- PBMEM(0xffe01400),
+- IRQ(8),
+-};
+-DEFINE_DEV_DATA(atmel_usart, 2);
+-DEV_CLK(usart, atmel_usart2, pba, 5);
+-
+-static struct atmel_uart_data atmel_usart3_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-static struct resource atmel_usart3_resource[] = {
+- PBMEM(0xffe01800),
+- IRQ(9),
+-};
+-DEFINE_DEV_DATA(atmel_usart, 3);
+-DEV_CLK(usart, atmel_usart3, pba, 6);
+-
+-static inline void configure_usart0_pins(void)
+-{
+- select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
+- select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
+-}
+-
+-static inline void configure_usart1_pins(void)
+-{
+- select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
+- select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
+-}
+-
+-static inline void configure_usart2_pins(void)
+-{
+- select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
+- select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
+-}
+-
+-static inline void configure_usart3_pins(void)
+-{
+- select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
+- select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
+-}
+-
+-static struct platform_device *__initdata at32_usarts[4];
+-
+-void __init at32_map_usart(unsigned int hw_id, unsigned int line)
+-{
+- struct platform_device *pdev;
+-
+- switch (hw_id) {
+- case 0:
+- pdev = &atmel_usart0_device;
+- configure_usart0_pins();
+- break;
+- case 1:
+- pdev = &atmel_usart1_device;
+- configure_usart1_pins();
+- break;
+- case 2:
+- pdev = &atmel_usart2_device;
+- configure_usart2_pins();
+- break;
+- case 3:
+- pdev = &atmel_usart3_device;
+- configure_usart3_pins();
+- break;
+- default:
+- return;
+- }
+-
+- if (PXSEG(pdev->resource[0].start) == P4SEG) {
+- /* Addresses in the P4 segment are permanently mapped 1:1 */
+- struct atmel_uart_data *data = pdev->dev.platform_data;
+- data->regs = (void __iomem *)pdev->resource[0].start;
+- }
+-
+- pdev->id = line;
+- at32_usarts[line] = pdev;
+-}
+-
+-struct platform_device *__init at32_add_device_usart(unsigned int id)
+-{
+- platform_device_register(at32_usarts[id]);
+- return at32_usarts[id];
+-}
+-
+-struct platform_device *atmel_default_console_device;
+-
+-void __init at32_setup_serial_console(unsigned int usart_id)
+-{
+- atmel_default_console_device = at32_usarts[usart_id];
+-}
+-
+-/* --------------------------------------------------------------------
+- * Ethernet
+- * -------------------------------------------------------------------- */
+-
+-static struct eth_platform_data macb0_data;
+-static struct resource macb0_resource[] = {
+- PBMEM(0xfff01800),
+- IRQ(25),
+-};
+-DEFINE_DEV_DATA(macb, 0);
+-DEV_CLK(hclk, macb0, hsb, 8);
+-DEV_CLK(pclk, macb0, pbb, 6);
+-
+-static struct eth_platform_data macb1_data;
+-static struct resource macb1_resource[] = {
+- PBMEM(0xfff01c00),
+- IRQ(26),
+-};
+-DEFINE_DEV_DATA(macb, 1);
+-DEV_CLK(hclk, macb1, hsb, 9);
+-DEV_CLK(pclk, macb1, pbb, 7);
+-
+-struct platform_device *__init
+-at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
+-{
+- struct platform_device *pdev;
+-
+- switch (id) {
+- case 0:
+- pdev = &macb0_device;
+-
+- select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
+- select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
+- select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
+- select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
+- select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
+- select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
+- select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
+- select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
+- select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
+- select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
+-
+- if (!data->is_rmii) {
+- select_peripheral(PC(0), PERIPH_A, 0); /* COL */
+- select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
+- select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
+- select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
+- select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
+- select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
+- select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
+- select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
+- select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
+- }
+- break;
+-
+- case 1:
+- pdev = &macb1_device;
+-
+- select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
+- select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
+- select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
+- select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
+- select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
+- select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
+- select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
+- select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
+- select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
+- select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
+-
+- if (!data->is_rmii) {
+- select_peripheral(PC(19), PERIPH_B, 0); /* COL */
+- select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
+- select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
+- select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
+- select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
+- select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
+- select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
+- select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
+- select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
+- }
+- break;
+-
+- default:
+- return NULL;
+- }
+-
+- memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
+- platform_device_register(pdev);
+-
+- return pdev;
+-}
+-
+-/* --------------------------------------------------------------------
+- * SPI
+- * -------------------------------------------------------------------- */
+-static struct resource atmel_spi0_resource[] = {
+- PBMEM(0xffe00000),
+- IRQ(3),
+-};
+-DEFINE_DEV(atmel_spi, 0);
+-DEV_CLK(spi_clk, atmel_spi0, pba, 0);
+-
+-static struct resource atmel_spi1_resource[] = {
+- PBMEM(0xffe00400),
+- IRQ(4),
+-};
+-DEFINE_DEV(atmel_spi, 1);
+-DEV_CLK(spi_clk, atmel_spi1, pba, 1);
+-
+-static void __init
+-at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
+- unsigned int n, const u8 *pins)
+-{
+- unsigned int pin, mode;
+-
+- for (; n; n--, b++) {
+- b->bus_num = bus_num;
+- if (b->chip_select >= 4)
+- continue;
+- pin = (unsigned)b->controller_data;
+- if (!pin) {
+- pin = pins[b->chip_select];
+- b->controller_data = (void *)pin;
+- }
+- mode = AT32_GPIOF_OUTPUT;
+- if (!(b->mode & SPI_CS_HIGH))
+- mode |= AT32_GPIOF_HIGH;
+- at32_select_gpio(pin, mode);
+- }
+-}
+-
+-struct platform_device *__init
+-at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
+-{
+- /*
+- * Manage the chipselects as GPIOs, normally using the same pins
+- * the SPI controller expects; but boards can use other pins.
+- */
+- static u8 __initdata spi0_pins[] =
+- { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
+- GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
+- static u8 __initdata spi1_pins[] =
+- { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
+- GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
+- struct platform_device *pdev;
+-
+- switch (id) {
+- case 0:
+- pdev = &atmel_spi0_device;
+- select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
+- select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
+- select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
+- at32_spi_setup_slaves(0, b, n, spi0_pins);
+- break;
+-
+- case 1:
+- pdev = &atmel_spi1_device;
+- select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
+- select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
+- select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
+- at32_spi_setup_slaves(1, b, n, spi1_pins);
+- break;
+-
+- default:
+- return NULL;
+- }
+-
+- spi_register_board_info(b, n);
+- platform_device_register(pdev);
+- return pdev;
+-}
+-
+-/* --------------------------------------------------------------------
+- * TWI
+- * -------------------------------------------------------------------- */
+-static struct resource atmel_twi0_resource[] __initdata = {
+- PBMEM(0xffe00800),
+- IRQ(5),
+-};
+-static struct clk atmel_twi0_pclk = {
+- .name = "twi_pclk",
+- .parent = &pba_clk,
+- .mode = pba_clk_mode,
+- .get_rate = pba_clk_get_rate,
+- .index = 2,
+-};
+-
+-struct platform_device *__init at32_add_device_twi(unsigned int id)
+-{
+- struct platform_device *pdev;
+-
+- if (id != 0)
+- return NULL;
+-
+- pdev = platform_device_alloc("atmel_twi", id);
+- if (!pdev)
+- return NULL;
+-
+- if (platform_device_add_resources(pdev, atmel_twi0_resource,
+- ARRAY_SIZE(atmel_twi0_resource)))
+- goto err_add_resources;
+-
+- select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
+- select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
+-
+- atmel_twi0_pclk.dev = &pdev->dev;
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-err_add_resources:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * MMC
+- * -------------------------------------------------------------------- */
+-static struct resource atmel_mci0_resource[] __initdata = {
+- PBMEM(0xfff02400),
+- IRQ(28),
+-};
+-static struct clk atmel_mci0_pclk = {
+- .name = "mci_clk",
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .index = 9,
+-};
+-
+-struct platform_device *__init at32_add_device_mci(unsigned int id)
+-{
+- struct platform_device *pdev;
+-
+- if (id != 0)
+- return NULL;
+-
+- pdev = platform_device_alloc("atmel_mci", id);
+- if (!pdev)
+- return NULL;
+-
+- if (platform_device_add_resources(pdev, atmel_mci0_resource,
+- ARRAY_SIZE(atmel_mci0_resource)))
+- goto err_add_resources;
+-
+- select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
+- select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
+- select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
+- select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
+- select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
+- select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
+-
+- atmel_mci0_pclk.dev = &pdev->dev;
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-err_add_resources:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * LCDC
+- * -------------------------------------------------------------------- */
+-static struct atmel_lcdfb_info atmel_lcdfb0_data;
+-static struct resource atmel_lcdfb0_resource[] = {
+- {
+- .start = 0xff000000,
+- .end = 0xff000fff,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(1),
+- {
+- /* Placeholder for pre-allocated fb memory */
+- .start = 0x00000000,
+- .end = 0x00000000,
+- .flags = 0,
+- },
+-};
+-DEFINE_DEV_DATA(atmel_lcdfb, 0);
+-DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
+-static struct clk atmel_lcdfb0_pixclk = {
+- .name = "lcdc_clk",
+- .dev = &atmel_lcdfb0_device.dev,
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 7,
+-};
+-
+-struct platform_device *__init
+-at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
+- unsigned long fbmem_start, unsigned long fbmem_len)
+-{
+- struct platform_device *pdev;
+- struct atmel_lcdfb_info *info;
+- struct fb_monspecs *monspecs;
+- struct fb_videomode *modedb;
+- unsigned int modedb_size;
+-
+- /*
+- * Do a deep copy of the fb data, monspecs and modedb. Make
+- * sure all allocations are done before setting up the
+- * portmux.
+- */
+- monspecs = kmemdup(data->default_monspecs,
+- sizeof(struct fb_monspecs), GFP_KERNEL);
+- if (!monspecs)
+- return NULL;
+-
+- modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
+- modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
+- if (!modedb)
+- goto err_dup_modedb;
+- monspecs->modedb = modedb;
+-
+- switch (id) {
+- case 0:
+- pdev = &atmel_lcdfb0_device;
+- select_peripheral(PC(19), PERIPH_A, 0); /* CC */
+- select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
+- select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
+- select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
+- select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
+- select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
+- select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
+- select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
+- select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
+- select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
+- select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
+- select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
+- select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
+- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
+- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
+- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
+- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
+- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
+- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
+- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
+- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
+- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
+- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
+- select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
+- select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
+- select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
+- select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
+- select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
+- select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
+- select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+- select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+-
+- clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
+- clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
+- break;
+-
+- default:
+- goto err_invalid_id;
+- }
+-
+- if (fbmem_len) {
+- pdev->resource[2].start = fbmem_start;
+- pdev->resource[2].end = fbmem_start + fbmem_len - 1;
+- pdev->resource[2].flags = IORESOURCE_MEM;
+- }
+-
+- info = pdev->dev.platform_data;
+- memcpy(info, data, sizeof(struct atmel_lcdfb_info));
+- info->default_monspecs = monspecs;
+-
+- platform_device_register(pdev);
+- return pdev;
+-
+-err_invalid_id:
+- kfree(modedb);
+-err_dup_modedb:
+- kfree(monspecs);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * SSC
+- * -------------------------------------------------------------------- */
+-static struct resource ssc0_resource[] = {
+- PBMEM(0xffe01c00),
+- IRQ(10),
+-};
+-DEFINE_DEV(ssc, 0);
+-DEV_CLK(pclk, ssc0, pba, 7);
+-
+-static struct resource ssc1_resource[] = {
+- PBMEM(0xffe02000),
+- IRQ(11),
+-};
+-DEFINE_DEV(ssc, 1);
+-DEV_CLK(pclk, ssc1, pba, 8);
+-
+-static struct resource ssc2_resource[] = {
+- PBMEM(0xffe02400),
+- IRQ(12),
+-};
+-DEFINE_DEV(ssc, 2);
+-DEV_CLK(pclk, ssc2, pba, 9);
+-
+-struct platform_device *__init
+-at32_add_device_ssc(unsigned int id, unsigned int flags)
+-{
+- struct platform_device *pdev;
+-
+- switch (id) {
+- case 0:
+- pdev = &ssc0_device;
+- if (flags & ATMEL_SSC_RF)
+- select_peripheral(PA(21), PERIPH_A, 0); /* RF */
+- if (flags & ATMEL_SSC_RK)
+- select_peripheral(PA(22), PERIPH_A, 0); /* RK */
+- if (flags & ATMEL_SSC_TK)
+- select_peripheral(PA(23), PERIPH_A, 0); /* TK */
+- if (flags & ATMEL_SSC_TF)
+- select_peripheral(PA(24), PERIPH_A, 0); /* TF */
+- if (flags & ATMEL_SSC_TD)
+- select_peripheral(PA(25), PERIPH_A, 0); /* TD */
+- if (flags & ATMEL_SSC_RD)
+- select_peripheral(PA(26), PERIPH_A, 0); /* RD */
+- break;
+- case 1:
+- pdev = &ssc1_device;
+- if (flags & ATMEL_SSC_RF)
+- select_peripheral(PA(0), PERIPH_B, 0); /* RF */
+- if (flags & ATMEL_SSC_RK)
+- select_peripheral(PA(1), PERIPH_B, 0); /* RK */
+- if (flags & ATMEL_SSC_TK)
+- select_peripheral(PA(2), PERIPH_B, 0); /* TK */
+- if (flags & ATMEL_SSC_TF)
+- select_peripheral(PA(3), PERIPH_B, 0); /* TF */
+- if (flags & ATMEL_SSC_TD)
+- select_peripheral(PA(4), PERIPH_B, 0); /* TD */
+- if (flags & ATMEL_SSC_RD)
+- select_peripheral(PA(5), PERIPH_B, 0); /* RD */
+- break;
+- case 2:
+- pdev = &ssc2_device;
+- if (flags & ATMEL_SSC_TD)
+- select_peripheral(PB(13), PERIPH_A, 0); /* TD */
+- if (flags & ATMEL_SSC_RD)
+- select_peripheral(PB(14), PERIPH_A, 0); /* RD */
+- if (flags & ATMEL_SSC_TK)
+- select_peripheral(PB(15), PERIPH_A, 0); /* TK */
+- if (flags & ATMEL_SSC_TF)
+- select_peripheral(PB(16), PERIPH_A, 0); /* TF */
+- if (flags & ATMEL_SSC_RF)
+- select_peripheral(PB(17), PERIPH_A, 0); /* RF */
+- if (flags & ATMEL_SSC_RK)
+- select_peripheral(PB(18), PERIPH_A, 0); /* RK */
+- break;
+- default:
+- return NULL;
+- }
+-
+- platform_device_register(pdev);
+- return pdev;
+-}
+-
+-/* --------------------------------------------------------------------
+- * USB Device Controller
+- * -------------------------------------------------------------------- */
+-static struct resource usba0_resource[] __initdata = {
+- {
+- .start = 0xff300000,
+- .end = 0xff3fffff,
+- .flags = IORESOURCE_MEM,
+- }, {
+- .start = 0xfff03000,
+- .end = 0xfff033ff,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(31),
+-};
+-static struct clk usba0_pclk = {
+- .name = "pclk",
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .index = 12,
+-};
+-static struct clk usba0_hclk = {
+- .name = "hclk",
+- .parent = &hsb_clk,
+- .mode = hsb_clk_mode,
+- .get_rate = hsb_clk_get_rate,
+- .index = 6,
+-};
+-
+-struct platform_device *__init
+-at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
+-{
+- struct platform_device *pdev;
+-
+- if (id != 0)
+- return NULL;
+-
+- pdev = platform_device_alloc("atmel_usba_udc", 0);
+- if (!pdev)
+- return NULL;
+-
+- if (platform_device_add_resources(pdev, usba0_resource,
+- ARRAY_SIZE(usba0_resource)))
+- goto out_free_pdev;
+-
+- if (data) {
+- if (platform_device_add_data(pdev, data, sizeof(*data)))
+- goto out_free_pdev;
+-
+- if (data->vbus_pin != GPIO_PIN_NONE)
+- at32_select_gpio(data->vbus_pin, 0);
+- }
+-
+- usba0_pclk.dev = &pdev->dev;
+- usba0_hclk.dev = &pdev->dev;
+-
+- platform_device_add(pdev);
+-
+- return pdev;
+-
+-out_free_pdev:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * IDE / CompactFlash
+- * -------------------------------------------------------------------- */
+-static struct resource at32_smc_cs4_resource[] __initdata = {
+- {
+- .start = 0x04000000,
+- .end = 0x07ffffff,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(~0UL), /* Magic IRQ will be overridden */
+-};
+-static struct resource at32_smc_cs5_resource[] __initdata = {
+- {
+- .start = 0x20000000,
+- .end = 0x23ffffff,
+- .flags = IORESOURCE_MEM,
+- },
+- IRQ(~0UL), /* Magic IRQ will be overridden */
+-};
+-
+-static int __init at32_init_ide_or_cf(struct platform_device *pdev,
+- unsigned int cs, unsigned int extint)
+-{
+- static unsigned int extint_pin_map[4] __initdata = {
+- GPIO_PIN_PB(25),
+- GPIO_PIN_PB(26),
+- GPIO_PIN_PB(27),
+- GPIO_PIN_PB(28),
+- };
+- static bool common_pins_initialized __initdata = false;
+- unsigned int extint_pin;
+- int ret;
+-
+- if (extint >= ARRAY_SIZE(extint_pin_map))
+- return -EINVAL;
+- extint_pin = extint_pin_map[extint];
+-
+- switch (cs) {
+- case 4:
+- ret = platform_device_add_resources(pdev,
+- at32_smc_cs4_resource,
+- ARRAY_SIZE(at32_smc_cs4_resource));
+- if (ret)
+- return ret;
+-
+- select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
+- set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
+- break;
+- case 5:
+- ret = platform_device_add_resources(pdev,
+- at32_smc_cs5_resource,
+- ARRAY_SIZE(at32_smc_cs5_resource));
+- if (ret)
+- return ret;
+-
+- select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
+- set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- if (!common_pins_initialized) {
+- select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
+- select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
+- select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
+- select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
+- common_pins_initialized = true;
+- }
+-
+- at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
+-
+- pdev->resource[1].start = EIM_IRQ_BASE + extint;
+- pdev->resource[1].end = pdev->resource[1].start;
+-
+- return 0;
+-}
+-
+-struct platform_device *__init
+-at32_add_device_ide(unsigned int id, unsigned int extint,
+- struct ide_platform_data *data)
+-{
+- struct platform_device *pdev;
+-
+- pdev = platform_device_alloc("at32_ide", id);
+- if (!pdev)
+- goto fail;
+-
+- if (platform_device_add_data(pdev, data,
+- sizeof(struct ide_platform_data)))
+- goto fail;
+-
+- if (at32_init_ide_or_cf(pdev, data->cs, extint))
+- goto fail;
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-fail:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-struct platform_device *__init
+-at32_add_device_cf(unsigned int id, unsigned int extint,
+- struct cf_platform_data *data)
+-{
+- struct platform_device *pdev;
+-
+- pdev = platform_device_alloc("at32_cf", id);
+- if (!pdev)
+- goto fail;
+-
+- if (platform_device_add_data(pdev, data,
+- sizeof(struct cf_platform_data)))
+- goto fail;
+-
+- if (at32_init_ide_or_cf(pdev, data->cs, extint))
+- goto fail;
+-
+- if (data->detect_pin != GPIO_PIN_NONE)
+- at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
+- if (data->reset_pin != GPIO_PIN_NONE)
+- at32_select_gpio(data->reset_pin, 0);
+- if (data->vcc_pin != GPIO_PIN_NONE)
+- at32_select_gpio(data->vcc_pin, 0);
+- /* READY is used as extint, so we can't select it as gpio */
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-fail:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * AC97C
+- * -------------------------------------------------------------------- */
+-static struct resource atmel_ac97c0_resource[] __initdata = {
+- PBMEM(0xfff02800),
+- IRQ(29),
+-};
+-static struct clk atmel_ac97c0_pclk = {
+- .name = "pclk",
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .index = 10,
+-};
+-
+-struct platform_device *__init at32_add_device_ac97c(unsigned int id)
+-{
+- struct platform_device *pdev;
+-
+- if (id != 0)
+- return NULL;
+-
+- pdev = platform_device_alloc("atmel_ac97c", id);
+- if (!pdev)
+- return NULL;
+-
+- if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
+- ARRAY_SIZE(atmel_ac97c0_resource)))
+- goto err_add_resources;
+-
+- select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
+- select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
+- select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
+- select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
+-
+- atmel_ac97c0_pclk.dev = &pdev->dev;
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-err_add_resources:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * ABDAC
+- * -------------------------------------------------------------------- */
+-static struct resource abdac0_resource[] __initdata = {
+- PBMEM(0xfff02000),
+- IRQ(27),
+-};
+-static struct clk abdac0_pclk = {
+- .name = "pclk",
+- .parent = &pbb_clk,
+- .mode = pbb_clk_mode,
+- .get_rate = pbb_clk_get_rate,
+- .index = 8,
+-};
+-static struct clk abdac0_sample_clk = {
+- .name = "sample_clk",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 6,
+-};
+-
+-struct platform_device *__init at32_add_device_abdac(unsigned int id)
+-{
+- struct platform_device *pdev;
+-
+- if (id != 0)
+- return NULL;
+-
+- pdev = platform_device_alloc("abdac", id);
+- if (!pdev)
+- return NULL;
+-
+- if (platform_device_add_resources(pdev, abdac0_resource,
+- ARRAY_SIZE(abdac0_resource)))
+- goto err_add_resources;
+-
+- select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
+- select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
+- select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
+- select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
+-
+- abdac0_pclk.dev = &pdev->dev;
+- abdac0_sample_clk.dev = &pdev->dev;
+-
+- platform_device_add(pdev);
+- return pdev;
+-
+-err_add_resources:
+- platform_device_put(pdev);
+- return NULL;
+-}
+-
+-/* --------------------------------------------------------------------
+- * GCLK
+- * -------------------------------------------------------------------- */
+-static struct clk gclk0 = {
+- .name = "gclk0",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 0,
+-};
+-static struct clk gclk1 = {
+- .name = "gclk1",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 1,
+-};
+-static struct clk gclk2 = {
+- .name = "gclk2",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 2,
+-};
+-static struct clk gclk3 = {
+- .name = "gclk3",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 3,
+-};
+-static struct clk gclk4 = {
+- .name = "gclk4",
+- .mode = genclk_mode,
+- .get_rate = genclk_get_rate,
+- .set_rate = genclk_set_rate,
+- .set_parent = genclk_set_parent,
+- .index = 4,
+-};
+-
+-struct clk *at32_clock_list[] = {
+- &osc32k,
+- &osc0,
+- &osc1,
+- &pll0,
+- &pll1,
+- &cpu_clk,
+- &hsb_clk,
+- &pba_clk,
+- &pbb_clk,
+- &at32_pm_pclk,
+- &at32_intc0_pclk,
+- &hmatrix_clk,
+- &ebi_clk,
+- &hramc_clk,
+- &smc0_pclk,
+- &smc0_mck,
+- &pdc_hclk,
+- &pdc_pclk,
+- &dmaca0_hclk,
+- &pico_clk,
+- &pio0_mck,
+- &pio1_mck,
+- &pio2_mck,
+- &pio3_mck,
+- &pio4_mck,
+- &at32_systc0_pclk,
+- &atmel_usart0_usart,
+- &atmel_usart1_usart,
+- &atmel_usart2_usart,
+- &atmel_usart3_usart,
+- &macb0_hclk,
+- &macb0_pclk,
+- &macb1_hclk,
+- &macb1_pclk,
+- &atmel_spi0_spi_clk,
+- &atmel_spi1_spi_clk,
+- &atmel_twi0_pclk,
+- &atmel_mci0_pclk,
+- &atmel_lcdfb0_hck1,
+- &atmel_lcdfb0_pixclk,
+- &ssc0_pclk,
+- &ssc1_pclk,
+- &ssc2_pclk,
+- &usba0_hclk,
+- &usba0_pclk,
+- &atmel_ac97c0_pclk,
+- &abdac0_pclk,
+- &abdac0_sample_clk,
+- &gclk0,
+- &gclk1,
+- &gclk2,
+- &gclk3,
+- &gclk4,
+-};
+-unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
+-
+-void __init at32_portmux_init(void)
+-{
+- at32_init_pio(&pio0_device);
+- at32_init_pio(&pio1_device);
+- at32_init_pio(&pio2_device);
+- at32_init_pio(&pio3_device);
+- at32_init_pio(&pio4_device);
+-}
+-
+-void __init at32_clock_init(void)
+-{
+- u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
+- int i;
+-
+- if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
+- main_clock = &pll0;
+- cpu_clk.parent = &pll0;
+- } else {
+- main_clock = &osc0;
+- cpu_clk.parent = &osc0;
+- }
+-
+- if (pm_readl(PLL0) & PM_BIT(PLLOSC))
+- pll0.parent = &osc1;
+- if (pm_readl(PLL1) & PM_BIT(PLLOSC))
+- pll1.parent = &osc1;
+-
+- genclk_init_parent(&gclk0);
+- genclk_init_parent(&gclk1);
+- genclk_init_parent(&gclk2);
+- genclk_init_parent(&gclk3);
+- genclk_init_parent(&gclk4);
+- genclk_init_parent(&atmel_lcdfb0_pixclk);
+- genclk_init_parent(&abdac0_sample_clk);
+-
+- /*
+- * Turn on all clocks that have at least one user already, and
+- * turn off everything else. We only do this for module
+- * clocks, and even though it isn't particularly pretty to
+- * check the address of the mode function, it should do the
+- * trick...
+- */
+- for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
+- struct clk *clk = at32_clock_list[i];
+-
+- if (clk->users == 0)
+- continue;
+-
+- if (clk->mode == &cpu_clk_mode)
+- cpu_mask |= 1 << clk->index;
+- else if (clk->mode == &hsb_clk_mode)
+- hsb_mask |= 1 << clk->index;
+- else if (clk->mode == &pba_clk_mode)
+- pba_mask |= 1 << clk->index;
+- else if (clk->mode == &pbb_clk_mode)
+- pbb_mask |= 1 << clk->index;
+- }
+-
+- pm_writel(CPU_MASK, cpu_mask);
+- pm_writel(HSB_MASK, hsb_mask);
+- pm_writel(PBA_MASK, pba_mask);
+- pm_writel(PBB_MASK, pbb_mask);
+-}
+diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
+new file mode 100644
+index 0000000..06795d0
+--- /dev/null
++++ b/arch/avr32/mach-at32ap/at32ap700x.c
+@@ -0,0 +1,1809 @@
++/*
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
projects / openwrt.git / blobdiff