kernel: add scsi cdrom support

[openwrt.git] / target / linux / lantiq / patches / 105-header_xway.patch

diff --git a/target/linux/lantiq/patches/105-header_xway.patch b/target/linux/lantiq/patches/105-header_xway.patch
index f41e335..18e37a7 100644 (file)
--- a/target/linux/lantiq/patches/105-header_xway.patch
+++ b/target/linux/lantiq/patches/105-header_xway.patch
@@ -165,15 +165,15 @@
 + */
 +typedef void (*timer_callback)(unsigned long arg);
 +
 + */
 +typedef void (*timer_callback)(unsigned long arg);
 +

-+extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
-+extern int ifxmips_free_timer(unsigned int);
-+extern int ifxmips_start_timer(unsigned int, int);
-+extern int ifxmips_stop_timer(unsigned int);
-+extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
-+extern int ifxmips_get_count_value(unsigned int, unsigned long *);
-+extern u32 ifxmips_cal_divider(unsigned long);
-+extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
-+extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
++extern int lq_free_timer(unsigned int);
++extern int lq_start_timer(unsigned int, int);
++extern int lq_stop_timer(unsigned int);
++extern int lq_reset_counter_flags(u32 timer, u32 flags);
++extern int lq_get_count_value(unsigned int, unsigned long *);
++extern u32 lq_cal_divider(unsigned long);
++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
++extern int lq_set_counter(unsigned int timer, unsigned int flag,

 +      u32 reload, unsigned long arg1, unsigned long arg2);
 +
 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 +      u32 reload, unsigned long arg1, unsigned long arg2);
 +
 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */


@@ -273,8 +273,8 @@
 +#define PCI_CS_PR_BASE_ADDR   (KSEG1 + 0x17000000)
 +
 +/*------------ WDT */
 +#define PCI_CS_PR_BASE_ADDR   (KSEG1 + 0x17000000)
 +
 +/*------------ WDT */

-+#define LQ_WDT_BASE                   0x1F880000
-+#define LQ_WDT_SIZE                   0x400
++#define LQ_WDT_BASE                   0x1F8803F0
++#define LQ_WDT_SIZE                   0x10

 +
 +/*------------ Serial To Parallel conversion  */
 +#define LQ_STP_BASE                   0x1E100BB0
 +
 +/*------------ Serial To Parallel conversion  */
 +#define LQ_STP_BASE                   0x1E100BB0


@@ -303,7 +303,7 @@
 +#endif
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
 +#endif
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h

-@@ -0,0 +1,144 @@
+@@ -0,0 +1,194 @@

 +/*
 + *   This program is free software; you can redistribute it and/or modify it
 + *   under the terms of the GNU General Public License version 2 as published
 +/*
 + *   This program is free software; you can redistribute it and/or modify it
 + *   under the terms of the GNU General Public License version 2 as published