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Support for BCM47XX based boards
-+config ATHEROS
++config ATHEROS_AR231X
+ bool "Atheros 231x/531x SoC support"
+ select CEVT_R4K
+ select CSRC_R4K
#
+# Atheros AR5312/AR2312 WiSoC
+#
-+core-$(CONFIG_ATHEROS) += arch/mips/ar231x/
-+cflags-$(CONFIG_ATHEROS) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
-+load-$(CONFIG_ATHEROS) += 0xffffffff80041000
++core-$(CONFIG_ATHEROS_AR231X) += arch/mips/ar231x/
++cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
++load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
+
+#
# Cobalt Server
@@ -0,0 +1,17 @@
+config ATHEROS_AR5312
+ bool "Atheros 5312/2312+ support"
-+ depends on ATHEROS
++ depends on ATHEROS_AR231X
+ default y
+
+config ATHEROS_AR2315
+ bool "Atheros 2315+ support"
-+ depends on ATHEROS
++ depends on ATHEROS_AR231X
+ select DMA_NONCOHERENT
+ select CEVT_R4K
+ select CSRC_R4K
+
--- /dev/null
+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,547 @@
+@@ -0,0 +1,549 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ if (!ar231x_board.radio)
+ return 0;
+
-+ if (*((u32 *) radio) & AR531X_RADIO0_MASK)
++ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) &&
++ (config->flags & BD_WLAN0))
+ ar231x_add_wmac(0, AR531X_WLAN0,
+ AR5312_IRQ_WLAN0_INTRS);
+
+ break;
+ }
+
-+ if (*((u32 *) radio) & AR531X_RADIO1_MASK)
++ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) &&
++ (config->flags & BD_WLAN1))
+ ar231x_add_wmac(1, AR531X_WLAN1,
+ AR5312_IRQ_WLAN1_INTRS);
+
+
--- /dev/null
+++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,643 @@
+@@ -0,0 +1,658 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ if (!pend)
+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
+
++ /* Enable interrupt with edge detection */
++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
++ return;
++
+ if (bit >= 0)
+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
+}
+{
+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
+
-+ /* reconfigure GPIO line as input */
-+ ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
-+
+ /* Enable interrupt with edge detection */
++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
++ return;
++
+ gpiointmask |= (1 << gpio);
+ ar2315_set_gpiointmask(gpio, 3);
+}
+
++static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
++{
++ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
++
++ /* reconfigure GPIO line as input */
++ ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
++ ar2315_gpio_intr_enable(irq);
++ return 0;
++}
++
+static void ar2315_gpio_intr_disable(unsigned int irq)
+{
+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
+
+static struct irq_chip ar2315_gpio_intr_controller = {
+ .typename = "AR2315-GPIO",
++ .startup = ar2315_gpio_intr_startup,
+ .ack = ar2315_gpio_intr_disable,
+ .mask_ack = ar2315_gpio_intr_disable,
+ .mask = ar2315_gpio_intr_disable,