ar71xx: add AR71XX_ prefix to GPIO_REG_* defines

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 87a352c..a83b046 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -89,7 +89,9 @@
 #define AR71XX_GPIO_IRQ_BASE   40
 #define AR71XX_GPIO_IRQ_COUNT  32
 #define AR71XX_PCI_IRQ_BASE    72
-#define AR71XX_PCI_IRQ_COUNT   8
+#define AR71XX_PCI_IRQ_COUNT   6
+#define AR934X_IP2_IRQ_BASE    78
+#define AR934X_IP2_IRQ_COUNT   2
 
 #define AR71XX_CPU_IRQ_IP2     (AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_USB     (AR71XX_CPU_IRQ_BASE + 3)
@@ -119,6 +121,9 @@
 #define AR71XX_PCI_IRQ_DEV2    (AR71XX_PCI_IRQ_BASE + 2)
 #define AR71XX_PCI_IRQ_CORE    (AR71XX_PCI_IRQ_BASE + 4)
 
+#define AR934X_IP2_IRQ_WMAC    (AR934X_IP2_IRQ_BASE + 0)
+#define AR934X_IP2_IRQ_PCIE    (AR934X_IP2_IRQ_BASE + 1)
+
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
@@ -413,17 +418,17 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 /*
  * GPIO block
  */
-#define GPIO_REG_OE            0x00
-#define GPIO_REG_IN            0x04
-#define GPIO_REG_OUT           0x08
-#define GPIO_REG_SET           0x0c
-#define GPIO_REG_CLEAR         0x10
-#define GPIO_REG_INT_MODE      0x14
-#define GPIO_REG_INT_TYPE      0x18
-#define GPIO_REG_INT_POLARITY  0x1c
-#define GPIO_REG_INT_PENDING   0x20
-#define GPIO_REG_INT_ENABLE    0x24
-#define GPIO_REG_FUNC          0x28
+#define AR71XX_GPIO_REG_OE             0x00
+#define AR71XX_GPIO_REG_IN             0x04
+#define AR71XX_GPIO_REG_OUT            0x08
+#define AR71XX_GPIO_REG_SET            0x0c
+#define AR71XX_GPIO_REG_CLEAR          0x10
+#define AR71XX_GPIO_REG_INT_MODE       0x14
+#define AR71XX_GPIO_REG_INT_TYPE       0x18
+#define AR71XX_GPIO_REG_INT_POLARITY   0x1c
+#define AR71XX_GPIO_REG_INT_PENDING    0x20
+#define AR71XX_GPIO_REG_INT_ENABLE     0x24
+#define AR71XX_GPIO_REG_FUNC           0x28
 
 #define AR71XX_GPIO_FUNC_STEREO_EN     BIT(17)
 #define AR71XX_GPIO_FUNC_SLIC_EN       BIT(16)
@@ -473,7 +478,7 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 #define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 #define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 
-#define AR934X_GPIO_COUNT              32
+#define AR934X_GPIO_COUNT              23
 #define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 
 extern void __iomem *ar71xx_gpio_base;
@@ -528,6 +533,7 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear);
 #define AR934X_DDR_REG_FLUSH_GE1       0xa0
 #define AR934X_DDR_REG_FLUSH_USB       0xa4
 #define AR934X_DDR_REG_FLUSH_PCIE      0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC      0xac
 
 
 #define PCI_WIN0_OFFS  0x10000000
@@ -623,9 +629,42 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR933X_BOOTSTRAP_REF_CLK_40            BIT(0)
 
 #define AR934X_RESET_REG_RESET_MODULE          0x1c
+
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP         BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC           BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0          BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1          BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2          BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3          BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+       (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+        AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+       (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
 #define AR934X_RESET_REG_BOOTSTRAP             0xb0
-/* 0 - 25MHz   1 - 40 MHz */
-#define AR934X_REF_CLK_40                      (1 << 4)
+#define AR934X_BOOTSTRAP_SW_OPTION8            BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7            BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6            BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5            BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4            BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3            BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2            BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1            BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE       BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC               BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE            BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40            BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI         BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED                BIT(1)
+#define AR934X_BOOTSTRAP_DDR1                  BIT(0)
 
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
@@ -692,6 +731,39 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR933X_RESET_USB_PHY           BIT(4)
 #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 
+#define AR934X_RESET_HOST              BIT(31)
+#define AR934X_RESET_SLIC              BIT(30)
+#define AR934X_RESET_HDMA              BIT(29)
+#define AR934X_RESET_EXTERNAL          BIT(28)
+#define AR934X_RESET_RTC               BIT(27)
+#define AR934X_RESET_PCIE_EP_INT       BIT(26)
+#define AR934X_RESET_CHKSUM_ACC                BIT(25)
+#define AR934X_RESET_FULL_CHIP         BIT(24)
+#define AR934X_RESET_GE1_MDIO          BIT(23)
+#define AR934X_RESET_GE0_MDIO          BIT(22)
+#define AR934X_RESET_CPU_NMI           BIT(21)
+#define AR934X_RESET_CPU_COLD          BIT(20)
+#define AR934X_RESET_HOST_RESET_INT    BIT(19)
+#define AR934X_RESET_PCIE_EP           BIT(18)
+#define AR934X_RESET_UART1             BIT(17)
+#define AR934X_RESET_DDR               BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF             BIT(14)
+#define AR934X_RESET_GE1_MAC           BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
+#define AR934X_RESET_HOST_DMA_INT      BIT(10)
+#define AR934X_RESET_GE0_MAC           BIT(9)
+#define AR934X_RESET_ETH_SIWTCH                BIT(8)
+#define AR934X_RESET_PCIE_PHY          BIT(7)
+#define AR934X_RESET_PCIE              BIT(6)
+#define AR934X_RESET_USB_HOST          BIT(5)
+#define AR934X_RESET_USB_PHY           BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
+#define AR934X_RESET_LUT               BIT(2)
+#define AR934X_RESET_MBOX              BIT(1)
+#define AR934X_RESET_I2S               BIT(0)
+
 #define REV_ID_MAJOR_MASK      0xfff0
 #define REV_ID_MAJOR_AR71XX    0x00a0
 #define REV_ID_MAJOR_AR913X    0x00b0
@@ -770,6 +842,13 @@ void ar71xx_flash_release(void);
 #define MII_REG_MII0_CTRL      0x00
 #define MII_REG_MII1_CTRL      0x04
 
+#define MII_CTRL_IF_MASK       3
+#define MII_CTRL_SPEED_SHIFT   4
+#define MII_CTRL_SPEED_MASK    3
+#define MII_CTRL_SPEED_10      0
+#define MII_CTRL_SPEED_100     1
+#define MII_CTRL_SPEED_1000    2
+
 #define MII0_CTRL_IF_GMII      0
 #define MII0_CTRL_IF_MII       1
 #define MII0_CTRL_IF_RGMII     2