ar71xx: add AR934X specific MDIO registration code

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 87a352c..99f3497 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -624,8 +624,21 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR934X_RESET_REG_RESET_MODULE          0x1c
 #define AR934X_RESET_REG_BOOTSTRAP             0xb0
-/* 0 - 25MHz   1 - 40 MHz */
-#define AR934X_REF_CLK_40                      (1 << 4)
+#define AR934X_BOOTSTRAP_SW_OPTION8            BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7            BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6            BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5            BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4            BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3            BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2            BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1            BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE       BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC               BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE            BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40            BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI         BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED                BIT(1)
+#define AR934X_BOOTSTRAP_DDR1                  BIT(0)
 
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
@@ -692,6 +705,39 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR933X_RESET_USB_PHY           BIT(4)
 #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 
+#define AR934X_RESET_HOST              BIT(31)
+#define AR934X_RESET_SLIC              BIT(30)
+#define AR934X_RESET_HDMA              BIT(29)
+#define AR934X_RESET_EXTERNAL          BIT(28)
+#define AR934X_RESET_RTC               BIT(27)
+#define AR934X_RESET_PCIE_EP_INT       BIT(26)
+#define AR934X_RESET_CHKSUM_ACC                BIT(25)
+#define AR934X_RESET_FULL_CHIP         BIT(24)
+#define AR934X_RESET_GE1_MDIO          BIT(23)
+#define AR934X_RESET_GE0_MDIO          BIT(22)
+#define AR934X_RESET_CPU_NMI           BIT(21)
+#define AR934X_RESET_CPU_COLD          BIT(20)
+#define AR934X_RESET_HOST_RESET_INT    BIT(19)
+#define AR934X_RESET_PCIE_EP           BIT(18)
+#define AR934X_RESET_UART1             BIT(17)
+#define AR934X_RESET_DDR               BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF             BIT(14)
+#define AR934X_RESET_GE1_MAC           BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
+#define AR934X_RESET_HOST_DMA_INT      BIT(10)
+#define AR934X_RESET_GE0_MAC           BIT(9)
+#define AR934X_RESET_ETH_SIWTCH                BIT(8)
+#define AR934X_RESET_PCIE_PHY          BIT(7)
+#define AR934X_RESET_PCIE              BIT(6)
+#define AR934X_RESET_USB_HOST          BIT(5)
+#define AR934X_RESET_USB_PHY           BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
+#define AR934X_RESET_LUT               BIT(2)
+#define AR934X_RESET_MBOX              BIT(1)
+#define AR934X_RESET_I2S               BIT(0)
+
 #define REV_ID_MAJOR_MASK      0xfff0
 #define REV_ID_MAJOR_AR71XX    0x00a0
 #define REV_ID_MAJOR_AR913X    0x00b0