#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
-#define RT2880_PCI_SLOT1_BASE 0x20000000
+#define RT2880_PCI_MEM_BASE 0x20000000
+#define RT2880_PCI_MEM_SIZE 0x10000000
+#define RT2880_PCI_IO_BASE 0x00460000
+#define RT2880_PCI_IO_SIZE 0x00010000
#define RT2880_PCI_REG_PCICFG_ADDR 0x00
#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
#define RT2880_PCI_REG_SUBID 0x38
#define RT2880_PCI_REG_ARBCTL 0x80
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-void __iomem *rt2880_pci_base;
+static void __iomem *rt2880_pci_base;
+static DEFINE_SPINLOCK(rt2880_pci_lock);
static u32 rt2880_pci_reg_read(u32 reg)
{
writel(val, rt2880_pci_base + reg);
}
-static void config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned char where, u32 *data)
+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+ unsigned int func, unsigned int where)
{
- unsigned int slot = PCI_SLOT(devfn);
- unsigned int address;
- u8 func = PCI_FUNC(devfn);
-
- address = (bus->number << 16) | (slot << 11) | (func << 8) |
- (where & 0xfc) | 0x80000000;
-
- rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- if (access_type == PCI_ACCESS_WRITE)
- rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
- else
- *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+ 0x80000000);
}
static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
- u32 data = 0;
+ unsigned long flags;
+ u32 address;
+ u32 data;
- config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where);
- if (size == 1)
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+ switch (size) {
+ case 1:
*val = (data >> ((where & 3) << 3)) & 0xff;
- else if (size == 2)
+ break;
+ case 2:
*val = (data >> ((where & 3) << 3)) & 0xffff;
- else
+ break;
+ case 4:
*val = data;
+ break;
+ }
return PCIBIOS_SUCCESSFUL;
}
static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
- u32 data = 0;
+ unsigned long flags;
+ u32 address;
+ u32 data;
- if (size == 4) {
+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where);
+
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+
+ switch (size) {
+ case 1:
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 2:
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 4:
data = val;
- } else {
- config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
- if (size == 1)
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- else if (size == 2)
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
+ break;
}
- config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
+ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
.write = rt2880_pci_config_write,
};
-static struct resource rt2880_pci_io_resource = {
+static struct resource rt2880_pci_mem_resource = {
.name = "PCI MEM space",
- .start = 0x20000000,
- .end = 0x2FFFFFFF,
+ .start = RT2880_PCI_MEM_BASE,
+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
};
-static struct resource rt2880_pci_mem_resource = {
+static struct resource rt2880_pci_io_resource = {
.name = "PCI IO space",
- .start = 0x00460000,
- .end = 0x0046FFFF,
+ .start = RT2880_PCI_IO_BASE,
+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO,
};
static struct pci_controller rt2880_pci_controller = {
.pci_ops = &rt2880_pci_ops,
- .mem_resource = &rt2880_pci_io_resource,
- .io_resource = &rt2880_pci_mem_resource,
+ .mem_resource = &rt2880_pci_mem_resource,
+ .io_resource = &rt2880_pci_io_resource,
};
-static inline void read_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long *val)
+static inline u32 rt2880_pci_read_u32(unsigned long reg)
{
- unsigned long address;
+ unsigned long flags;
+ u32 address;
+ u32 ret;
+
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
- address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
- 0x80000000;
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+ return ret;
}
-static inline void write_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long val)
+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
{
- unsigned long address;
+ unsigned long flags;
+ u32 address;
- address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
- 0x80000000;
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
+
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u16 cmd;
- unsigned long val;
int irq = -1;
if (dev->bus->number != 0)
- return 0;
+ return irq;
switch (PCI_SLOT(dev->devfn)) {
case 0x00:
- write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
- read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
break;
case 0x11:
irq = RT288X_CPU_IRQ_PCI;
return irq;
}
-static int __init rt2880_pci_init(void)
+int __init rt288x_register_pci(void)
{
- unsigned long val = 0;
+ void __iomem *io_map_base;
int i;
rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
+ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
+ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
+ set_io_port_base((unsigned long) io_map_base);
+
+ ioport_resource.start = RT2880_PCI_IO_BASE;
+ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
+
rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
for(i = 0; i < 0xfffff; i++) {}
rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
- rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE);
- rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE);
+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
- write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
- read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
register_pci_controller(&rt2880_pci_controller);
return 0;
{
return 0;
}
-
-struct pci_fixup pcibios_fixups[] = {
- {0}
-};
-
-arch_initcall(rt2880_pci_init);
projects / openwrt.git / blobdiff