ar71xx: fix register range check for DMA stuck checks (thx, Frédéric Moulins)

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
index 9bfaa82..c541933 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
@@ -425,9 +425,39 @@ static void ag71xx_dma_reset(struct ag71xx *ag)
 
 static void ag71xx_hw_stop(struct ag71xx *ag)
 {
-       /* disable all interrupts and stop the rx engine */
+       /* disable all interrupts and stop the rx/tx engine */
        ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
        ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+       ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+}
+
+static void ag71xx_hw_setup(struct ag71xx *ag)
+{
+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+       /* setup MAC configuration registers */
+       ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
+
+       ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
+                 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
+
+       /* setup max frame length */
+       ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+
+       /* setup MII interface type */
+       ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
+
+       /* setup FIFO configuration registers */
+       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
+       if (pdata->is_ar724x) {
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+       } else {
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+       }
+       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
+       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 }
 
 static void ag71xx_hw_init(struct ag71xx *ag)
@@ -457,31 +487,38 @@ static void ag71xx_hw_init(struct ag71xx *ag)
        ar71xx_device_start(reset_mask);
        mdelay(200);
 
-       /* setup MAC configuration registers */
-       ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
+       ag71xx_hw_setup(ag);
 
-       ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
-                 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
+       ag71xx_dma_reset(ag);
+}
 
-       /* setup max frame length */
-       ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+static void ag71xx_fast_reset(struct ag71xx *ag)
+{
+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+       struct net_device *dev = ag->dev;
+       u32 reset_mask = pdata->reset_bit;
+       u32 rx_ds, tx_ds;
+       u32 mii_reg;
 
-       /* setup MII interface type */
-       ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
+       reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
 
-       /* setup FIFO configuration registers */
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
-       if (pdata->is_ar724x) {
-               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
-               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
-       } else {
-               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
-               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
-       }
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
+       mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
+       rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
+       tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
+
+       ar71xx_device_stop(reset_mask);
+       udelay(10);
+       ar71xx_device_start(reset_mask);
+       udelay(10);
 
        ag71xx_dma_reset(ag);
+       ag71xx_hw_setup(ag);
+
+       ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
+       ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
+       ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
+
+       ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 }
 
 static void ag71xx_hw_start(struct ag71xx *ag)
@@ -509,6 +546,9 @@ void ag71xx_link_adjust(struct ag71xx *ag)
                return;
        }
 
+       if (pdata->is_ar724x)
+               ag71xx_fast_reset(ag);
+
        cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
        cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
        cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
@@ -755,13 +795,43 @@ static void ag71xx_restart_work_func(struct work_struct *work)
 {
        struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 
+       if (ag71xx_get_pdata(ag)->is_ar724x) {
+               ag->link = 0;
+               ag71xx_link_adjust(ag);
+               return;
+       }
+
        ag71xx_stop(ag->dev);
        ag71xx_open(ag->dev);
 }
 
+static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
+{
+       u32 rx_sm, tx_sm, rx_fd;
+
+       if (likely(time_before(jiffies, timestamp + HZ/10)))
+               return false;
+
+       if (!netif_carrier_ok(ag->dev))
+               return false;
+
+       rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
+       if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
+               return true;
+
+       tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
+       rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
+       if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
+           ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
+               return true;
+
+       return false;
+}
+
 static int ag71xx_tx_packets(struct ag71xx *ag)
 {
        struct ag71xx_ring *ring = &ag->tx_ring;
+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
        int sent;
 
        DBG("%s: processing TX ring\n", ag->dev->name);
@@ -772,8 +842,12 @@ static int ag71xx_tx_packets(struct ag71xx *ag)
                struct ag71xx_desc *desc = ring->buf[i].desc;
                struct sk_buff *skb = ring->buf[i].skb;
 
-               if (!ag71xx_desc_empty(desc))
+               if (!ag71xx_desc_empty(desc)) {
+                       if (pdata->is_ar7240 &&
+                           ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
+                               schedule_work(&ag->restart_work);
                        break;
+               }
 
                ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);