-+ if (v & 0x100 /* Trans complete */)
-+ break;
-+ msleep(1);
-+ }
-+}
-+
-+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
- {
- const u16 mdio_control = 0x128;
- const u16 mdio_data = 0x12C;
-+ int max_retries = 10;
-+ u16 ret = 0;
- u32 v;
- int i;
-
-@@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
- v |= 0x2; /* MDIO Clock Divisor */
- pcicore_write32(pc, mdio_control, v);
-
-+ if (pc->dev->id.revision >= 10) {
-+ max_retries = 200;
-+ ssb_pcie_mdio_set_phy(pc, device);
-+ }
-+
- v = (1 << 30); /* Start of Transaction */
-- v |= (1 << 28); /* Write Transaction */
-+ v |= (1 << 29); /* Read Transaction */
- v |= (1 << 17); /* Turnaround */
-- v |= (u32)device << 22;
-+ if (pc->dev->id.revision < 10)
-+ v |= (u32)device << 22;
- v |= (u32)address << 18;
-- v |= data;
- pcicore_write32(pc, mdio_data, v);
- /* Wait for the device to complete the transaction */
- udelay(10);
-- for (i = 0; i < 10; i++) {
-+ for (i = 0; i < max_retries; i++) {
- v = pcicore_read32(pc, mdio_control);
-- if (v & 0x100 /* Trans complete */)
-+ if (v & 0x100 /* Trans complete */) {
-+ udelay(10);
-+ ret = pcicore_read32(pc, mdio_data);
- break;
-+ }
- msleep(1);
- }
- pcicore_write32(pc, mdio_control, 0);
-+ return ret;
- }
-
--static void ssb_broadcast_value(struct ssb_device *dev,
-- u32 address, u32 data)
-+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-+ u8 address, u16 data)
- {
-- /* This is used for both, PCI and ChipCommon core, so be careful. */
-- BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-- BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
--
-- ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
-- ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
-- ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
-- ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
--}
-+ const u16 mdio_control = 0x128;
-+ const u16 mdio_data = 0x12C;
-+ int max_retries = 10;
-+ u32 v;
-+ int i;
-
--static void ssb_commit_settings(struct ssb_bus *bus)
--{
-- struct ssb_device *dev;
-+ v = 0x80; /* Enable Preamble Sequence */
-+ v |= 0x2; /* MDIO Clock Divisor */
-+ pcicore_write32(pc, mdio_control, v);
-
-- dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-- if (WARN_ON(!dev))
-- return;
-- /* This forces an update of the cached registers. */
-- ssb_broadcast_value(dev, 0xFD8, 0);
-+ if (pc->dev->id.revision >= 10) {
-+ max_retries = 200;
-+ ssb_pcie_mdio_set_phy(pc, device);
-+ }
-+
-+ v = (1 << 30); /* Start of Transaction */
-+ v |= (1 << 28); /* Write Transaction */
-+ v |= (1 << 17); /* Turnaround */
-+ if (pc->dev->id.revision < 10)
-+ v |= (u32)device << 22;
-+ v |= (u32)address << 18;
-+ v |= data;
-+ pcicore_write32(pc, mdio_data, v);
-+ /* Wait for the device to complete the transaction */
-+ udelay(10);
-+ for (i = 0; i < max_retries; i++) {
-+ v = pcicore_read32(pc, mdio_control);
-+ if (v & 0x100 /* Trans complete */)
-+ break;
-+ msleep(1);
-+ }
-+ pcicore_write32(pc, mdio_control, 0);
- }
-
- int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-@@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
- if (pc->setup_done)
- goto out;
- if (pdev->id.coreid == SSB_DEV_PCI) {
-- tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-- tmp |= SSB_PCICORE_SBTOPCI_PREF;
-- tmp |= SSB_PCICORE_SBTOPCI_BURST;
-- pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
--
-- if (pdev->id.revision < 5) {
-- tmp = ssb_read32(pdev, SSB_IMCFGLO);
-- tmp &= ~SSB_IMCFGLO_SERTO;
-- tmp |= 2;
-- tmp &= ~SSB_IMCFGLO_REQTO;
-- tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
-- ssb_write32(pdev, SSB_IMCFGLO, tmp);
-- ssb_commit_settings(bus);
-- } else if (pdev->id.revision >= 11) {
-- tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-- tmp |= SSB_PCICORE_SBTOPCI_MRM;
-- pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-- }
-+ ssb_pcicore_pci_setup_workarounds(pc);
- } else {
- WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
-- //TODO: Better make defines for all these magic PCIE values.
-- if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
-- /* TLP Workaround register. */
-- tmp = ssb_pcie_read(pc, 0x4);
-- tmp |= 0x8;
-- ssb_pcie_write(pc, 0x4, tmp);
-- }
-- if (pdev->id.revision == 0) {
-- const u8 serdes_rx_device = 0x1F;
--
-- ssb_pcie_mdio_write(pc, serdes_rx_device,
-- 2 /* Timer */, 0x8128);
-- ssb_pcie_mdio_write(pc, serdes_rx_device,
-- 6 /* CDR */, 0x0100);
-- ssb_pcie_mdio_write(pc, serdes_rx_device,
-- 7 /* CDR BW */, 0x1466);
-- } else if (pdev->id.revision == 1) {
-- /* DLLP Link Control register. */
-- tmp = ssb_pcie_read(pc, 0x100);
-- tmp |= 0x40;
-- ssb_pcie_write(pc, 0x100, tmp);
-- }
-+ ssb_pcicore_pcie_setup_workarounds(pc);
- }
- pc->setup_done = 1;
- out:
-diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
-index e05ba6e..6ec6e09 100644
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -557,7 +557,7 @@ error:
- }
-
- /* Needs ssb_buses_lock() */
--static int ssb_attach_queued_buses(void)
-+static int __devinit ssb_attach_queued_buses(void)
- {
- struct ssb_bus *bus, *n;
- int err = 0;
-@@ -768,9 +768,9 @@ out:
- return err;
- }
-
--static int ssb_bus_register(struct ssb_bus *bus,
-- ssb_invariants_func_t get_invariants,
-- unsigned long baseaddr)
-+static int __devinit ssb_bus_register(struct ssb_bus *bus,
-+ ssb_invariants_func_t get_invariants,
-+ unsigned long baseaddr)
- {
- int err;
-
-@@ -851,8 +851,8 @@ err_disable_xtal:
- }
-
- #ifdef CONFIG_SSB_PCIHOST
--int ssb_bus_pcibus_register(struct ssb_bus *bus,
-- struct pci_dev *host_pci)
-+int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
-+ struct pci_dev *host_pci)
- {
- int err;
-
-@@ -875,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
- #endif /* CONFIG_SSB_PCIHOST */
-
- #ifdef CONFIG_SSB_PCMCIAHOST
--int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-- struct pcmcia_device *pcmcia_dev,
-- unsigned long baseaddr)
-+int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-+ struct pcmcia_device *pcmcia_dev,
-+ unsigned long baseaddr)
- {
- int err;
-
-@@ -897,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
- #endif /* CONFIG_SSB_PCMCIAHOST */
-
- #ifdef CONFIG_SSB_SDIOHOST
--int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
-- unsigned int quirks)
-+int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
-+ struct sdio_func *func,
-+ unsigned int quirks)
- {
- int err;
-
-@@ -918,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
- EXPORT_SYMBOL(ssb_bus_sdiobus_register);
- #endif /* CONFIG_SSB_PCMCIAHOST */
-
--int ssb_bus_ssbbus_register(struct ssb_bus *bus,
-- unsigned long baseaddr,
-- ssb_invariants_func_t get_invariants)
-+int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
-+ unsigned long baseaddr,
-+ ssb_invariants_func_t get_invariants)
- {
- int err;
-
-@@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
- switch (plltype) {
- case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
- if (m & SSB_CHIPCO_CLK_T6_MMASK)
-- return SSB_CHIPCO_CLK_T6_M0;
-- return SSB_CHIPCO_CLK_T6_M1;
-+ return SSB_CHIPCO_CLK_T6_M1;
-+ return SSB_CHIPCO_CLK_T6_M0;
- case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
- case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
- case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-@@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
- {
- u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
-
-- /* The REJECT bit changed position in TMSLOW between
-- * Backplane revisions. */
-+ /* The REJECT bit seems to be different for Backplane rev 2.3 */
- switch (rev) {
- case SSB_IDLOW_SSBREV_22:
-- return SSB_TMSLOW_REJECT_22;
-+ case SSB_IDLOW_SSBREV_24:
-+ case SSB_IDLOW_SSBREV_26:
-+ return SSB_TMSLOW_REJECT;
- case SSB_IDLOW_SSBREV_23:
- return SSB_TMSLOW_REJECT_23;
-- case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
-- case SSB_IDLOW_SSBREV_25: /* same here */
-- case SSB_IDLOW_SSBREV_26: /* same here */
-+ case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
- case SSB_IDLOW_SSBREV_27: /* same here */
-- return SSB_TMSLOW_REJECT_23; /* this is a guess */
-+ return SSB_TMSLOW_REJECT; /* this is a guess */
- default:
- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
- WARN_ON(1);
- }
-- return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
-+ return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
- }
-
- int ssb_device_is_enabled(struct ssb_device *dev)
-@@ -1266,7 +1266,10 @@ u32 ssb_dma_translation(struct ssb_device *dev)
- case SSB_BUSTYPE_SSB:
- return 0;
- case SSB_BUSTYPE_PCI:
-- return SSB_PCI_DMA;
-+ if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
-+ return SSB_PCIE_DMA_H32;
-+ else
-+ return SSB_PCI_DMA;
- default:
- __ssb_dma_not_implemented(dev);
- }
-@@ -1309,20 +1312,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
-
- int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
- {
-- struct ssb_chipcommon *cc;
- int err;
- enum ssb_clkmode mode;
-
- err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
- if (err)
- goto error;
-- cc = &bus->chipco;
-- mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
-- ssb_chipco_set_clockmode(cc, mode);
-
- #ifdef CONFIG_SSB_DEBUG
- bus->powered_up = 1;
- #endif
-+
-+ mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
-+ ssb_chipco_set_clockmode(&bus->chipco, mode);
-+
- return 0;
- error:
- ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
-@@ -1330,6 +1333,37 @@ error:
- }
- EXPORT_SYMBOL(ssb_bus_powerup);
-
-+static void ssb_broadcast_value(struct ssb_device *dev,
-+ u32 address, u32 data)
-+{
-+#ifdef CONFIG_SSB_DRIVER_PCICORE
-+ /* This is used for both, PCI and ChipCommon core, so be careful. */
-+ BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-+ BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-+#endif
-+
-+ ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
-+ ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
-+ ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
-+ ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
-+}
-+
-+void ssb_commit_settings(struct ssb_bus *bus)
-+{
-+ struct ssb_device *dev;
-+
-+#ifdef CONFIG_SSB_DRIVER_PCICORE
-+ dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-+#else
-+ dev = bus->chipco.dev;
-+#endif
-+ if (WARN_ON(!dev))
-+ return;
-+ /* This forces an update of the cached registers. */
-+ ssb_broadcast_value(dev, 0xFD8, 0);
-+}
-+EXPORT_SYMBOL(ssb_commit_settings);
-+
- u32 ssb_admatch_base(u32 adm)
- {
- u32 base = 0;
-diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
-index a467b20..a00b35f 100644
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
- static int ssb_pci_sprom_get(struct ssb_bus *bus,
- struct ssb_sprom *sprom)