/*
* Atheros AR71xx SoC specific definitions
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
#define AR71XX_DMA_SIZE 0x10000
#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
#define AR71XX_STEREO_SIZE 0x10000
+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+#define AR91XX_WMAC_SIZE 0x30000
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
#define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */
#define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */
+#define AR71XX_MACH_WNR2000 11 /* NETGEAR WNR2000 */
+#define AR71XX_MACH_PB42 12 /* Atheros PB42 */
+#define AR71XX_MACH_MZK_W300NH 13 /* Planex MZK-W300NH */
+#define AR71XX_MACH_MZK_W04NU 14 /* Planex MZK-W04NU */
/*
* PLL block
#define RESET_MODULE_EXTERNAL BIT(28)
#define RESET_MODULE_FULL_CHIP BIT(24)
+#define RESET_MODULE_AMBA2WMAC BIT(22)
#define RESET_MODULE_CPU_NMI BIT(21)
#define RESET_MODULE_CPU_COLD BIT(20)
#define RESET_MODULE_DMA BIT(19)