-From cdd4310f4631d5a41c2c6ab09bbddb558c26587f Mon Sep 17 00:00:00 2001
+From a34c288f7214637f214ec17fb2b35dd5d20b0634 Mon Sep 17 00:00:00 2001
From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Wed, 4 Feb 2009 20:43:00 +0100
+Date: Sat, 14 Mar 2009 20:41:58 +0100
Subject: [PATCH] rt2x00: Implement support for rt2800pci
Add support for the rt2800pci chipset.
-Includes various patches from Mattias, Mark and Felix.
+Includes various patches from Mattias, Mark, Felix and Xose.
+Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
Signed-off-by: Mark Asselstine <asselsm@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
drivers/net/wireless/rt2x00/Kconfig | 15 +
drivers/net/wireless/rt2x00/Makefile | 1 +
- drivers/net/wireless/rt2x00/rt2800pci.c | 2785 +++++++++++++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2800pci.h | 1877 +++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2x00.h | 4 +
- 5 files changed, 4682 insertions(+), 0 deletions(-)
+ drivers/net/wireless/rt2x00/rt2800pci.c | 3035 +++++++++++++++++++++++++++++++
+ drivers/net/wireless/rt2x00/rt2800pci.h | 1880 +++++++++++++++++++
+ drivers/net/wireless/rt2x00/rt2x00.h | 6 +
+ 5 files changed, 4937 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
obj-$(CONFIG_RT73USB) += rt73usb.o
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
-@@ -0,0 +1,2785 @@
+@@ -0,0 +1,3035 @@
+/*
+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
+ <http://rt2x00.serialmonkey.com>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
++#include <linux/platform_device.h>
+#include <linux/eeprom_93cx6.h>
+
+#include "rt2x00.h"
+#include "rt2x00pci.h"
+#include "rt2800pci.h"
+
++/* FIXME: Make Kconfig dependent */
++#ifdef CONFIG_PCI
++#define CONFIG_RT2800PCI_PCI
++#endif
++#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
++#define CONFIG_RT2800PCI_WISOC
++#endif
++
+/*
+ * Allow hardware encryption to be disabled.
+ */
+{
+ u32 reg;
+
-+ if (!word)
-+ return;
-+
+ mutex_lock(&rt2x00dev->csr_mutex);
+
+ /*
+ mutex_unlock(&rt2x00dev->csr_mutex);
+}
+
++static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
++{
++ unsigned int i;
++ u32 reg;
++
++ for (i = 0; i < 200; i++) {
++ rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
++
++ if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
++ (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
++ (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
++ (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
++ break;
++
++ udelay(REGISTER_BUSY_DELAY);
++ }
++
++ if (i == 200)
++ ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
++
++ rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
++ rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
++}
++
++#ifdef CONFIG_RT2800PCI_WISOC
++static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
++{
++ u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
++
++ memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
++}
++#else
++static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
++{
++}
++#endif /* CONFIG_RT2800PCI_WISOC */
++
++#ifdef CONFIG_RT2800PCI_PCI
+static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
+{
+ struct rt2x00_dev *rt2x00dev = eeprom->data;
+ rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
+}
+
++static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
++{
++ struct eeprom_93cx6 eeprom;
++ u32 reg;
++
++ rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
++
++ eeprom.data = rt2x00dev;
++ eeprom.register_read = rt2800pci_eepromregister_read;
++ eeprom.register_write = rt2800pci_eepromregister_write;
++ eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
++ PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
++ eeprom.reg_data_in = 0;
++ eeprom.reg_data_out = 0;
++ eeprom.reg_data_clock = 0;
++ eeprom.reg_chip_select = 0;
++
++ eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
++ EEPROM_SIZE / sizeof(u16));
++}
++#else
++static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
++{
++}
++#endif /* CONFIG_RT2800PCI_PCI */
++
+#ifdef CONFIG_RT2X00_LIB_DEBUGFS
+static const struct rt2x00debug rt2800pci_rt2x00debug = {
+ .owner = THIS_MODULE,
+ u32 offset;
+ u32 reg;
+
-+ offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
++ offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
+
+ rt2x00pci_register_read(rt2x00dev, offset, ®);
+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
+ !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
++ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
++ (crypto->cmd == SET_KEY) * crypto->cipher);
+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX,
+ (crypto->cmd == SET_KEY) * crypto->bssidx);
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
++ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
+ rt2x00pci_register_write(rt2x00dev, offset, reg);
+
-+ offset = MAC_IVEIV_ENTRY(crypto->aid);
++ offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
+
+ memset(&iveiv_entry, 0, sizeof(iveiv_entry));
+ if ((crypto->cipher == CIPHER_TKIP) ||
+ rt2x00pci_register_multiwrite(rt2x00dev, offset,
+ &iveiv_entry, sizeof(iveiv_entry));
+
-+ offset = MAC_WCID_ENTRY(crypto->aid);
++ offset = MAC_WCID_ENTRY(key->hw_key_idx);
+
+ memset(&wcid_entry, 0, sizeof(wcid_entry));
+ if (crypto->cmd == SET_KEY)
+ * Using the correct defines correctly will cause overhead,
+ * so just calculate the correct offset.
+ */
-+ field.bit_offset = (4 * key->keyidx);
++ field.bit_offset = 4 * (key->hw_key_idx % 8);
+ field.bit_mask = 0x7 << field.bit_offset;
+
+ offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
++
+ rt2x00pci_register_read(rt2x00dev, offset, ®);
+ rt2x00_set_field32(®, field,
+ (crypto->cmd == SET_KEY) * crypto->cipher);
+ if (crypto->cmd == SET_KEY) {
+ /*
+ * 1 pairwise key is possible per AID, this means that the AID
-+ * equals our hw_key_idx.
++ * equals our hw_key_idx. Make sure the WCID starts _after_ the
++ * last possible shared key entry.
+ */
-+ key->hw_key_idx = crypto->aid;
++ if (crypto->aid > (256 - 32))
++ return -ENOSPC;
++
++ key->hw_key_idx = 32 + crypto->aid;
++
+
+ memcpy(key_entry.key, crypto->key,
+ sizeof(key_entry.key));
+ rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
+ break;
+ case 2:
-+ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
++ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
+ break;
+ case 3:
+ /* Do nothing */
+}
+
+static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
++ struct ieee80211_conf *conf,
+ struct rf_channel *rf,
+ struct channel_info *info)
+{
+ unsigned int tx_pin;
+ u16 eeprom;
+
-+ tx_pin = 0;
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
-+
+ rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
+
+ /*
+ * Determine antenna settings from EEPROM
+ */
+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
++
+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
-+ /* Turn off unused PA or LNA when only 1T or 1R */
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
+ }
+
+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-+ /* Turn off unused PA or LNA when only 1T or 1R */
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
+ } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
+
+
+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
+ TXPOWER_A_TO_DEV(info->tx_power2));
-+
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
+ } else {
+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
+ TXPOWER_G_TO_DEV(info->tx_power1));
+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
+ TXPOWER_G_TO_DEV(info->tx_power2));
-+
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
+ }
+
-+ rt2x00_set_field32(&rf->rf4, RF4_BW40,
-+ test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
++ rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
+
+ rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
+ rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
+ }
-+
-+ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
-+ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
+ } else {
+ rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
+
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
+ else
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
++ }
++
++ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
++ rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
++ rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
++ rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
++ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
++
++ tx_pin = 0;
++
++ /* Turn on unused PA or LNA when not using 1T or 1R */
++ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
++ }
+
-+ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
-+ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
++ /* Turn on unused PA or LNA when not using 1T or 1R */
++ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
+ }
+
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
++
+ rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
+
+ msleep(1);
+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
+ rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
+
-+ rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
++ rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
+ } else {
-+ rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
++ rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
+
+ rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
+ rt2800pci_config_lna_gain(rt2x00dev, libconf);
+
+ if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
-+ rt2800pci_config_channel(rt2x00dev, &libconf->rf,
-+ &libconf->channel);
++ rt2800pci_config_channel(rt2x00dev, libconf->conf,
++ &libconf->rf, &libconf->channel);
+ if (flags & IEEE80211_CONF_CHANGE_POWER)
+ rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
+ if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
+
+ rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, ®);
+ rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
++ rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
++ IEEE80211_MAX_RTS_THRESHOLD);
+ rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
+ rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
+
+ /*
+ * ASIC will keep garbage value after boot, clear encryption keys.
+ */
-+ for (i = 0; i < 254; i++) {
++ for (i = 0; i < 256; i++) {
+ u32 wcid[2] = { 0xffffffff, 0x00ffffff };
+ rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
+ wcid, sizeof(wcid));
++
++ rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
++ rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
+ }
+
-+ for (i = 0; i < 4; i++)
++ for (i = 0; i < 16; i++)
+ rt2x00pci_register_write(rt2x00dev,
+ SHARED_KEY_MODE_ENTRY(i), 0);
+
-+ for (i = 0; i < 256; i++)
-+ rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
-+
+ /*
+ * Clear all beacons
+ * For the Beacon base registers we only need to clear
+ * BBP was enabled after firmware was loaded,
+ * but we need to reactivate it now.
+ */
-+ rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
-+ rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
++ rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
++ rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
+ msleep(1);
+
+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
+{
+ rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
+
-+ if (state == STATE_AWAKE)
-+ rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
-+ else
++ if (state == STATE_AWAKE) {
++ rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
++ rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
++ } else
+ rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
+
+ return 0;
+ test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
+ rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
+ rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
-+ skbdesc->entry->entry_idx);
++ test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
++ txdesc->key_idx : 0xff);
+ rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
+ rt2x00_set_field32(&word, TXWI_W1_PACKETID,
+ skbdesc->entry->queue->qid);
+ rt2x00_desc_write(txwi, 1, word);
+
-+ if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
-+ _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
-+ _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
-+ }
++ /*
++ * Always write 0 to IV/EIV fields, hardware will insert the IV
++ * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
++ * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
++ * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
++ * crypto entry in the registers should be used to encrypt the frame.
++ */
++ _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
++ _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
+
+ /*
+ * Initialize TX descriptor
+ rt2x00_desc_write(txd, 2, word);
+
+ rt2x00_desc_read(txd, 3, &word);
-+ rt2x00_set_field32(&word, TXD_W3_WIV, 1);
++ rt2x00_set_field32(&word, TXD_W3_WIV,
++ !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
+ rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
+ rt2x00_desc_write(txd, 3, word);
+}
+ * decryption. This prevents us from correct providing
+ * correct statistics through debugfs.
+ */
-+ rxdesc->cipher = CIPHER_NONE;
++ rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
+ rxdesc->cipher_status =
+ rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
+ }
+ /*
+ * Mask of 0x8 bit to remove the short preamble flag.
+ */
-+ if (rxdesc->dev_flags == RATE_MODE_CCK)
++ if (rxdesc->rate_mode == RATE_MODE_CCK)
+ rxdesc->signal &= ~0x8;
+
+ rxdesc->rssi =
+ /*
+ * Remove TXWI descriptor from start of buffer.
+ */
-+ skb_pull(entry->skb, TXWI_DESC_SIZE);
++ skb_pull(entry->skb, RXWI_DESC_SIZE);
+ skb_trim(entry->skb, rxdesc->size);
+}
+
+ */
+static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
+{
-+ struct eeprom_93cx6 eeprom;
-+ u32 reg;
+ u16 word;
+ u8 *mac;
+ u8 default_lna_gain;
+
-+ rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
-+
-+ eeprom.data = rt2x00dev;
-+ eeprom.register_read = rt2800pci_eepromregister_read;
-+ eeprom.register_write = rt2800pci_eepromregister_write;
-+ eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
-+ PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
-+ eeprom.reg_data_in = 0;
-+ eeprom.reg_data_out = 0;
-+ eeprom.reg_data_clock = 0;
-+ eeprom.reg_chip_select = 0;
-+
-+ eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
-+ EEPROM_SIZE / sizeof(u16));
++ /*
++ * Read EEPROM into buffer
++ */
++ switch(rt2x00dev->chip.rt) {
++ case RT2880:
++ case RT3052:
++ rt2800pci_read_eeprom_soc(rt2x00dev);
++ break;
++ default:
++ rt2800pci_read_eeprom_pci(rt2x00dev);
++ break;
++ }
+
+ /*
+ * Start validation of the data that has been read.
+ rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
+ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+ EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
++ } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
++ /*
++ * There is a max of 2 RX streams for RT2860 series
++ */
++ if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
++ rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
++ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+ }
+
+ rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
+ u32 reg;
+ u16 value;
+ u16 eeprom;
-+ u16 device;
+
+ /*
+ * Read EEPROM word for configuration.
+
+ /*
+ * Identify RF chipset.
-+ * To determine the RT chip we have to read the
-+ * PCI header of the device.
+ */
-+ pci_read_config_word(to_pci_dev(rt2x00dev->dev),
-+ PCI_CONFIG_HEADER_DEVICE, &device);
+ value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
+ rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
-+ rt2x00_set_chip(rt2x00dev, device, value, reg);
++ rt2x00_set_chip_rf(rt2x00dev, value, reg);
+
+ if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
+ !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
+ !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
+ !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
+ !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
-+ !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
++ !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
++ !rt2x00_rf(&rt2x00dev->chip, RF3052)) {
+ ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
+ return -ENODEV;
+ }
+ char *tx_power1;
+ char *tx_power2;
+ unsigned int i;
++ u16 eeprom;
+
+ /*
+ * Initialize all hw fields.
+ rt2x00_eeprom_addr(rt2x00dev,
+ EEPROM_MAC_ADDR_0));
+
++ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
++
+ /*
+ * Initialize hw_mode information.
+ */
+ spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
+
+ if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
-+ rt2x00_rf(&rt2x00dev->chip, RF2720)) {
++ rt2x00_rf(&rt2x00dev->chip, RF2720) ||
++ rt2x00_rf(&rt2x00dev->chip, RF3052)) {
+ spec->num_channels = 14;
+ spec->channels = rf_vals;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
+ IEEE80211_HT_CAP_PSMP_SUPPORT;
+ spec->ht.ampdu_factor = 3;
+ spec->ht.ampdu_density = 4;
-+ spec->ht.mcs.rx_mask[0] = 0xff;
-+ spec->ht.mcs.rx_mask[1] = 0xff;
+ spec->ht.mcs.tx_params =
-+ IEEE80211_HT_MCS_TX_DEFINED;
++ IEEE80211_HT_MCS_TX_DEFINED |
++ IEEE80211_HT_MCS_TX_RX_DIFF |
++ ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
++ IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
++
++ switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
++ case 3:
++ spec->ht.mcs.rx_mask[2] = 0xff;
++ case 2:
++ spec->ht.mcs.rx_mask[1] = 0xff;
++ case 1:
++ spec->ht.mcs.rx_mask[0] = 0xff;
++ spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
++ break;
++ }
+
+ /*
+ * Create channel information array
+/*
+ * IEEE80211 stack callback functions.
+ */
++static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
++ u32 *iv32, u16 *iv16)
++{
++ struct rt2x00_dev *rt2x00dev = hw->priv;
++ struct mac_iveiv_entry iveiv_entry;
++ u32 offset;
++
++ offset = MAC_IVEIV_ENTRY(hw_key_idx);
++ rt2x00pci_register_multiread(rt2x00dev, offset,
++ &iveiv_entry, sizeof(iveiv_entry));
++
++ memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
++ memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
++}
++
+static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
+{
+ struct rt2x00_dev *rt2x00dev = hw->priv;
+ .configure_filter = rt2x00mac_configure_filter,
+ .set_key = rt2x00mac_set_key,
+ .get_stats = rt2x00mac_get_stats,
++ .get_tkip_seq = rt2800pci_get_tkip_seq,
+ .set_rts_threshold = rt2800pci_set_rts_threshold,
+ .bss_info_changed = rt2x00mac_bss_info_changed,
+ .conf_tx = rt2800pci_conf_tx,
+
+static const struct data_queue_desc rt2800pci_queue_rx = {
+ .entry_num = RX_ENTRIES,
-+ .data_size = DATA_FRAME_SIZE,
++ .data_size = AGGREGATION_SIZE,
+ .desc_size = RXD_DESC_SIZE,
+ .priv_size = sizeof(struct queue_entry_priv_pci),
+};
+
+static const struct data_queue_desc rt2800pci_queue_tx = {
+ .entry_num = TX_ENTRIES,
-+ .data_size = DATA_FRAME_SIZE,
++ .data_size = AGGREGATION_SIZE,
+ .desc_size = TXD_DESC_SIZE,
+ .priv_size = sizeof(struct queue_entry_priv_pci),
+};
+/*
+ * RT2800pci module information.
+ */
++#ifdef CONFIG_RT2800PCI_PCI
+static struct pci_device_id rt2800pci_device_table[] = {
+ { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { 0, }
+};
++MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
++#endif /* CONFIG_RT2800PCI_PCI */
+
+MODULE_AUTHOR(DRV_PROJECT);
+MODULE_VERSION(DRV_VERSION);
+MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
+MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
-+MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
+MODULE_FIRMWARE(FIRMWARE_RT2860);
+MODULE_LICENSE("GPL");
+
++#ifdef CONFIG_RT2800PCI_WISOC
++
++#ifdef CONFIG_RALINK_RT288X
++#define WSOC_RT_CHIPSET RT2880
++#endif /* CONFIG_RALINK_RT288X */
++
++#ifdef CONFIG_RALINK_RT305X
++#define WSOC_RT_CHIPSET RT3052
++#endif /* CONFIG_RALINK_RT305X */
++
++static void rt2800soc_free_reg(struct rt2x00_dev *rt2x00dev)
++{
++ kfree(rt2x00dev->rf);
++ rt2x00dev->rf = NULL;
++
++ kfree(rt2x00dev->eeprom);
++ rt2x00dev->eeprom = NULL;
++}
++
++static int rt2800soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
++{
++ struct platform_device *pdev = to_platform_device(rt2x00dev->dev);
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ ERROR_PROBE("Failed to get MMIO resource\n");
++ return -ENODEV;
++ }
++
++ rt2x00dev->csr.base = (void __iomem *) KSEG1ADDR(res->start);
++ rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
++ if (!rt2x00dev->eeprom)
++ goto exit;
++
++ rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
++ if (!rt2x00dev->rf)
++ goto exit;
++
++ return 0;
++
++exit:
++ ERROR_PROBE("Failed to allocate registers.\n");
++ rt2800soc_free_reg(rt2x00dev);
++
++ return -ENOMEM;
++}
++
++static int rt2800soc_probe(struct platform_device *pdev)
++{
++ const struct rt2x00_ops *ops = &rt2800pci_ops;
++ struct ieee80211_hw *hw;
++ struct rt2x00_dev *rt2x00dev;
++ int retval;
++
++ hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
++ if (!hw) {
++ ERROR_PROBE("Failed to allocate hardware.\n");
++ return -ENOMEM;
++ }
++
++ platform_set_drvdata(pdev, hw);
++
++ rt2x00dev = hw->priv;
++ rt2x00dev->dev = &pdev->dev;
++ rt2x00dev->ops = ops;
++ rt2x00dev->hw = hw;
++ rt2x00dev->irq = platform_get_irq(pdev, 0);
++ rt2x00dev->name = pdev->dev.driver->name;
++
++ rt2x00_set_chip_rt(rt2x00dev, WSOC_RT_CHIPSET);
++
++ retval = rt2800soc_alloc_reg(rt2x00dev);
++ if (retval)
++ goto exit_free_device;
++
++ retval = rt2x00lib_probe_dev(rt2x00dev);
++ if (retval)
++ goto exit_free_reg;
++
++ return 0;
++
++exit_free_reg:
++ rt2800soc_free_reg(rt2x00dev);
++
++exit_free_device:
++ ieee80211_free_hw(hw);
++
++ return retval;
++}
++
++static int rt2800soc_remove(struct platform_device *pdev)
++{
++ struct ieee80211_hw *hw = platform_get_drvdata(pdev);
++ struct rt2x00_dev *rt2x00dev = hw->priv;
++
++ /*
++ * Free all allocated data.
++ */
++ rt2x00lib_remove_dev(rt2x00dev);
++ rt2800soc_free_reg(rt2x00dev);
++ ieee80211_free_hw(hw);
++
++ return 0;
++}
++
++static struct platform_driver rt2800soc_driver = {
++ .driver.name = "rt2800_wmac",
++ .probe = rt2800soc_probe,
++ .remove = rt2800soc_remove,
++};
++#endif /* CONFIG_RT2800PCI_WISOC */
++
++#ifdef CONFIG_RT2800PCI_PCI
+static struct pci_driver rt2800pci_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = rt2800pci_device_table,
+ .suspend = rt2x00pci_suspend,
+ .resume = rt2x00pci_resume,
+};
++#endif /* CONFIG_RT2800PCI_PCI */
+
+static int __init rt2800pci_init(void)
+{
-+ return pci_register_driver(&rt2800pci_driver);
++ int ret = 0;
++
++#ifdef CONFIG_RT2800PCI_WISOC
++ ret = platform_driver_register(&rt2800soc_driver);
++#endif
++#ifdef CONFIG_RT2800PCI_PCI
++ ret = pci_register_driver(&rt2800pci_driver);
++#endif
++ return ret;
+}
+
+static void __exit rt2800pci_exit(void)
+{
++#ifdef CONFIG_RT2800PCI_PCI
+ pci_unregister_driver(&rt2800pci_driver);
++#endif
++#ifdef CONFIG_RT2800PCI_WISOC
++ platform_driver_unregister(&rt2800soc_driver);
++#endif
+}
+
+module_init(rt2800pci_init);
+module_exit(rt2800pci_exit);
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
-@@ -0,0 +1,1877 @@
+@@ -0,0 +1,1880 @@
+/*
+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
+ <http://rt2x00.serialmonkey.com>
+ * RF2750 2.4G/5G 1T2R
+ * RF3020 2.4G 1T1R
+ * RF2020 2.4G B/G
++ * RF3052 2.4G 2T2R
+ */
+#define RF2820 0x0001
+#define RF2850 0x0002
+#define RF2750 0x0004
+#define RF3020 0x0005
+#define RF2020 0x0006
++#define RF3052 0x0008
+
+/*
+ * RT2860 version
+#define EEPROM_SIZE 0x0110
+#define BBP_BASE 0x0000
+#define BBP_SIZE 0x0080
-+#define RF_BASE 0x0000
-+#define RF_SIZE 0x0014
++#define RF_BASE 0x0004
++#define RF_SIZE 0x0010
+
+/*
+ * Number of TX queues.
+#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
+
+/*
-+ * RINGREG_DIFF
-+ */
-+#define RINGREG_DIFF 0x0010
-+
-+/*
+ * GPIO_CTRL_CFG:
+ */
+#define GPIO_CTRL_CFG 0x0228
+#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
+
+/*
-+ * PBF registers
++ * PBF registers
+ * Most are for debug. Driver doesn't touch PBF register.
+ */
+#define PBF_CFG 0x0408
+#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
+
+/*
-+ * PBF registers
++ * PBF registers
+ * Most are for debug. Driver doesn't touch PBF register.
+ */
+#define TXRXQ_PCNT 0x0438
+ * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
+ */
+#define TX_BAND_CFG 0x132c
++#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
+#define TX_BAND_CFG_A FIELD32(0x00000002)
+#define TX_BAND_CFG_BG FIELD32(0x00000004)
+
+} __attribute__ ((packed));
+
+/*
-+ * MAC_IVEIV:
-+ */
-+#define MAC_IVEIV_EIV FIELD32(0x20000000)
-+#define MAC_IVEIV_KEYIDX FIELD32(0xc0000000)
-+
-+/*
+ * MAC_WCID_ATTRIBUTE:
+ */
+#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
+ * H2M_MAILBOX_CID:
+ */
+#define H2M_MAILBOX_CID 0x7014
++#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
++#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
++#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
++#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
+
+/*
+ * H2M_MAILBOX_STATUS:
+#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
+#define RF4_TXPOWER_A FIELD32(0x00000780)
+#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
-+#define RF4_BW40 FIELD32(0x00200000)
++#define RF4_HT40 FIELD32(0x00200000)
+
+/*
+ * EEPROM content.
+#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
+
+/*
-+ * EEPROM TXPOWER 802.11G
++ * EEPROM TXPOWER 802.11BG
+ */
+#define EEPROM_TXPOWER_BG1 0x0029
+#define EEPROM_TXPOWER_BG2 0x0030
+ */
+#define MCU_SLEEP 0x30
+#define MCU_WAKEUP 0x31
++#define MCU_RADIO_OFF 0x35
+#define MCU_LED 0x50
+#define MCU_LED_STRENGTH 0x51
+#define MCU_LED_1 0x52
+#define MCU_LED_3 0x54
+#define MCU_RADAR 0x60
+#define MCU_BOOT_SIGNAL 0x72
++#define MCU_BBP_SIGNAL 0x80
++
++/*
++ * MCU mailbox tokens
++ */
++#define TOKEN_WAKUP 3
+
+/*
+ * DMA descriptor defines.
+#endif /* RT2800PCI_H */
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -138,6 +138,10 @@ struct rt2x00_chip {
+@@ -138,6 +138,12 @@ struct rt2x00_chip {
#define RT2561 0x0302
#define RT2661 0x0401
#define RT2571 0x1300
+#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
+#define RT2890 0x0701 /* 2.4GHz PCIe */
+#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
++#define RT2880 0x2880 /* WSOC */
++#define RT3052 0x3052 /* WSOC */
u16 rf;
u32 rev;
projects / openwrt.git / blobdiff