[package] base-files: rewrite killing of nonessential services to not rely on top...

[openwrt.git] / package / broadcom-diag / src / gpio.h

diff --git a/package/broadcom-diag/src/gpio.h b/package/broadcom-diag/src/gpio.h
index c6f34bd..7191778 100644 (file)
--- a/package/broadcom-diag/src/gpio.h
+++ b/package/broadcom-diag/src/gpio.h
@@ -1,70 +1,160 @@
 #ifndef __DIAG_GPIO_H
 #define __DIAG_GPIO_H
 
 #ifndef __DIAG_GPIO_H
 #define __DIAG_GPIO_H
 

-#include <typedefs.h>
-#include <osl.h>
-#include <bcmdevs.h>
-#include <sbutils.h>
-#include <sbconfig.h>
-#include <sbchipc.h>
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
-#include <sbmips.h>
-#else
-#include <hndcpu.h>
+#include <linux/interrupt.h>
+#include <linux/ssb/ssb_embedded.h>
+#include <linux/gpio.h>
+#include <bcm47xx.h>
+
+static inline u32 gpio_in(void)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               return ssb_gpio_in(&bcm47xx_bus.ssb, ~0);

 #endif
 #endif

+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, ~0);
+#endif
+       }
+       return -EINVAL;
+}

 
 

-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-#define sbh bcm947xx_sbh
-#define sbh_lock bcm947xx_sbh_lock
+static inline u32 gpio_out(u32 mask, u32 value)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);

 #endif
 #endif

+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+       }
+       return -EINVAL;
+}

 
 

-#define EXTIF_ADDR 0x1f000000
-#define EXTIF_UART (EXTIF_ADDR + 0x00800000)
+static inline u32 gpio_outen(u32 mask, u32 value)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
+               return 0;
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+               return 0;
+#endif
+       }
+       return -EINVAL;
+}

 
 

-#define GPIO_TYPE_NORMAL       (0x0 << 24)
-#define GPIO_TYPE_EXTIF        (0x1 << 24)
-#define GPIO_TYPE_MASK         (0xf << 24)
+static inline u32 gpio_control(u32 mask, u32 value)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+       }
+       return -EINVAL;
+}

 
 

-extern void *sbh;
-extern spinlock_t sbh_lock;
+static inline u32 gpio_setintmask(u32 mask, u32 value)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+       }
+       return -EINVAL;
+}

 
 

-#define gpio_in()      sb_gpioin(sbh)
-#define gpio_out(mask, value)  sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
-#define gpio_outen(mask, value)        sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_control(mask, value)      sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intmask(mask, value)      sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intpolarity(mask, value)  sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
+static inline u32 gpio_intpolarity(u32 mask, u32 value)
+{
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+       }
+       return -EINVAL;
+}

 
 

-static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
+#ifdef CONFIG_BCM47XX_SSB
+static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
+                                      u32 mask, u32 value)

 {
 {

-       unsigned int coreidx;
-       unsigned long flags;
-       chipcregs_t *cc;
-       int irq;
+       value &= mask;
+       value |= ssb_read32(dev, offset) & ~mask;
+       ssb_write32(dev, offset, value);
+       return value;
+}
+#endif

 
 

-       spin_lock_irqsave(sbh_lock, flags);
-       coreidx = sb_coreidx(sbh);
+#ifdef CONFIG_BCM47XX_BCMA
+static inline u32 __bcma_write32_masked(struct bcma_device *dev, u16 offset,
+                                      u32 mask, u32 value)
+{
+       value &= mask;
+       value |= bcma_read32(dev, offset) & ~mask;
+       bcma_write32(dev, offset, value);
+       return value;
+}
+#endif

 
 

-       irq = sb_irq(sbh) + 2;
-       if (enabled)
-               request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
-       else
-               free_irq(irq, handler);
+static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
+{
+       int irq;

 
 

-       if ((cc = sb_setcore(sbh, SB_CC, 0))) {
-               int intmask;
+       irq = gpio_to_irq(0);
+       if (irq == -EINVAL) return;
+       
+       if (enabled) {
+               if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
+                       return;
+       } else {
+               free_irq(irq, handler);
+       }

 
 

-               intmask = readl(&cc->intmask);
-               if (enabled)
-                       intmask |= CI_GPIO;
-               else
-                       intmask &= ~CI_GPIO;
-               writel(intmask, &cc->intmask);
+       switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+       case BCM47XX_BUS_TYPE_SSB:
+               if (bcm47xx_bus.ssb.chipco.dev)
+                       __ssb_write32_masked(bcm47xx_bus.ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+       case BCM47XX_BUS_TYPE_BCMA:
+               if (bcm47xx_bus.bcma.bus.drv_cc.core)
+                       __bcma_write32_masked(bcm47xx_bus.bcma.bus.drv_cc.core, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO, (enabled ? BCMA_CC_IRQ_GPIO : 0));
+#endif

        }
        }

-       sb_setcoreidx(sbh, coreidx);
-       spin_unlock_irqrestore(sbh_lock, flags);

 }
 
 }
 

+#define EXTIF_ADDR 0x1f000000
+#define EXTIF_UART (EXTIF_ADDR + 0x00800000)
+
+#define GPIO_TYPE_NORMAL       (0x0 << 24)
+#define GPIO_TYPE_EXTIF        (0x1 << 24)
+#define GPIO_TYPE_MASK         (0xf << 24)
+

 static inline void gpio_set_extif(int gpio, int value)
 {
        volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
 static inline void gpio_set_extif(int gpio, int value)
 {
        volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);


@@ -74,5 +164,4 @@ static inline void gpio_set_extif(int gpio, int value)
                *addr;
 }
 
                *addr;
 }
 

-
-#endif
+#endif /* __DIAG_GPIO_H */