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[ar7] generate NA and non-NA images for Titan platforms
[openwrt.git]
/
target
/
linux
/
brcm47xx
/
patches-2.6.32
/
700-ssb-gigabit-ethernet-driver.patch
diff --git
a/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
b/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
index
8cf9f8e
..
5793249
100644
(file)
--- a/
target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
+++ b/
target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
@@
-8,7
+8,7
@@
#include <net/checksum.h>
#include <net/ip.h>
#include <net/checksum.h>
#include <net/ip.h>
-@@ -4
46,8 +447
,9 @@ static void _tw32_flush(struct tg3 *tp,
+@@ -4
57,8 +458
,9 @@ static void _tw32_flush(struct tg3 *tp,
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
{
tp->write32_mbox(tp, off, val);
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
{
tp->write32_mbox(tp, off, val);
@@
-20,7
+20,7
@@
tp->read32_mbox(tp, off);
}
tp->read32_mbox(tp, off);
}
-@@ -4
57,7 +459
,7 @@ static void tg3_write32_tx_mbox(struct t
+@@ -4
68,7 +470
,7 @@ static void tg3_write32_tx_mbox(struct t
writel(val, mbox);
if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
writel(val, mbox);
writel(val, mbox);
if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
writel(val, mbox);
@@
-29,7
+29,7
@@
readl(mbox);
}
readl(mbox);
}
-@@ -7
29,7 +731
,7 @@ static void tg3_switch_clocks(struct tg3
+@@ -7
68,7 +770
,7 @@ static void tg3_switch_clocks(struct tg3
#define PHY_BUSY_LOOPS 5000
#define PHY_BUSY_LOOPS 5000
@@
-38,7
+38,7
@@
{
u32 frame_val;
unsigned int loops;
{
u32 frame_val;
unsigned int loops;
-@@ -
778,7 +780
,12 @@ static int tg3_readphy(struct tg3 *tp, i
+@@ -
817,7 +819
,12 @@ static int tg3_readphy(struct tg3 *tp, i
return ret;
}
return ret;
}
@@
-52,7
+52,7
@@
{
u32 frame_val;
unsigned int loops;
{
u32 frame_val;
unsigned int loops;
-@@ -8
27,6 +834
,11 @@ static int tg3_writephy(struct tg3 *tp,
+@@ -8
66,6 +873
,11 @@ static int tg3_writephy(struct tg3 *tp,
return ret;
}
return ret;
}
@@
-64,7
+64,7
@@
static int tg3_bmcr_reset(struct tg3 *tp)
{
u32 phy_control;
static int tg3_bmcr_reset(struct tg3 *tp)
{
u32 phy_control;
-@@ -2
263,6 +2275
,9 @@ static int tg3_nvram_read(struct tg3 *tp
+@@ -2
337,6 +2349
,9 @@ static int tg3_nvram_read(struct tg3 *tp
{
int ret;
{
int ret;
@@
-74,20
+74,20
@@
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
return tg3_nvram_read_using_eeprom(tp, offset, val);
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
return tg3_nvram_read_using_eeprom(tp, offset, val);
-@@ -2
594,8 +2609
,10 @@ static int tg3_set_power_state(struct tg
+@@ -2
668,8 +2683
,10 @@ static int tg3_set_power_state(struct tg
tg3_frob_aux_power(tp);
/* Workaround for unstable PLL clock */
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
tg3_frob_aux_power(tp);
/* Workaround for unstable PLL clock */
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
-+ if ((tp->phy_id & PHY_ID_MASK
!= PHY_ID_BCM5750_2)
&&
++ if ((tp->phy_id & PHY_ID_MASK
) != PHY_ID_BCM5750_2
&&
+ /* !!! FIXME !!! */
+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00);
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+ /* !!! FIXME !!! */
+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00);
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
-@@ -3
087,6 +3104
,14 @@ relink:
+@@ -3
161,6 +3178
,14 @@ relink:
tg3_phy_copper_begin(tp);
tg3_phy_copper_begin(tp);
@@
-102,7
+102,7
@@
tg3_readphy(tp, MII_BMSR, &tmp);
if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
(tmp & BMSR_LSTATUS))
tg3_readphy(tp, MII_BMSR, &tmp);
if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
(tmp & BMSR_LSTATUS))
-@@ -6
000,6 +6025
,11 @@ static int tg3_poll_fw(struct tg3 *tp)
+@@ -6
273,6 +6298
,11 @@ static int tg3_poll_fw(struct tg3 *tp)
int i;
u32 val;
int i;
u32 val;
@@
-114,7
+114,7
@@
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
-@@ -6
257,6 +6287
,14 @@ static int tg3_chip_reset(struct tg3 *tp
+@@ -6
550,6 +6580
,14 @@ static int tg3_chip_reset(struct tg3 *tp
tw32(0x5000, 0x400);
}
tw32(0x5000, 0x400);
}
@@
-129,7
+129,7
@@
tw32(GRC_MODE, tp->grc_mode);
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
tw32(GRC_MODE, tp->grc_mode);
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-@@ -6
409,9 +6447
,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
+@@ -6
704,9 +6742
,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
return -ENODEV;
}
return -ENODEV;
}
@@
-145,7
+145,7
@@
return 0;
}
return 0;
}
-@@ -6
474,6 +6515
,11 @@ static int tg3_load_5701_a0_firmware_fix
+@@ -6
769,6 +6810
,11 @@ static int tg3_load_5701_a0_firmware_fix
const __be32 *fw_data;
int err, i;
const __be32 *fw_data;
int err, i;
@@
-157,7
+157,7
@@
fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by
fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by
-@@ -6
533,6 +6579
,11 @@ static int tg3_load_tso_firmware(struct
+@@ -6
828,6 +6874
,11 @@ static int tg3_load_tso_firmware(struct
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
int err, i;
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
int err, i;
@@
-169,7
+169,7
@@
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
return 0;
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
return 0;
-@@ -7
444,6 +7495
,11 @@ static void tg3_timer(unsigned long __op
+@@ -7
915,6 +7966
,11 @@ static void tg3_timer(unsigned long __op
spin_lock(&tp->lock);
spin_lock(&tp->lock);
@@
-181,7
+181,7
@@
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
/* All of this garbage is because when using non-tagged
* IRQ status the mailbox/status_block protocol the chip
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
/* All of this garbage is because when using non-tagged
* IRQ status the mailbox/status_block protocol the chip
-@@ -9
217,6 +9273
,11 @@ static int tg3_test_nvram(struct tg3 *tp
+@@ -9
801,6 +9857
,11 @@ static int tg3_test_nvram(struct tg3 *tp
if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
return 0;
if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
return 0;
@@
-193,7
+193,7
@@
if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO;
if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO;
-@@ -10
010,7 +10071
,7 @@ static int tg3_ioctl(struct net_device *
+@@ -10
595,7 +10656
,7 @@ static int tg3_ioctl(struct net_device *
return -EAGAIN;
spin_lock_bh(&tp->lock);
return -EAGAIN;
spin_lock_bh(&tp->lock);
@@
-202,7
+202,7
@@
spin_unlock_bh(&tp->lock);
data->val_out = mii_regval;
spin_unlock_bh(&tp->lock);
data->val_out = mii_regval;
-@@ -10
029,7 +10090
,7 @@ static int tg3_ioctl(struct net_device *
+@@ -10
611,7 +10672
,7 @@ static int tg3_ioctl(struct net_device *
return -EAGAIN;
spin_lock_bh(&tp->lock);
return -EAGAIN;
spin_lock_bh(&tp->lock);
@@
-211,7
+211,7
@@
spin_unlock_bh(&tp->lock);
return err;
spin_unlock_bh(&tp->lock);
return err;
-@@ -1
0619,6 +10680,12 @@ static void __devinit tg3_get_57780_nvra
+@@ -1
1256,6 +11317,12 @@ static void __devinit tg3_get_5717_nvram
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void __devinit tg3_nvram_init(struct tg3 *tp)
{
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void __devinit tg3_nvram_init(struct tg3 *tp)
{
@@
-224,7
+224,7
@@
tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD <<
tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD <<
-@@ -1
0877,6 +10944
,9 @@ static int tg3_nvram_write_block(struct
+@@ -1
1516,6 +11583
,9 @@ static int tg3_nvram_write_block(struct
{
int ret;
{
int ret;
@@
-234,7
+234,7
@@
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
~GRC_LCLCTRL_GPIO_OUTPUT1);
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -12
136,6 +12205
,11 @@ static int __devinit tg3_get_invariants(
+@@ -12
801,6 +12871
,11 @@ static int __devinit tg3_get_invariants(
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
@@
-246,7
+246,7
@@
/* Get eeprom hw config before calling tg3_set_power_state().
* In particular, the TG3_FLG2_IS_NIC flag must be
* determined before calling tg3_set_power_state() so that
/* Get eeprom hw config before calling tg3_set_power_state().
* In particular, the TG3_FLG2_IS_NIC flag must be
* determined before calling tg3_set_power_state() so that
-@@ -1
2513,6 +12587
,10 @@ static int __devinit tg3_get_device_addr
+@@ -1
3190,6 +13265
,10 @@ static int __devinit tg3_get_device_addr
}
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
}
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
@@
-257,7
+257,7
@@
#ifdef CONFIG_SPARC
if (!tg3_get_default_macaddr_sparc(tp))
return 0;
#ifdef CONFIG_SPARC
if (!tg3_get_default_macaddr_sparc(tp))
return 0;
-@@ -13
004,6 +13082
,7 @@ static char * __devinit tg3_phy_string(s
+@@ -13
682,6 +13761
,7 @@ static char * __devinit tg3_phy_string(s
case PHY_ID_BCM5704: return "5704";
case PHY_ID_BCM5705: return "5705";
case PHY_ID_BCM5750: return "5750";
case PHY_ID_BCM5704: return "5704";
case PHY_ID_BCM5705: return "5705";
case PHY_ID_BCM5750: return "5750";
@@
-265,7
+265,7
@@
case PHY_ID_BCM5752: return "5752";
case PHY_ID_BCM5714: return "5714";
case PHY_ID_BCM5780: return "5780";
case PHY_ID_BCM5752: return "5752";
case PHY_ID_BCM5714: return "5714";
case PHY_ID_BCM5780: return "5780";
-@@ -13
214,6 +1329
3,13 @@ static int __devinit tg3_init_one(struct
+@@ -13
893,6 +1397
3,13 @@ static int __devinit tg3_init_one(struct
tp->msg_enable = tg3_debug;
else
tp->msg_enable = TG3_DEF_MSG_ENABLE;
tp->msg_enable = tg3_debug;
else
tp->msg_enable = TG3_DEF_MSG_ENABLE;
@@
-281,7
+281,7
@@
* swapping. DMA data byte swapping is controlled in the GRC_MODE
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
* swapping. DMA data byte swapping is controlled in the GRC_MODE
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
-@@ -1
853,6 +1853
,9 @@
+@@ -1
939,6 +1939
,9 @@
#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
@@
-291,7
+291,7
@@
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
-@@ -2
701,6 +2704
,7 @@ struct tg3 {
+@@ -2
824,6 +2827
,7 @@ struct tg3 {
#define PHY_ID_BCM5714 0x60008340
#define PHY_ID_BCM5780 0x60008350
#define PHY_ID_BCM5755 0xbc050cc0
#define PHY_ID_BCM5714 0x60008340
#define PHY_ID_BCM5780 0x60008350
#define PHY_ID_BCM5755 0xbc050cc0
@@
-299,7
+299,7
@@
#define PHY_ID_BCM5787 0xbc050ce0
#define PHY_ID_BCM5756 0xbc050ed0
#define PHY_ID_BCM5784 0xbc050fa0
#define PHY_ID_BCM5787 0xbc050ce0
#define PHY_ID_BCM5756 0xbc050ed0
#define PHY_ID_BCM5784 0xbc050fa0
-@@ -2
745,7 +2749
,7 @@ struct tg3 {
+@@ -2
868,7 +2872
,7 @@ struct tg3 {
(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
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