[package] libpcap: explicitely disable libnl support to prevent different build resul...

[openwrt.git] / target / linux / ar71xx / patches-3.3 / 601-MIPS-ath79-add-more-register-defines.patch

diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 4d948bb..74b3c83 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -68,7 +68,15 @@
  #define AR933X_PLL_CPU_CONFIG_REG     0x00
  #define AR933X_PLL_CLOCK_CTRL_REG     0x08
  
  #define AR933X_PLL_CPU_CONFIG_REG     0x00
  #define AR933X_PLL_CLOCK_CTRL_REG     0x08
  

-@@ -285,7 +305,11 @@
+@@ -165,6 +185,7 @@
+ #define AR934X_PLL_CPU_CONFIG_REG             0x00
+ #define AR934X_PLL_DDR_CONFIG_REG             0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG               0x08
++#define AR934X_PLL_ETH_XMII_CONTROL_REG               0x2c
+ 
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
+@@ -285,7 +306,11 @@

  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  


@@ -80,7 +88,7 @@
  #define AR933X_RESET_USB_HOST         BIT(5)
  #define AR933X_RESET_USB_PHY          BIT(4)
  #define AR933X_RESET_USBSUS_OVERRIDE  BIT(3)
  #define AR933X_RESET_USB_HOST         BIT(5)
  #define AR933X_RESET_USB_PHY          BIT(4)
  #define AR933X_RESET_USBSUS_OVERRIDE  BIT(3)

-@@ -323,6 +347,8 @@
+@@ -323,6 +348,8 @@

  #define AR934X_RESET_MBOX             BIT(1)
  #define AR934X_RESET_I2S              BIT(0)
  
  #define AR934X_RESET_MBOX             BIT(1)
  #define AR934X_RESET_I2S              BIT(0)
  


@@ -89,7 +97,7 @@
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)

-@@ -427,6 +453,14 @@
+@@ -427,6 +454,14 @@

  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  


@@ -104,7 +112,7 @@
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20

-@@ -434,4 +468,124 @@
+@@ -434,4 +469,124 @@

  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
  
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23