tahvo doesn't need ohci

[openwrt.git] / target / linux / ramips / files / drivers / net / ramips_esw.c

diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c
index df0873e..df567a7 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ramips_esw.c
+++ b/target/linux/ramips/files/drivers/net/ramips_esw.c
@@ -5,7 +5,7 @@
 
 #define RT305X_ESW_REG_FCT0            0x08
 #define RT305X_ESW_REG_PFC1            0x14
 
 #define RT305X_ESW_REG_FCT0            0x08
 #define RT305X_ESW_REG_PFC1            0x14

-#define RT305X_ESW_REG_PVIDC(_n)       (0x48 + 4 * (_n))
+#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))

 #define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 #define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 #define RT305X_ESW_REG_FPA             0x84
 #define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 #define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 #define RT305X_ESW_REG_FPA             0x84


@@ -28,105 +28,241 @@
 
 #define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 
 
 #define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 

+#define RT305X_ESW_PVIDC_PVID_M                0xfff
+#define RT305X_ESW_PVIDC_PVID_S                12
+
+#define RT305X_ESW_VLANI_VID_M         0xfff
+#define RT305X_ESW_VLANI_VID_S         12
+
+#define RT305X_ESW_VMSC_MSC_M          0xff
+#define RT305X_ESW_VMSC_MSC_S          8
+
+#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
+#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
+#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
+#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
+
+#define RT305X_ESW_POC1_EN_BP_S                0
+#define RT305X_ESW_POC1_EN_FC_S                8
+#define RT305X_ESW_POC1_DIS_RMC2CPU_S  16
+#define RT305X_ESW_POC1_DIS_PORT_S     23
+
+#define RT305X_ESW_POC3_UNTAG_EN_S     0
+#define RT305X_ESW_POC3_ENAGING_S      8
+#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
+
+#define RT305X_ESW_PORT0               0
+#define RT305X_ESW_PORT1               1
+#define RT305X_ESW_PORT2               2
+#define RT305X_ESW_PORT3               3
+#define RT305X_ESW_PORT4               4
+#define RT305X_ESW_PORT5               5
+#define RT305X_ESW_PORT6               6
+
+#define RT305X_ESW_PORTS_INTERNAL                                      \
+               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
+                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
+                BIT(RT305X_ESW_PORT4))
+
+#define RT305X_ESW_PORTS_NOCPU \
+               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
+
+#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
+
+#define RT305X_ESW_PORTS_ALL   \
+               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
+

 struct rt305x_esw {
        void __iomem *base;
        struct rt305x_esw_platform_data *pdata;
 struct rt305x_esw {
        void __iomem *base;
        struct rt305x_esw_platform_data *pdata;

+       spinlock_t reg_rw_lock;

 };
 
 static inline void
 };
 
 static inline void

-ramips_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
+rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)

 {
        __raw_writel(val, esw->base + reg);
 }
 
 static inline u32
 {
        __raw_writel(val, esw->base + reg);
 }
 
 static inline u32

-ramips_esw_rr(struct rt305x_esw *esw, unsigned reg)
+rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)

 {
        return __raw_readl(esw->base + reg);
 }
 
 {
        return __raw_readl(esw->base + reg);
 }
 

-u32
-mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
-             u32 write_data)
+static inline void
+rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
+                  unsigned long val)
+{
+       unsigned long t;
+
+       t = __raw_readl(esw->base + reg) & ~mask;
+       __raw_writel(t | val, esw->base + reg);
+}
+
+static void
+rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
+              unsigned long val)

 {
 {

-       unsigned long volatile t_start = jiffies;
+       unsigned long flags;
+
+       spin_lock_irqsave(&esw->reg_rw_lock, flags);
+       rt305x_esw_rmw_raw(esw, reg, mask, val);
+       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
+}
+
+static u32
+rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
+                u32 write_data)
+{
+       unsigned long t_start = jiffies;

        int ret = 0;
 
        int ret = 0;
 

-       while(1)
-       {
-               if (!(ramips_esw_rr(esw, RT305X_ESW_REG_PCR1) &
+       while (1) {
+               if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &

                      RT305X_ESW_PCR1_WT_DONE))
                        break;
                      RT305X_ESW_PCR1_WT_DONE))
                        break;

-               if(time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT))
-               {
+               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {

                        ret = 1;
                        goto out;
                }
        }
 
        write_data &= 0xffff;
                        ret = 1;
                        goto out;
                }
        }
 
        write_data &= 0xffff;

-       ramips_esw_wr(esw,
+       rt305x_esw_wr(esw,

                      (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
                      (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
                      (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
                      RT305X_ESW_REG_PCR0);
 
        t_start = jiffies;
                      (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
                      (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
                      (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
                      RT305X_ESW_REG_PCR0);
 
        t_start = jiffies;

-       while(1)
-       {
-               if (ramips_esw_rr(esw, RT305X_ESW_REG_PCR1) &
+       while (1) {
+               if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &

                    RT305X_ESW_PCR1_WT_DONE)
                        break;
                    RT305X_ESW_PCR1_WT_DONE)
                        break;

-               if(time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT))
-               {
+
+               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {

                        ret = 1;
                        break;
                }
        }
 out:
                        ret = 1;
                        break;
                }
        }
 out:

-       if(ret)
+       if (ret)

                printk(KERN_ERR "ramips_eth: MDIO timeout\n");
        return ret;
 }
 
                printk(KERN_ERR "ramips_eth: MDIO timeout\n");
        return ret;
 }
 

+static void
+rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
+{
+       unsigned s;
+
+       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
+       rt305x_esw_rmw(esw,
+                      RT305X_ESW_REG_VLANI(vlan / 2),
+                      RT305X_ESW_VLANI_VID_M << s,
+                      (vid & RT305X_ESW_VLANI_VID_M) << s);
+}
+
+static void
+rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
+{
+       unsigned s;
+
+       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
+       rt305x_esw_rmw(esw,
+                      RT305X_ESW_REG_PVIDC(port / 2),
+                      RT305X_ESW_PVIDC_PVID_M << s,
+                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
+}
+
+static void
+rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
+{
+       unsigned s;
+
+       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
+       rt305x_esw_rmw(esw,
+                      RT305X_ESW_REG_VMSC(vlan / 4),
+                      RT305X_ESW_VMSC_MSC_M << s,
+                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
+}
+

 static void
 rt305x_esw_hw_init(struct rt305x_esw *esw)
 {
        int i;
 
        /* vodoo from original driver */
 static void
 rt305x_esw_hw_init(struct rt305x_esw *esw)
 {
        int i;
 
        /* vodoo from original driver */

-       ramips_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
-       ramips_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
-       ramips_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
-       ramips_esw_wr(esw, 0x00002001, RT305X_ESW_REG_VLANI(0));
-       ramips_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
-       ramips_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
-       ramips_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
-       ramips_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
-       ramips_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
-       ramips_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2));
-       ramips_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
-       ramips_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
-
-       mii_mgr_write(esw, 0, 31, 0x8000);
-       for(i = 0; i < 5; i++)
-       {
-               mii_mgr_write(esw, i, 0, 0x3100);   //TX10 waveform coefficient
-               mii_mgr_write(esw, i, 26, 0x1601);   //TX10 waveform coefficient
-               mii_mgr_write(esw, i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
-               mii_mgr_write(esw, i, 30, 0x0018);   //TX100 slew rate control
+       rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
+       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
+       rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
+
+       /* Enable Back Pressure, and Flow Control */
+       rt305x_esw_wr(esw,
+                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
+                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
+                     RT305X_ESW_REG_POC1);
+
+       /* Enable Aging, and VLAN TAG removal */
+       rt305x_esw_wr(esw,
+                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
+                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
+                     RT305X_ESW_REG_POC3);
+
+       rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
+       rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
+
+       /* Setup SoC Port control register */
+       rt305x_esw_wr(esw,
+                     (RT305X_ESW_SOCPC_CRC_PADDING |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
+                     RT305X_ESW_REG_SOCPC);
+
+       rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
+       rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1);
+       rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
+       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
+
+       rt305x_mii_write(esw, 0, 31, 0x8000);
+       for (i = 0; i < 5; i++) {
+               /* TX10 waveform coefficient */
+               rt305x_mii_write(esw, i, 0, 0x3100);
+               /* TX10 waveform coefficient */
+               rt305x_mii_write(esw, i, 26, 0x1601);
+               /* TX100/TX10 AD/DA current bias */
+               rt305x_mii_write(esw, i, 29, 0x7058);
+               /* TX100 slew rate control */
+               rt305x_mii_write(esw, i, 30, 0x0018);

        }
        }

+

        /* PHY IOT */
        /* PHY IOT */

-       mii_mgr_write(esw, 0, 31, 0x0);      //select global register
-       mii_mgr_write(esw, 0, 22, 0x052f);   //tune TP_IDL tail and head waveform
-       mii_mgr_write(esw, 0, 17, 0x0fe0);   //set TX10 signal amplitude threshold to minimum
-       mii_mgr_write(esw, 0, 18, 0x40ba);   //set squelch amplitude to higher threshold
-       mii_mgr_write(esw, 0, 14, 0x65);     //longer TP_IDL tail length
-       mii_mgr_write(esw, 0, 31, 0x8000);   //select local register
+       /* select global register */
+       rt305x_mii_write(esw, 0, 31, 0x0);
+       /* tune TP_IDL tail and head waveform */
+       rt305x_mii_write(esw, 0, 22, 0x052f);
+       /* set TX10 signal amplitude threshold to minimum */
+       rt305x_mii_write(esw, 0, 17, 0x0fe0);
+       /* set squelch amplitude to higher threshold */
+       rt305x_mii_write(esw, 0, 18, 0x40ba);
+       /* longer TP_IDL tail length */
+       rt305x_mii_write(esw, 0, 14, 0x65);
+       /* select local register */
+       rt305x_mii_write(esw, 0, 31, 0x8000);

 
        /* set default vlan */
 
        /* set default vlan */

-       ramips_esw_wr(esw, 0x2001, RT305X_ESW_REG_VLANI(0));
-       ramips_esw_wr(esw, 0x504f, RT305X_ESW_REG_VMSC(0));
+       rt305x_esw_set_vlan_id(esw, 0, 1);
+       rt305x_esw_set_vlan_id(esw, 1, 2);
+       rt305x_esw_set_vmsc(esw, 0,
+                           (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
+                            BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
+                            BIT(RT305X_ESW_PORT6)));
+       rt305x_esw_set_vmsc(esw, 1,
+                           (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
+       rt305x_esw_set_vmsc(esw, 2, 0);
+       rt305x_esw_set_vmsc(esw, 3, 0);

 }
 
 static int
 }
 
 static int


@@ -147,7 +283,7 @@ rt305x_esw_probe(struct platform_device *pdev)
                return -ENOMEM;
        }
 
                return -ENOMEM;
        }
 

-       esw = kzalloc(sizeof (struct rt305x_esw), GFP_KERNEL);
+       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);

        if (!esw) {
                dev_err(&pdev->dev, "no memory for private data\n");
                return -ENOMEM;
        if (!esw) {
                dev_err(&pdev->dev, "no memory for private data\n");
                return -ENOMEM;


@@ -163,6 +299,7 @@ rt305x_esw_probe(struct platform_device *pdev)
        platform_set_drvdata(pdev, esw);
 
        esw->pdata = pdata;
        platform_set_drvdata(pdev, esw);
 
        esw->pdata = pdata;

+       spin_lock_init(&esw->reg_rw_lock);

        rt305x_esw_hw_init(esw);
 
        return 0;
        rt305x_esw_hw_init(esw);
 
        return 0;